VHDL RTL

.


.

(RTL)

-.

IEEE 1076.6, VHDL
Register Transfer Level .

IEEE 1076.6
VHDL


.
1999. =>
VHDL-87.
2004. =>
VHDL-2002.


:
,
boolean, bit character.
,
integer, natural i positive.

bit_vector string
std_ulogic, std_ulogic_vector, std_logic std_logic_vector,
std_logic_1164
unsigned signed, numeric_bit
unsigned signed, numeric_std

boolean bit,

std_logic std_ulogic
.

.

enum_encoding:
attribute enum_encoding : string;
:
type state is (idle, preamble, data, crc, ok, error);
attribute enum_encoding of state : type is "000 001 010 011 100 111";

.
,

:
type sample is range 64 to 63; 7-
subtype table_index is natural range 0 to 1023; 10-

231
+231 1

.
.



.
=>
.

:
type coeffs is array (3 downto 0) of integer;
type channel_states is array (0 to 7) of state; state
subtype word is bit_vector(31 downto 0);
type reg_file is array (0 to 15) of word;

:
type color is (red, green, blue);
type plane_status is array (color) of boolean;
type matrix is array (1 to 3, 1 to 3) of real; 2D, floatingpoint
type reg_file_set is array (0 to 3) of reg_file;




0 1.

-
.


.




'Z',
.
:
if request_enable = '1' then
request := ready;
else
request <= 'Z';
end if;





( ),
,
,
.
,
std_match.

 std_match
numeric_std

.

. "="

std_match .
std_match
"don't care" ('')

"don't care" .

.
status <= ready and not limit_exceeded;
status <= ready and (sample < limit);

.
:
with addr(1 downto 0) select
request <= request_a when "00",
request_b when "01",
request_c when "10",
request_d when "11";

:
request <= request_a when addr(1 downto 0) = "00" else
request_b when addr(1 downto 0) = "01" else
request_c when addr(1 downto 0) = "10" else
request_d when addr(1 downto 0) = "11";

,
.
,
.

.
data_bus <= resize(sample_byte, 16) when std_match(sample_enable, '1') else
"ZZZZZZZZZZZZZZZZ";

data_bus <= resize(sample_byte, 16) when std_match(sample_enable, '1') else

(others => 'Z');

process
,
.
read_sample : process ( read_enable, sample, limit_exceeded, ready )
begin
if std_match(read_enable, '1') then
data <= sample;
parity <= calc_parity(sample);
status <= ready and not Iimit_exceeded;
else
data <= "ZZZZZZZZ";
parity <= 'Z';
status <= 'Z';
end if;
end process read_sample;

.
, ,
.
bit, std_ulogic
std_logic.
,
bit std_ulogic .



process_statement <=
[ process_label : ] process ( clock_signal_name )
{ process_declarative_item }
begin
if clock_edge then
{ sequential_statement }
end if ;
end process [ process_label ] ;

.
=> wait
(clock-edge) .



clock_edge .

:
rising_edge( clock_signal_name )
clock_signal_name'event and clock_signal_name = '1'
clock_signal_name = '1' and clock_signal_name'event
not clock_signal_name'stable and clock_signal_name = '1'
clock_signal_name = '1' and not clock_signal_name'stable




:
falling_edge( clock_signal_name )
clock_signal_name'event and clock_signal_name = 0'
clock_signal_name = 0' and clock_signal_name'event
not clock_signal_name'stable and clock_signal_name = 0'
clock_signal_name = 0' and not clock_signal_name'stable



:
simple_reg : process ( clk )
begin
if clk'event and clk = '1' then
reg_out <= data_in;
end if;
end process simple_reg;




:
process_statement <=
[ process_label : ] process ( clock_signal_name,
asynchronous_signal_name {, ...} )
{ process_declarative_item }
begin
if boolean_expression then
{ sequential_statement }
{ elsif boolean_expression then
{ sequential_statement } }
elsif clock_edge then
{ sequential_statement }
end if;
end process [ process_label ] ;



(
)
;
then

=>
.
:
wait ,

.



:
count_byte : process ( clk, rst_n, load, load_data )
variable count : unsigned(7 downto 0);
begin
if std_match(rst_n, '0') then
count := "00000000";
q <= count;
elsif std_match(Ioad, '1') then
count := load_data;
q <= count;
elsif rising_edge(clk) then
count := count + 1;
q <= count;
end If;
end process count_byte;





!
,
.
=>
,
.



wait
:
process_statement <=
[ process_label : ] process is
{ process_declarative_item }
begin
wait on <sensitivity_list>;
if <condition> then
<sequence_of_statements>;
end if;
end process [ process_label ] ;
wait (
),
.




wait until...
Tada je za clock-edge e
:
clock_signal_name = '1'
clock_signal_name = '0
wait
,
wait .
, wait

.


reg : process is
begin
wait until reset = '1' or rising_edge(clk);
if reset = '1' then
q <= X"00";
elsif rising_edge(clk) then
if en = '1' then
q <= d;
end if;
end if;
end process dual_reg;



:
shift_reg: process
variable stored_value : bit_vector(7 downto 0);
begin
wait until clk = '1';
If load = '1' then
stored_value := load_data_in;
q <= stored_value;
else
stored_value := stored_value(6 downto 0) & serial_data_in;
q <= stored_value;
end If;
end process shift_reg;



,
. ,
,
. inferred storage.
:

latch : process ( enable, d )

begin
if enable = '1' then
q <=d;
end if;
end process latch;





VHDL-.

,

.

.

 VHDL
:


.

.

.

 VHDL :

(inertial transport)
after .

(clockedge) ,
.

 VHDL :

,


.

 VHDL
:

. 'base,
'left, 'right, 'high, 'low, 'range,
'reverse_range 'length.

.
, A'left(1) .
'event 'stable
clock-edge .

 VHDL
:
,
shift_left shift_right
numeric_bit
numeric_std.
"/", mod rem
,

.
"**"

,
2.

 VHDL
:
,
.
. :
rtl_synthesis off

rtl_synthesis on

.
VHDL
rtl_synthesis off
rtl_synthesis on .

10 VHDL

1.

VHDL-
VHDL

2.

FF
FF




FF

2.




( Enable )

3.

4.

process (state, input)
begin
case state is
when S1 =>
if input = 1 then
output <= 0;
end if;
when S2 =>
output <= 1;
end case;
end process;

process (state, input)

begin
case state is
when S1 =>
if input = 1 then
output <= 0;
else
output <= 1;
end if;
when S2 =>
output <= 1;
end case;
end process;

4.

process (state, input)
begin
case state is
when S1 =>
if input = 1 then
output <= 0;
end if;
when S2 =>
output <= 1;
end case;
end process;

process (state, input)

begin
case state is
when S1 =>
if input = 1 then
output <= 0;
else
output <= 1;
end if;
when S2 =>
output <= 1;
end case;
end process;

5.

type states is (START, RUN, IDLE, ZAPHOD);
signal current, next : states;
process (current)
begin
case current is
when START => ...
when RUN => ...
when IDLE => ...
end case;
end process;

6.
9

7.
process (Clk, Reset)
begin
if Reset = 1 then
Q <= 0;
else
if rising_edge(Clk) then
Q <= D;
end if;
end if;
end process;

process (Clk)
begin
if rising_edge(Clk) then
if Reset = 1 then
Q <= 0;
else
Q <= D;
end if;
end if;
end process;

( )

8.
,
,

9.
Z X
architecture behv of ALU is
begin
process (A,B,Sel) begin
case Sel is
when "00" =>
Res <= A + B;
when "01" =>
Res <= A + (not B) + 1;
when "1X" =>
Res <= A and B;
when "1Z" =>
Res <= A or B;
when others =>
Res <= "XX";
end case;
end process;
end behv;

architecture behv of ALU is

begin
process(A,B,Sel) begin
case Sel is
when "00" =>
Res <= A + B;
when "01" =>
Res <= A + (not B) + 1;
when "10" =>
Res <= A and B;
when "11" =>
Res <= A or B;
when others =>
Res <= "XX";
end case;
end process;
end behv;

9.
Z X
architecture behv of ALU is
begin
process (A,B,Sel) begin
case Sel is
when "00" =>
Res <= A + B;
when "01" =>
Res <= A + (not B) + 1;
when "1X" =>
Res <= A and B;
when "1Z" =>
Res <= A or B;
when others =>
Res <= "XX";
end case;
end process;
end behv;

architecture behv of ALU is

begin
process(A,B,Sel) begin
case Sel is
when "00" =>
Res <= A + B;
when "01" =>
Res <= A + (not B) + 1;
when "10" =>
Res <= A and B;
when "11" =>
Res <= A or B;
when others =>
Res <= "XX";
end case;
end process;
end behv;

10.
wait

wait 20ns