Write VHDL code for 8 bit parity generator (with for loop and generic stat events) Aim

: Write VHDL code for 8 bit parity generator (with for loop and generic stat events). CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity pairity is generic(n:integer:=7); port(a:in std_logic_vector(n-1 downto 0); b:out std_logic_vector(n downto 0)); end pairity; architecture Behavioral of pairity is begin process(a) variable temp1:std_logic; variable temp2:std_logic_vector(b'range); begin temp1:='0'; for i in a'range loop temp1:=temp1 xor a(i); temp2(i):=a(i); end loop; temp2(b'high):=temp1; b<=temp2; end process; end Behavioral;