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16 LP_0 LP_1 Inv_CLK Ep Cp 8 " Lm 16 8 O&'_1 O&'_( Eu !

u E+ E+1 Inv_CLK

PROGRAM COUNTER

W bus
8 16

L%

A REGI#TER

Inv_CLK E%

,LAG DI#PLA) -

,LAG REGI#TER

MAR INPUT
16 8
inv_clK Clock mode

ARIT!METIC $ LOGIC UNIT

16 8

8 L' E'_ E'_1 Inv_CLK 8

RUN mode

8_U Inv_CLK Lr Er

TEMPORAR) REGI#TER

RAM

8 Lmd Lmd1 8_U 8

" REGI#TER

L* E* Inv_CLK

MDR
Emd Emd1 8 16

C& Cd

#TACK

En Inv_CLK

Li !LT

CLK Inv_CLK

IN#TRUCTION REGI#TER $ CONTROLLER

8 O&'
clock_mode RUN mode

OUTPUT REGI#TER
8

Inv_CLK

29 CONTROL "U#

DI#PLA)

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