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Code: 9D57101/9D57101b M.Tech - Semester Supplementary Examinations, November 2012 VLSI TECHNOLOGY (Common to VLSIS, VLSISD, VLSI, VLSID and ES) Time: 3 hours Max Marks: 60 Answer any FIVE questions All questions carry equal marks ***** 1 (a) (b) 2 (a) (b) 3 (a) (b) 4 (a) (b) 5 (a) (b) 6 (a) (b) 7 (a) (b) 8 (a) (b) Illustrate the main steps in a typical n-well process. Compare CMOS and Bi-CMOS. Define V t , G m and G ds . Discuss the electrical properties of MOS circuits. Write short notes on MOS inverter. Discuss the wiring capacitances.

Differentiate switch logic and gate logic. List the salient features of subsystem lay out.

What are the various simulators used for combinational logic? Write short notes on power optimization of combinational logic networks. Explain the method of design validation and testing in sequential system. Write short notes on clocking discipline. Give the salient features of SOCs. List the steps involved in architecture testing. With an example give the method involved in chip design. Discuss the steps involved in software co-design.

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