bit 7-6 Unimplemented: Read as 0 bit 5-4 DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 fo CCP Module

! Capture mode: "nused# Compare mode: "nused# PWM mode: $%ese bits a e t%e t&o 'east (i)nificant bits *bit 1 and bit 0+ of t%e 10-bit PWM duty cycle# $%e ei)%t Most (i)nificant bits *DC!,-:./+ of t%e duty cycle a e found in CCPR!'# bit 0-0 CCPxM<3:0>: CCP Module ! Mode (elect bits 0000 1 Ca2tu e3Co42a e3PWM disabled5 esets CCP! 4odule 0001 1 Rese 6ed 0010 1 Co42a e 4ode7 to))le out2ut on 4atc%5 CCP!89 bit is set 0011 1 Rese 6ed 0100 1 Ca2tu e 4ode7 e6e y fallin) ed)e 0101 1 Ca2tu e 4ode7 e6e y isin) ed)e 0110 1 Ca2tu e 4ode7 e6e y 4t% isin) ed)e 0111 1 Ca2tu e 4ode7 e6e y 16t% isin) ed)e 1000 1 Co42a e 4ode7 initiali:e CCP! 2in lo&5 on co42a e 4atc%7 fo ce CCP! 2in %i)%5 CCP!89 bit is set 1001 1 Co42a e 4ode7 initiali:e CCP! 2in %i)%5 on co42a e 4atc%7 fo ce CCP! 2in lo&5 CCP!89 bit is set 1010 1 Co42a e 4ode7 )ene ate soft&a e inte u2t on co42a e 4atc%5 CCP!89 bit is set5 CCP! 2in eflects 83; state 1011 1 Co42a e 4ode7 t i))e s2ecial e6ent5 CCP!89 bit is set7 CCP! 2in is unaffected *9o t%e effects of t%e t i))e 7 see Section 17.3. !Special "#ent $ri%%er&#+ 11xx 1 PWM 4ode

PWM Period = [(PR2) + 1] 4 TOSC (TMR2 Prescale Value) PWM Du ! C!cle = (CCPR"#$CCP"CO%&'$4() TOSC (TMR2 Prescale Value)