Half adder: module halfadder(sum,carry,a,b); input a,b; output sum,carry; xor(sum,a,b); and(carry,a,b); endmodule

Output:

Full adder: module fulladder(a,b,c,sum,carry); input a,b,c; output sum,carry; wire d,e,f,g; xor(d,a,b); xor(sum,d,c); and(e,a,b); and(f,c,b); and(g,a,c); or(carry,e,f,g); endmodule

Output:

Half subtractor: module halfsubtractor(difference,borrow,a,b); input a,b; output difference,borrow; wire c; xor(difference,a,b); not(c,a); and(borrow,c,b); endmodule

Output:

Full subtractor: module fullsubtractor(borrow,diff,a,b,c); input a,b,c; output diff,borrow; wire d,e,f,g,h; xor(d,a,b); not(g,a); and(e,g,b); xor(diff,d,c); not(h,d); and(f,h,c); or(borrow,f,e); endmodule Output:

Multiplexer: module mux(y,s0,s1,d0,d1,d2,d3); input s0,s1,d0,d1,d2,d3; output y; wire a,b,c,d,e,f,g,h; not(a,s0); not(b,s1); and(c,d0,a,b); and(d0,d1,s0,d); or(g,c,d); and(e,d2,a1,s1); and(f,a3,s0,s1); or(h,e,f); or(y,g,h); endmodule Output:

Demultiplexer: module demux(d0,d1,d2,d3,s0,s1,i); input s0,s1,i; output d0,d1,d2,d3; wire a,b; not(a,s0); not(b,s1); and(d0,i,a,b); and(d1,i,b,s0); and(d2,i,s1,a); and(d3,i,s0,s1); endmodule Output:

Counter: module counter(q,clk,clear); output[3:0]q; input clk,clear; reg[3:0]q; always@(posedge clear or negedge clk) begin if(clear) q<=4'b0; else q<=q+1; end endmodule Output:

Shift Registers: Serial In Serial Out: module siso(sout,clk,rst,sin); output sout; input clk,rst,sin; reg [3:0]q; reg sout; always@(posedge clk) begin if(rst) begin q<=4'b0; sout<=1'b0; end else {sout,q}<={q[3],q[2:0],sin}; end endmodule Output:

Shift Registers: Serial In Parallel Out: module sipo(pout,clk,rst,sin); output [3:0]pout; input clk,rst,sin; reg [3:0]s; reg [3:0]pout; always@(posedge clk) begin if(rst) begin s<=4'b0; pout<=4'b0; end else begin s<={s[2:0],sin}; pout<=s; end end endmodule Output: