1

U1D
J3
3P0J303
TX+

17

P0U1D017

TD+

TX+

R7
3VDD3

P0R702

3VDD3

R 0.0499K
A

5P0J305
C7

R8
P0R801

P0C701 P0C702

R 0.0499K

16

P0U1D016

TD-

P0R802

C10
GND

GND

P0C1002 P0C1001

0.1UF

0.1UF

4P0J304

14

TX-

7P0J307
RX+

P0U1D014

RD+

CT1

TXTRANSMITTER
RX+

R9
P0R901

3VDD3

P0R902

3VDD3

R 0.0499K

6P0J306
C8

R10
P0R1001

RD-

P0R1002

P0C801 P0C802

R 0.0499K

13

P0U1D013

C9
GND

GND

P0C901

0.1UF

CABLE SIDE

P0R701

CT2

P0C902

0.1UF

8P0J308

RX-

RXRECIEVER

Ethernet transceiver

N0L102
L1-2

P0J301

N0L101
L1-1

P0J302

N0L202
L2-2

P0J3012

N0L201
L2-1

P0J3011

12
11

13P0J3013
GND

GND

RJ-45 CONNECTOR

U1E
U1F
X1
C
X2
MDC

34

N0FPGA0CLK
FPGA_CLK

P0U1E034

P0U1F040

LED_CFG/CRS/CRS_DV

33

P0U1E033

P0U1F028

31
30

N0MDIO
MDIO

RESET_N

P0R401

P0R402

3VDD3

R 1K5

29

LED_ACT/COL/AN_EN
25MHz_OUT

R3
P0R301

GND

P0R302

P0R1101

25

P0R1201

P0R1501

R 110R
P0R1202

R16

P0LED301

P0R1601

P0R1301

R17
N0PWR0DOWN/INT
PWR_DOWN/INT
P0R1701

P0R1702

3VDD3

R 1K5

Ethernet transceiver

C1
10UF 6V
P0C301 P0C302

7P0U1E07

C2
0.1UF

P0C401 P0C402

LED 0603
C4
0.1UF

P0R1602

R 110R

R13
P0C101

P0R1502

R 2K2

23

P0C201 P0C202

R15

P0U1E023

2P0C102

PWR_DOWN/INT

P0R1102

R12

18

3VDD3

P0R1402

R 110R

N0L202
L2-2

LED3

P0U1E018

PFBIN1

P0R1401

R 2K2

P0LED302

PFBINOUT

R14

R11

P0U1E037

PFBIN2

C
N0L102
L1-2

Ethernet transceiver

R 4K87

37

N0L101
L1-1

N0L201
L2-1

P0U1F025

24

28

26

P0U1F026

N0ETHERNET0RESET
ETHERNET_RESET

P0U1E029

P0U1E024

RBIAS

LED_SPEED/AN1

R4

N0CRS/CRS0DV
CRS/CRS_DV

27

P0U1F027

P0U1E030

MDIO

LED_LINK/AN0

N0MDC
MDC

P0U1E031

40

P0R1302

R 2K2

Title

C3
0.1UF

Size

D
Number

Revision

A4
Date:
File:
1

27/05/2006
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E:\PROJECT_ARCHIVES\..\ETHERNET_SCHEMATIC.SCHDOC
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4

GND
J1

J2
1

U1A

P0J101

PWR

P0J102

PWR

PWR

N0ETHERNET0RESET
ETHERNET_RESET

N0PWR0DOWN/INT
PWR_DOWN/INT

N0RXD4
RXD4

N0RXD3
RXD3

N0RXD2
RXD2

N0RXD1
RXD1

N0COL
COL

10

N0RX0ER
RX_ER

11

N0RX0DV
RX_DV

P0J104

P0J105

P0J106

6
7
8

P0J107

P0J108

P0J109

9
10
11
B
12

P0J1010

P0J1011

12

19 P0U1A019
AGND

N0MDIO
MDIO

N0MDC
MDC

N0CRS/CRS0DV
CRS/CRS_DV

N0TXD3
TXD3

N0TXD2
TXD2

35

P0U1A035

N0TXD1
TXD1

47

P0U1A047

N0TXD0
TXD0

10

N0TX0EN
TX_EN

11

N0TX0CLK
TX_CLK

P0J203

P0J204

P0J205

P0J206

6
7
8

P0J207

P0J208

P0J209

9
10
11

N0RX0CLK
RX_CLK

P0J1012

12

13

P0J1013

PWR

15 P0U1A015
AGND

P0J202

P0J103

P0J201

PWR

P0J2010

P0J2011

A
22

P0U1A022

AVDD33

36 P0U1A036
DGND

IOGND
IOGND
P0U1A032

IOVDD33
P0U1A048

IOVDD33

32
48

Ethernet transceiver
12

N0FPGA0CLK
FPGA_CLK

P0J2012

3VDD3

13

P0J2013

PWR

HDR_11X1_2MM54 + PWR

HDR_11X1_2MM54 + PWR

GND

3VDD3

U1B
P0U1B021

RESERVED

P0U1B020

RESERVED
C

12

P0U1B011

11

P0U1B010

10

P0U1B09

P0U1B08

RESERVED
RESERVED
U1G

RESERVED
P0U1G046

46

N0RXD4
RXD4

P0U1G045

45

N0RXD3
RXD3

P0U1G044

44

N0RXD2
RXD2

P0U1G043

43

N0RXD1
RXD1

42

N0COL
COL

41

N0RX0ER
RX_ER

39

N0RX0DV
RX_DV

RXD_4/PHYAD4
U1C

RXD_3/PHYAD3

TXD_3/SNI_MODE

N0TXD3
TXD3

N0TXD2
TXD2

N0TXD1
TXD1

N0TXD0
TXD0

N0TX0EN
TX_EN

P0U1C06

P0U1C05

TXD_2

P0U1C04

TXD_1
D

P0U1C03

TXD_0

P0U1C02

TX_EN

P0U1C01

TX_CLK
Ethernet transceiver

N0TX0CLK
TX_CLK

RXD_2/PHYAD2
RXD_1/PHYAD1
P0U1G042

COL/PHYAD0
P0U1G041

RX_ER/MDIX_EN
P0U1G039

RX_DV/MII_MODE

RESERVED

38

R1
P0R101

P0R202

3VDD3

R 2K2
3VDD3

P0R102

R 2K2

Title

N0RX0CLK
RX_CLK

D
Number

Revision

A4

Ethernet transceiver
1

P0R201

Ethernet transceiver

Size

P0U1G038

RX_CLK

20

P0U1B012

RESERVED

R2

21

Date:
File:
3

27/05/2006
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E:\PROJECT_ARCHIVES\..\TO-BOARD.SCHDOC
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