PCB Layout Tutorial e

PCB Design Tutorial
by David L. Jones
Email: david AT alternatezone DOT com
Revision A - June 29th 2004

The latest version of this tutorial can e found throu!h www.alternatezone.com
Freely distributable for educational and personal use. Copyright 2004 David L. Jones
PC Design !utorial by David L. Jones "ntroduction............................................................................................................................................................................ 4 !he #ld Days...................................................................................................................................................................... 4 PC Pac$ages..................................................................................................................................................................... 4 %tandards............................................................................................................................................................................ 4 !he %che&atic.................................................................................................................................................................... ' "&perial and (etric............................................................................................................................................................ ' )or$ing to *rids................................................................................................................................................................ + )or$ing fro& the top......................................................................................................................................................... , !rac$s................................................................................................................................................................................. , Pads..................................................................................................................................................................................... .ias..................................................................................................................................................................................... Polygons.............................................................................................................................................................................. Clearances........................................................................................................................................................................... / Co&ponent Place&ent 0 Design.........................................................................................................................................10 asic 2outing.................................................................................................................................................................... 12 Finishing !ouches............................................................................................................................................................14 %ingle %ided Design.........................................................................................................................................................14 Double %ided Design........................................................................................................................................................ 1' #ther Layers......................................................................................................................................................................... 1' %il$screen.......................................................................................................................................................................... 1' %older (as$...................................................................................................................................................................... 1' (echanical Layer............................................................................................................................................................. 1+ 3eepout............................................................................................................................................................................. 1+ Layer 4lign&ent............................................................................................................................................................... 1+ 5etlists.............................................................................................................................................................................. 1+ 2ats 5est........................................................................................................................................................................... 1+
Design 2ule Chec$ing...................................................................................................................................................... 1, For6ard and ac$ 4nnotation.........................................................................................................................................1, (ulti layer Design............................................................................................................................................................ 1, Po6er Planes..................................................................................................................................................................... 1*ood *rounding............................................................................................................................................................... 20 *ood ypassing................................................................................................................................................................ 20 7igh Fre8uency Design !echni8ues................................................................................................................................20 Double %ided Loading...................................................................................................................................................... 21 4uto 2outing ...................................................................................................................................................................21 4uto Place&ent................................................................................................................................................................. 22 Design For (anufacturing................................................................................................................................................... 22 Panelisation......................................................................................................................................................................22 !ooling %trips................................................................................................................................................................... 22 Fiducial (ar$s.................................................................................................................................................................. 22 !her&al 2elief.................................................................................................................................................................. 29 %oldering........................................................................................................................................................................... 29 asic PC (anufacture...................................................................................................................................................24 Page 2 of 2+ 2
PC Design !utorial by David L. Jones %urface Finishies..............................................................................................................................................................2' :lectrical !esting.............................................................................................................................................................. 2' %ignature........................................................................................................................................................................... 2' %ub&itting your design for &anufacture.........................................................................................................................2+
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PC Design !utorial by David L. Jones
Introduction
"ou#ve desi!ned $our circuit% &erha&s even read oarded a 'or(in! &rotot$&e% and no' it#s time to turn it into a nice )rinted *ircuit +oard ,)*+- desi!n. .or some desi!ners% the )*+ desi!n 'ill e a natural and eas$ e/tension of the desi!n &rocess. +ut for man$ others the &rocess of desi!nin! and la$in! out a )*+ can e a ver$ dauntin! tas(. There are even ver$ e/&erienced circuit desi!ners 'ho (no' ver$ little a out )*+ desi!n% and as such leave it u& to the 0e/&ert0 s&ecialist )*+ desi!ners. 1an$ com&anies even have their o'n dedicated )*+ desi!n de&artments. This is not sur&risin!% considerin! that it often ta(es a !reat deal of (no'led!e and talent to &osition hundreds of com&onents and thousands of trac(s into an intricate ,some sa$ artistic- desi!n that meets a 'hole host of &h$sical and electrical re2uirements. )ro&er )*+ desi!n is ver$ often an inte!ral &art of a desi!n. 3n man$ desi!ns ,hi!h s&eed di!ital% lo' level analo! and 4. to name a fe'- the )*+ la$out ma$ ma(e or rea( the o&eration and electrical &erformance of the desi!n. 3t must e remem ered that )*+ traces have resistance% inductance% and ca&acitance% 5ust li(e $our circuit does. This article is &resented to ho&efull$ ta(e some of the m$ster$ out of )*+ desi!n. 3t !ives some advice and 6rules of thum 7 on ho' to desi!n and la$ out $our )*+s in a &rofessional manner. 3t is% ho'ever% 2uite difficult to tr$ and 6teach7 )*+ desi!n. There are man$ asic rules and !ood &ractices to follo'% ut a&art from that )*+ desi!n is a hi!hl$ creative and individual &rocess. 3t is li(e tr$in! to teach someone ho' to &aint a &icture. Ever$one 'ill have their o'n uni2ue st$le% 'hile some &eo&le ma$ have no creative flair at all8 3ndeed% man$ )*+ desi!ners li(e to thin( of )*+ la$outs as 'or(s of art% to e admired for their eaut$ and ele!ance. 63f it loo(s !ood% it9ll 'or( !ood.7 is an old catch &hrase. Lets have a !o shall 'e...
The Old Days

+ac( in the &re:com&uter *AD da$s% )*+s 'ere desi!ned and laid out $ hand usin! adhesive ta&es and &ads on clear draftin! film. 1an$ hours 'ere s&ent slouched over a fluorescent li!ht o/% cuttin!% &lacin!% ri&&in! u&% and routin! trac(s $ hand. +isho& ;ra&hics% Letraset% and even Dalo &ens 'ill e names that evo(e fond% or not so fond memories. Those da$s are 'ell and trul$ !one% 'ith com&uter ased )*+ desi!n havin! re&laced this method com&letel$ in oth ho $ist and &rofessional electronics. *om&uter ased *AD &ro!rams allo' the utmost in fle/i ilit$ in oard desi!n and editin! over the traditional techni2ues. <hat used to ta(e hours can no' e done in seconds.
PCB Packages
There are man$ )*+ desi!n &ac(a!es availa le on the mar(et% a fe' of 'hich are free'are% share'are% or limited com&onent full versions. )rotel is the defacto industr$ standard &ac(a!e in Australia. )rofessionals use the e/&ensive hi!h end <indo's ased &ac(a!es such as 99=E and D>). ?o $ists use the e/cellent free'are DO= ased )rotel AutoTra/ &ro!ram% 'hich 'as% once u&on a time% the hi!h:end &ac(a!e of choice in Australia. *onfusin!l$% there is no' another <indo's ased &ac(a!e also called AutoTra/ EDA. This is in no 'a$ related to the )rotel soft'are. This article does not focus on the use of an$ one &ac(a!e% so the information can e a&&lied to almost an$ )*+ &ac(a!e availa le. There is ho'ever% one distinct e/ce&tion. @sin! a )*+ onl$ &ac(a!e% 'hich does not have schematic ca&a ilit$% !reatl$ limits 'hat $ou can do 'ith the &ac(a!e in the &rofessional sense. 1an$ of the more advanced techni2ues to e descri ed later re2uire access to a com&ati le schematic editor &ro!ram. This 'ill e e/&lained 'hen re2uired.
Standards
There are industr$ standards for almost ever$ as&ect of )*+ desi!n. These standards are controlled $ the former 3nstitute for 3nterconnectin! and )ac(a!in! Electronic *ircuits% 'ho are no' (no'n sim&l$ as the 3)* ,'''.i&c.or!-. There is an 3)* standard for ever$ as&ect of )*+ desi!n% manufacture% testin!% and an$thin! else that $ou could ever need. The ma5or document that covers )*+ desi!n is 3)*:222A% 6;eneric =tandard on )rinted +oard Desi!n7. This standard su&erseded the old 3)*:D:2BC standard ,also 1ilitar$ =td 2BC- 'hich has een used for the last half centur$. Local countries also have their o'n various standards for man$ as&ects of )*+ desi!n and manufacture% ut $ and lar!e the 3)* standards are the acce&ted industr$ standard around the 'orld.
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PC Design !utorial by David L. Jones )rinted *ircuit +oards are also (no'n ,some 'ould sa$% more correctl$ (no'n- as )rinted <irin! +oards% or sim&l$ )rinted +oards. +ut 'e 'ill settle on the more common term )*+ for this article.
The Schematic
+efore $ou even e!in to la$ out $our )*+% $ou 1@=T have a com&lete and accurate schematic dia!ram. 1an$ &eo&le 5um& strai!ht into the )*+ desi!n 'ith nothin! more than the circuit in their head% or the schematic dra'n on loose &ost:it notes 'ith no &in num ers and no order. This 5ust isn9t !ood enou!h% if $ou don9t have an accurate schematic then $our )*+ 'ill most li(el$ end u& a mess% and ta(e $ou t'ice as lon! as it should. 6;ar a!e:in% !ar a!e:out7 is an often used 2uote% and it can a&&l$ e2uall$ 'ell to )*+ desi!n. A )*+ desi!n is a manufactured version of $our schematic% so it is natural for the )*+ desi!n to e influenced $ the ori!inal schematic. 3f $our schematic is neat% lo!ical and clearl$ laid out% then it reall$ does ma(e $our )*+ desi!n 5o a lot easier. ;ood &ractice 'ill have si!nals flo'in! from in&uts at the left to out&uts on the ri!ht. <ith electricall$ im&ortant sections dra'n correctl$% the 'a$ the desi!ner 'ould li(e them to e laid out on the )*+. Li(e &uttin! $&ass ca&acitors ne/t to the com&onent the$ are meant for. Little notes on the schematic that aid in the la$out are ver$ useful. .or instance% 6this &in re2uires a !uard trac( to si!nal !round7% ma(es it clear to the &erson la$in! out the oard 'hat &recautions must e ta(en. Even if it is $ou 'ho desi!ned the circuit and dre' the schematic% notes not onl$ remind $ourself 'hen it comes to la$in! out the oard% ut the$ are useful for &eo&le revie'in! the desi!n. "our schematic reall$ should e dra'n 'ith the )*+ desi!n in mind. 3t is outside the sco&e of this article to !o into details on !ood schematic desi!n% as it 'ould re2uire a com&lete article in its o'n ri!ht.
Imperial and Metric

The first thin! to (no' a out )*+ desi!n is 'hat measurement units are used and their common terminolo!ies% as the$ can e a'full$ confusin!8 As an$ lon! time )*+ desi!ner 'ill tell $ou% $ou should al'a$s use im&erial units ,i.e. inches- 'hen desi!nin! )*+s. This isn9t 5ust for the sa(e of nostal!ia% althou!h that is a ma5or reason8 The ma5orit$ of electronic com&onents 'ere ,and still are- manufactured 'ith im&erial &in s&acin!. =o this is no time to !et stu orn and refuse to use an$thin! ut metric units% metric 'ill ma(e la$in! out of $our oard a lot harder and a lot messier. 3f $ou are $oun! enou!h to have een raised in the metric a!e then $ou had etter start learnin! 'hat inches are all a out and ho' to convert them. An old sa$in! for )*+ desi!n is 6thou shall use thous7. A tad confusin! until $ou (no' 'hat a 6thou7 is. A 6thou7 is ADA000th of an inch% and is universall$ used and reco!nised $ )*+ desi!ners and manufacturers ever$'here. =o start &racticin! s&ea(in! in terms of 6A0 thou s&acin!7 and 62C thou !rid7% $ou9ll sound li(e a &rofessional in no time8 Eo' that $ou understand 'hat a thou is% 'e9ll thro' another s&anner in the 'or(s 'ith the term 6mil7 ,or 6mils7-. A 6mil7 is the same as A thou% and is EOT to e confused 'ith the millimeter ,mm-% 'hich is often s&o(en the same as 6mil7. The term 6mil7 comes from A thou ein! e2ual to A mili inch. As a !eneral rule avoid the use of 6mil7 and stic( to 6thou7% it9s less confusin! 'hen tr$in! to e/&lain )*+ dimensions to those metricated non:)*+ &eo&le. =ome )*+ desi!ners 'ill tell $ou not to use metric millimeters for AE"T?3E; to do 'ith a )*+ desi!n. 3n the &ractical 'orld thou!h% $ou9ll have to use oth im&erial inches ,thous- and the metric millimeter ,mm-. =o 'hich units do $ou use for 'hatF As a !eneral rule% use thous for trac(s% &ads% s&acin!s and !rids% 'hich are most of $our asic 6desi!n and la$out7 re2uirements. Onl$ use mm for 6mechanical and manufacturin!7 t$&e re2uirements li(e hole sizes and oard dimensions. "ou 'ill find that man$ )*+ manufacturers 'ill follo' these asic !uidelines also% for 'hen the$ as( $ou to &rovide details for a 2uote to manufacture $our oard. 1ost manufacturers use metric size drills% so s&ecif$in! im&erial size holes reall$ is counter&roductive and can e &rone to errors. Just to confuse the issue even further% there are man$ com&onents ,ne' surface mount &arts are an e/am&le- 'hich have metric &in s&acin! and dimensions. =o $ou9ll often have to desi!n some com&onent foot&rints usin! metric !rids and &ads. 1an$ com&onent datasheets 'ill also have metric dimensions even thou!h the s&acin! are desi!ned to an im&erial !rid. 3f $ou see a 6'eird7 metric dimension li(e A.2Bmm in a com&onent% $ou can e &rett$ sure it actuall$ has a nice round im&erial e2uivalent. 3n this case A.2Bmm is C0
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thou. "es% )*+ desi!n can e confusin!8 =o 'hatever it is $ou have to do in )*+ desi!n $ou9ll need to ecome an e/&ert at im&erial to metric conversion% and vice:versa. To ma(e $our life easier thou!h% all the ma5or )*+ draftin! &ac(a!es have a sin!le 6hot (e$7 to convert et'een im&erial and metric units instantl$ ,6G7 on )rotel for instance-. 3t 'ill hel& $ou !reatl$ if $ou memorise a fe' (e$ conversions% li(e 100 thou (0.1 inch) = 2.54mm% and 200 thou (0.2 inch) = 5.08mm etc Halues of A00 thou and a ove are ver$ often e/&ressed in inches instead of thous. =o 0.2 inch is more commonl$ used than 200thou. A inch is also commonl$ (no'n as A 6&itch7. =o it is common to hear the &hrase 60.A inch &itch7% or more sim&l$ 60.A &itch7 'ith the inches units ein! assumed. This is often used for &in s&acin! on com&onents. A00 thou is a asic 6reference &oint7 for all as&ects of )*+ desi!n% and a vast arra$ of common com&onent lead s&acin! are multi&les or fractions of this asic unit. C0 and 200 thou are the most common. Alon! 'ith the rest of the 'orld% the 3)* standards have all een metricated% and onl$ occasionall$ refer to im&erial units. This hasn9t reall$ converted the )*+ industr$ thou!h. Old ha its die hard% and im&erial still rei!ns su&reme in man$ areas of &ractical usa!e.
Working to Grids
The second ma5or rule of )*+ desi!n% and the one most often missed $ e!inners% is to la$ out $our oard on a fi/ed !rid. This is called a 6sna& !rid7% as $our cursor% com&onents and trac(s 'ill 6sna&7 into fi/ed !rid &ositions. Eot 5ust an$ size !rid mind $ou% ut a fairl$ coarse one. A00 thou is a standard &lacement !rid for ver$ asic throu!h hole 'or(% 'ith C0 thou ein! a standard for !eneral trac(in! 'or(% li(e runnin! trac(s et'een throu!h:hole &ads. .or even finer 'or( $ou ma$ use a 2C thou sna& !rid or even lo'er. 1an$ desi!ners 'ill ar!ue over the merits of a 20 thou !rid vs a 2C thou !rid for instance. 3n &ractice% 2C thou is often more useful as it allo's $ou to !o e/actl$ half 'a$ et'een C0 thou s&aced &ads. <h$ is a coarse sna& !rid so im&ortantF 3t9s im&ortant ecause it 'ill (ee& $our com&onents neat and s$mmetricalI aestheticall$ &leasin! if $ou ma$. 3t9s not 5ust for aesthetics thou!h : it ma(es future editin!% dra!!in!% movement and ali!nment of $our trac(s% com&onents and loc(s of com&onents easier as $our la$out !ro's in size and com&le/it$. A ad and amateurish )*+ desi!n is instantl$ reco!nisa le% as man$ of the trac(s 'ill not line u& e/actl$ in the center of &ads. Little its of trac(s 'ill e 6tac(ed7 on to fill in !a&s etc. This is the result of not usin! a sna& !rid effectivel$. ;ood )*+ la$out &ractice 'ould involve $ou startin! out 'ith a coarse !rid li(e C0 thou and usin! a &ro!ressivel$ finer sna& !rid if $our desi!n ecomes 6ti!ht7 on s&ace. Dro& to 2C thou and A0 thou for finer routin! and &lacement 'hen needed. This 'ill do 99J of oards. 1a(e sure the finer !rid $ou choose is a nice even division of $our standard A00 thou. This means C0% 2C% 20% A0% or C thou. Don9t use an$thin! else% $ou9ll re!ret it. A !ood )*+ &ac(a!e 'ill have hot(e$s or &ro!ramma le macro (e$s to hel& $ou s'itch et'een different sna& !rid sizes instantl$% as $ou 'ill need to do this often. There are t'o t$&es of !rids in a )*+ draftin! &ac(a!e% a sna& !rid as discussed% and a 6visi le7 !rid. The visi le !rid is an o&tional on:screen !rid of solid or dashed lines% or dots. This is dis&la$ed as a ac(!round ehind $our desi!n and hel&s $ou !reatl$ in linin! u& com&onents and trac(s. "ou can have the sna& !rid and visi le !rid set to different units ,metric or im&erial-% and this is often ver$ hel&ful. 1an$ desi!ners &refer a A00 thou visi le !rid and rarel$ var$ from that. =ome &ro!rams also have 'hat is called an 6Electrical7 !rid. This !rid is not visi le% ut it ma(es $our cursor 6sna&7 onto the center of electrical o 5ects li(e trac(s and &ads% 'hen $our cursor !ets close enou!h. This is e/tremel$ useful for manual routin!% editin! and movin! o 5ects. One last t$&e of !rid is the 6*om&onent7 !rid. This 'or(s the same as the sna& !rid% ut it9s for com&onent movement onl$. This allo's $ou to ali!n com&onents u& to a different !rid. 1a(e sure $ou ma(e it a multi&le of $our =na& !rid. <hen $ou start la$in! out $our first oard% sna& !rids can feel a it 6funn$7% 'ith $our cursor onl$ ein! a le to e moved in ste&s. @nli(e normal &aint t$&e &ac(a!es 'hich ever$one is familiar 'ith. +ut it9s eas$ to !et used to% and $our )*+ desi!ns 'ill e one ste& closer to ein! neat and &rofessional.
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Working from the top

)*+ desi!n is al'a$s done loo(in! from the to& of $our oard% loo(in! throu!h the various la$ers as if the$ 'ere trans&arent. This is ho' all the )*+ &ac(a!es 'or(. The onl$ time $ou 'ill loo( at $our oard from the ottom is for manufacturin! or chec(in! &ur&oses. This 6throu!h the oard7 method means that $ou 'ill have to !et used to readin! te/t on the ottom la$ers as a mirror ima!e% !et used to it8
Tracks
There is no recommended standard for trac( sizes. <hat size trac( $ou use 'ill de&end u&on ,in order of im&ortance- the electrical re2uirements of the desi!n% the routin! s&ace and clearance $ou have availa le% and $our o'n &ersonal &reference. Ever$ desi!n 'ill have a different set of electrical re2uirements 'hich can var$ et'een trac(s on the oard. All ut asic non:critical desi!ns 'ill re2uire a mi/ture of trac( sizes. As a !eneral rule thou!h% the i!!er the trac( 'idth% the etter. +i!!er trac(s have lo'er D* resistance% lo'er inductance% can e easier and chea&er for the manufacturer to etch% and are easier to ins&ect and re'or(. The lo'er limit of $our trac( 'idth 'ill de&end u&on the 6trac(Ds&ace7 resolution that $our )*+ manufacturer is ca&a le of. .or e/am&le% a manufacturer ma$ 2uote a A0DK trac(Ds&ace fi!ure. This means that trac(s can e no less than A0 thou 'ide% and the s&acin! et'een trac(s ,or &ads% or an$ &art of the co&&er- can e no less than K thou. The fi!ures are almost al'a$s 2uoted in thou9s% 'ith trac( 'idth first and then s&acin!. 4eal 'orld t$&ical fi!ures are A0DA0 and KDK for asic oards. The 3)* standard recommends 4thou as ein! a lo'er limit. Once $ou !et to Lthou trac(s and elo' thou!h% $ou are !ettin! into the serious end of the usiness% and $ou should e consultin! $our oard manufacturer first. The lo'er the trac(Ds&ace fi!ure% the !reater care the manufacturer has to ta(e 'hen ali!nin! and etchin! the oard. The$ 'ill &ass this cost onto $ou% so ma(e sure that $ou don9t !o an$ lo'er than $ou need to. As a !uide% 'ith 6home made7 )*+ manufacturin! &rocesses li(e laser &rinted trans&arencies and &re:coated &hoto resist oards% it is &ossi le to easil$ !et A0DA0 and even KDK s&acin!. Just ecause a manufacturer can achieve a certain trac(Ds&acin!% it is no reason to 6&ush the limits7 'ith $our desi!n. @se as i! a trac(Ds&acin! as &ossi le unless $our desi!n &arameters call for somethin! smaller. As a start% $ou ma$ li(e to use sa$ 2C thou for si!nal trac(s% C0 thou for &o'er and !round trac(s% and A0:AC thou for !oin! et'een 3* and com&onent &ads. =ome desi!ners thou!h li(e the 6loo(7 of smaller si!nal trac(s li(e A0 or AC thou% 'hile others li(e all of their trac(s to e i! and 6chun($7. ;ood desi!n &ractice is to (ee& trac(s as i! as &ossi le% and then to chan!e to a thinner trac( onl$ 'hen re2uired to meet clearance re2uirements. *han!in! $our trac( from lar!e to small and then ac( to lar!e a!ain is (no'n as 6nec(in!7% or 6nec(in! do'n7. This is often re2uired 'hen $ou have to !o et'een or com&onent &ads. This allo's $ou to have nice i! lo' im&edance trac(s% ut still have the fle/i ilit$ to route et'een ti!ht s&ots. 3*
3n &ractice% $our trac( 'idth 'ill e dictated $ the current flo'in! throu!h it% and the ma/imum tem&erature rise of the trac( $ou are 'illin! to tolerate. 4emem er that ever$ trac( 'ill have a certain amount of resistance% so the trac( 'ill dissi&ate heat 5ust li(e a resistor. The 'ider the trac( the lo'er the resistance. The thic(ness of the co&&er on $our )*+ 'ill also &la$ a &art% as 'ill an$ solder coatin! finish. The thic(ness of the co&&er on the )*+ is nominall$ s&ecified in ounces &er s2uare foot% 'ith Aoz co&&er ein! the most common. "ou can order other thic(nesses li(e 0.Coz% 2oz and 4oz. The thic(er co&&er la$ers are useful for hi!h current% hi!h relia ilit$ desi!ns. The calculations to fi!ure out a re2uired trac( 'idth ased on the current and the ma/imum tem&erature rise are a little com&le/. The$ can also e 2uite inaccurate% as the standard is ased on a set of non:linear !ra&hs ased on measured data from around half a centur$ a!o. These are still re&roduced in the 3)* standard. A hand$ trac( 'idth calculator &ro!ram can e found at '''.ultracad.comDcalc.htm% and !ives results ased on the 3)* !ra&hs. As a rule of thum % a A0de!* tem&erature rise in $our trac( is a nice safe limit to desi!n around. A hand$ reference ta le has een included in this article to !ive $ou a list of trac( 'idths vs current for a A0de!* rise. The D* resistance in milli ohms &er inch is also sho'n. Of course% the i!!er the trac( the etter% so don9t 5ust lindl$ stic( to the ta le.
rac! "idth Re#erence a$le (#or 10de% & tem' rise). rac! "idth is in hous (mils) &urrent (Am's) "idth #or 1oz "idth #or 2 oz milli (hms)*nch A A0 C C2 2 M0 AC AB.2 Page , of 2+ ,
M 4 C L B K 9 A0
C0 K0 AA0 AC0 AK0 220 2L0 M00
PC Design !utorial by David L. Jones 2C 40 CC BC 90 AA0 AM0 AC0
A0.M L.4 4.B M.4 2.9 2.M 2.0 A.B
Pads
)ad sizes% sha&es and dimensions 'ill de&end not onl$ u&on the com&onent $ou are usin!% ut also the manufacturin! &rocess used to assem le the oard% amon! other thin!s. There are a 'hole sle' of standards and theories ehind &ad sizes and la$outs% and this 'ill e e/&lained later. =uffice it to sa$ at this sta!e that $our )*+ &ac(a!e should come 'ith a set of asic com&onent li raries that 'ill !et $ou started. .or all ut the sim&lest oards thou!h% $ou9ll have to modif$ these asic com&onents to suit $our &ur&ose. Over time $ou 'ill uild u& $our o'n li rar$ of com&onents suita le for various re2uirements. There is an im&ortant &arameter (no'n as the &adDhole ratio. This is the ratio of the &ad size to the hole size. Each manufacturer 'ill have their o'n minimum s&ecification for this. As a sim&le rule of thum % the &ad should e at least A.K times the diameter of the hole% or at least 0.Cmm lar!er. This is to allo' for ali!nment tolerances on the drill and the art'or( on to& and ottom la$ers. This ratio !ets more im&ortant the smaller the &ad and hole ecome% and is &articularl$ relevant to vias. There are some common &ractices used 'hen it comes to !eneric com&onent &ads. )ads for leaded com&onents li(e resistors% ca&acitors and diodes should e round% 'ith around B0 thou diameter ein! common. Dual 3n Line ,D3L- com&onents li(e 3*9s are etter suited 'ith oval sha&ed &ads ,L0 thou hi!h $ 90:A00 thou 'ide is common-. )in A of the chi& sould al'a$s e a different &ad sha&e% usuall$ rectan!ular% and 'ith the same dimensions as the other &ins. 1ost surface mount com&onents use rectan!ular &ads% althou!h surface mount =O &ac(a!e 3*s should use oval &ads. A!ain% 'ith &in A ein! rectan!ular. Other com&onents that rel$ on &in num erin!% li(e connectors and =3) resistor &ac(s% should also follo' the 6rectan!ular &in A7 rule. Octa!onal &ads are seldom used% and should !enerall$ e avoided. As a !eneral rule% use circular or oval &ads unless $ou need to use rectan!ular.
ias
Hias connect the trac(s from one side of $our oard to another% $ 'a$ of a hole in $our oard. On all ut chea& home made and lo' end commercial &rotot$&es% vias are made 'ith electricall$ &lated holes% called )lated Throu!h ?oles ,)T?-. )lated throu!h holes allo' electrical connection et'een different la$ers on $our oard. <hat is the difference et'een a via and a &adF )racticall$ s&ea(in! there is no real difference% the$ are oth 5ust electricall$ &lated holes. +ut there are differences 'hen it comes to )*+ desi!n &ac(a!es. )ads and Hias are% and should e% treated differentl$. "ou can !lo all$ edit them se&aratel$% and do some more advanced thin!s to e discussed later. =o don9t use a &ad in &lace of a via% and vice:versa. ?oles in vias are usuall$ a fair it smaller than com&onent &ads% 'ith 0.C:0.Bmm ein! t$&ical. @sin! a via to connect t'o la$ers is commonl$ called 6stitchin!7% as $ou are effectivel$ electricall$ stitchin! oth la$ers to!ether% li(e threadin! a needle ac( and forth throu!h material. Thro' the term stitchin! a fe' times into a conversation and $ou9ll reall$ sound li(e a )*+ &rofessional8
Polygons
6)ol$!ons7 are availa le on man$ )*+ &ac(a!es. A &ol$!on automaticall$ fills in ,or 6floods7- a desired area 'ith co&&er% 'hich 6flo's7 around other &ads and trac(s. The$ are ver$ useful for la$in! do'n !round &lanes. 1a(e sure $ou &lace &ol$!ons after $ou have &laced all of $our tac(s and &ads. )ol$!on can either e 6solid7 fills of co&&er% or 6hatched7 co&&er trac(s in a crisscross fashion. =olid fills are &referred% hatched fills are asicall$ a thin! of the &ast.
Page - of 2+ -
An e/am&le of a 6=olid )ol$!on .ill7 ,Left-% and a 6?atched )ol$!on .ill7 ,4i!ht-
Clearances
Electrical clearances are an im&ortant re2uirement for all oards. Too ti!ht a clearance et'een trac(s and &ads ma$ lead to 6hairline7 shorts and other etchin! &ro lems durin! the manufacturin! &rocess. These can e ver$ hard to fault find once $our oard is assem led. Once a!ain% don9t 6&ush the limits7 of $our manufacturer unless $ou have to% sta$ a ove their recommended minimum s&acin! if at all &ossi le. At least AC thou is a !ood clearance limit for asic throu!h hole desi!ns% 'ith A0 thou or K thou ein! used for more dense surface mount la$outs. 3f $ou !o elo' this% it9s a !ood idea to consult 'ith $our )*+ manufacturer first. .or 240H mains on )*+9s there are various le!al re2uirements% and $ou9ll need to consult the relevant standards if $ou are doin! this sort of 'or(. As a rule of thum % an a solute minimum of Kmm ,MAC thous&acin! should e allo'ed et'een 240H trac(s and isolated si!nal trac(s. ;ood desi!n &ractice 'ould dictate that $ou 'ould have much lar!er clearances than this an$'a$. .or non:mains volta!es% the 3)* standard has a set of ta les that define the clearance re2uired for various volta!es. A sim&lified ta le is sho'n here. The clearance 'ill var$ de&endin! on 'hether the trac(s are on an internal la$ers or the e/ternal surface. The$ also var$ 'ith the o&erational hei!ht of the oard a ove sea level% due to the thinnin! of the atmos&here at hi!h altitudes. *onformal coatin! also im&roves these fi!ures for a !iven clearance% and this is often used on militar$ s&ec )*+s.
Page / of 2+ /
&learances #or +lectrical &onductors

,olta%e (-& or .ea! A&) 0:ACH AL:M0H MA:C0H CA:A00H A0A:AC0H ACA:AB0H ABA:2C0H 2CA:M00H M0A:C00H *nternal 0.0Cmm 0.0Cmm 0.Amm 0.Amm 0.2mm 0.2mm 0.2mm 0.2mm 0.2Cmm +/ternal (01050m) 0.Amm 0.Amm 0.Lmm 0.Lmm 0.Lmm A.2Cmm A.2Cmm A.2Cmm 2.Cmm +/ternal (21050m) 0.Amm 0.Amm 0.Lmm A.Cmm M.2mm M.2mm L.4mm A2.Cmm A2.Cmm
Component Placement ! Design

An old sa$in! is that )*+ desi!n is 90J &lacement and A0J routin!. <hilst the actual fi!ures are of no im&ortance% the conce&t that com&onent &lacement is $ far the most im&ortant as&ect of la$in! out a oard certainl$ holds true. ;ood com&onent &lacement 'ill ma(e $our la$out 5o easier and !ive the est electrical &erformance. +ad com&onent &lacement can turn $our routin! 5o into a ni!htmare and !ive &oor electrical &erformance. 3t ma$ even ma(e $our oard unmanufactura le. =o there is a lot to thin( a out 'hen &lacin! com&onents8 Ever$ desi!ner 'ill have their o'n method of &lacin! com&onents% and if $ou !ave the same circuit ,no matter ho' sim&le- to A00 different e/&erienced desi!ners $ou9d !et a A00 different )*+ la$outs ever$ time. =o there is no a solute ri!ht 'a$ to &lace $our com&onents. +ut there are 2uite a fe' asic rules 'hich 'ill hel& ease $our routin!% !ive $ou the est electrical &erformance% and sim&lif$ lar!e and com&le/ desi!ns. At this &oint it is a !ood idea to !ive $ou an idea of the asic ste&s re2uired to !o a out la$in! out a com&lete oard:
=et $our sna& !rid% visi le !rid% and default trac(D&ad sizes. Thro' do'n all the com&onents onto the oard. Divide and &lace $our com&onents into functional 6 uildin! loc(s7 'here &ossi le. 3dentif$ la$out critical trac(s on $our circuit and route them first. )lace and route each uildin! loc( se&aratel$% off the oard. 1ove com&leted uildin! loc(s into &osition on $our main oard. 4oute the remainin! si!nal and &o'er connections et'een loc(s. Do a !eneral 6tid$ u&7 of the oard. Do a Desi!n 4ule *hec(. ;et someone to chec( it
This is $ no means a e:all and end:all chec( list% it9s hi!hl$ varia le de&endin! on man$ factors. +ut it is a !ood !eneral !uide to &roducin! a &rofessional first:class la$out. Lets loo( in more detail at the &rocedure descri ed a ove. <e have alread$ loo(ed at the !rids and trac(D&ad sizes% these should e the first thin!s that $ou set u& efore $ou start doin! an$thin!. Eo e/ce&tions8 1an$ &eo&le li(e to 5um& strai!ht into &lacin! all the com&onents into 'hat the$ thin( is the most o&timum &osition on the oard% all in one hit. <hilst this can 'or( for small circuits% $ou don9t have much of a ho&e 'hen $ou have more com&le/ circuits 'ith hundreds of com&onents s&read across man$ functional circuit loc(s. <h$F% ecause it9s ver$ eas$ to run out of 6routin! s&ace7% 'hich is the room to la$ do'n all $our trac(s. 3f $ou fi/ all $our com&onent &ositions and then tr$ to route ever$thin!% $ou can easil$ &aint $ourself into a corner so to s&ea(. Alternativel$% if $ou s&ace the com&onents out too much% $ou can end u& 'ith a lar!e oard that does not ma(e efficient use of s&ace. The hallmar( of an ine/&erienced desi!ner is a oard that has ever$ com&onent evenl$ s&aced out% and then has thousands of trac(s and vias crisscrossin! the oard. 3t mi!ht 'or(% ut it can e u!l$ and inefficient% not to mention i!!er and more e/&ensive to manufacture.
Page 10 of 2+ 10
PC Design !utorial by David L. Jones The est 'a$ to start $our la$out is to !et ALL of $our com&onents onto the screen first.
3f $ou have a com&anion schematic &ac(a!e% then the sim&lest 'a$ to do this is to !et $our )*+ &ro!ram to im&ort $our schematic desi!n and select all the com&onents automaticall$. This 'ill also e discussed later. 3f all $ou have is a )*+ &ro!ram% then $ou9ll have to select each com&onent from the li rar$ and &lace them do'n manuall$. <ith all the com&onents on screen% $ou should !et a !ood indication of 'hether or not $our &arts 'ill easil$ fit onto the size ,and sha&e- of oard that $ou re2uire. 3f it loo(s li(e it9s !oin! to e a ti!ht fit then $ou (no' that $ou 'ill have to 'or( hard to tr$ and (ee& the com&onent s&acin! 6ti!ht7% and the trac(in! as efficient as &ossi le. 3f it loo(s li(e $ou have &lent$ of room then $ou can e a it more li eral in $our la$out. Of course% if it loo(s li(e $ou have uc(le$s chance of !ettin! $our com&onents on the oard% $ou9ll have to !o ac( to the dra'in! oard. Eo' anal$se $our schematic and determine 'hich &arts of the desi!n can e ro(en u& into 6 uildin! loc(s7. Often this is fairl$ o vious. =a$ for e/am&le $ou have a com&le/ loo(in! active filter in $our circuit. This 'ould t$&icall$ have a sin!le in&ut line and a sin!le out&ut line% ut it 'ill have lots of com&onents and connections as &art of the filter. This is a classic 6 uildin! loc(7 circuit% and one that lends itself 'ell to com inin! all of these &arts to!ether in the same location. =o $ou 'ould !ra all of these &arts and start to rearran!e them into their o'n little la$out off to one side of $our oard. Don9t 'orr$ too much a out 'here the actual loc( !oes on $our oard $et. "ou 'ill also need to &artition off electricall$ sensitive &arts of $our desi!n into i!!er loc(s. One ma5or e/am&le is 'ith mi/ed di!ital and analo! circuits. Di!ital and analo! 5ust do not mi/% and 'ill need to e &h$sicall$ and electricall$ se&arated. Another e/am&le is 'ith hi!h fre2uenc$ and hi!h current circuits% the$ do not mi/ 'ith lo' fre2uenc$ and lo' current sensitive circuits. 1ore a out this later. As a !eneral rule% $our com&onents should e neatl$ lined u&. ?avin! 3*s in the same direction% resistors in neat columns% &olarised ca&acitors all around the same 'a$% and connectors on the ed!e of the oard. Don9t do this at the e/&ense of havin! an electricall$ &oor la$out% or an overl$ i! oard thou!h. Electrical &arameters should al'a$s ta(e &recedence over nicel$ lined u& com&onents. =$mmetr$ is really nice in )*+ desi!n% it9s aestheticall$ &leasin! and 5ust 6loo(s ri!ht7. 3f $ou have somethin! li(e t'o identical uildin! loc( circuits side $ side% and one is laid out sli!htl$ differentl$% it stic(s out li(e a sore thum . 3f $ou have &laced $our com&onents 'isel$% 90J of $our 'or( 'ill e done. The last A0J should 5ust e 5oinin! the dots so to s&ea(. <ell% not 2uite% ut !ood &lacement is a !ood ma5orit$ of $our 'or( done. Once $ou are ha&&$ 'ith the com&onent &lacements% $ou can start to route all the different uildin! loc(s se&aratel$. <hen finished% it is then often a sim&le matter to move and arran!e the uildin! loc(s into the rest of $our desi!n. The Desi!n 4ule *hec( ,D4*- 'ill e covered later% ut it is an essential ste& to ensurin! that $our oard is correct efore manufacture. A D4* asicall$ chec(s for correct connectivit$ of $our trac(s% and for correct 'idths and clearances. ;ettin! someone to chec( $our oard ma$ sound li(e an overl$ ureaucratic &rocess% ut it reall$ is a vital ste&. Eo matter ho' e/&erienced $ou are at )*+ desi!n% there 'ill always e somethin! $ou overloo(ed. A fresh &air of e$es and a different mindset 'ill &ic( u& &ro lems $ou 'ould never see. 3f $ou don9t have an$one to chec( $our oard over and don9t have D4* ca&a ilit$% then $ou9ll have to do it $ourself. ;et a &rintout of $our schematic and a hi!hli!hter &en. Eo'% com&are ever$ sin!le electrical 6net7 connection on $our oard 'ith the schematic% net $ net. ?i!hli!ht each net on the schematic as $ou com&lete it. <hen $ou are finished% there should e no electrical connections left that aren9t hi!hli!hted. "ou can no' e fairl$ confident that $our oard is electricall$ correct.
Page 11 of 2+ 11
Basic "outing
Eo' it9s time for some asic routin! rules. 4outin! is also (no'n as 6trac(in!7. 4outin! is the &rocess of la$in! do'n trac(s to connect com&onents on $our oard. An electrical connection et'een t'o or more &ads is (no'n as a 6net7.
Nee& nets as short as &ossi le. The lon!er $our total trac( len!th% the !reater it9s resistance% ca&acitance and inductance. All of 'hich can e undesira le factors. Trac(s should onl$ have an!les of 4C de!rees. Avoid the use of ri!ht an!les% and under no circumstances use an an!le !reater than 90 de!rees. This is im&ortant to !ive a &rofessional and neat a&&earance to $our oard. )*+ &ac(a!es 'ill have a mode to enforce 4C de!ree movements% ma(e use of it. There should never e a need to turn it off. *ontrar$ to &o&ular elief% shar& ri!ht an!le corners on trac(s don9t &roduce measura le E13 or other &ro lems. The reasons to avoid ri!ht an!les are much sim&ler : it 5ust doesn9t loo( !ood% and it ma$ have some manufacturin! im&lications. .or!et nice rounded trac( corners% the$ are harder and slo'er to &lace and have no real advanta!e. =tic( to 4C de!ree increments. 4ounded trac( ends elon! to the &re:*AD ta&ed art'or( era. 6=na(e7 $our trac(s around the oard% don9t 5ust !o 6&oint to &oint7. )oint to &oint trac(in! ma$ loo( more efficient to a e!inner at first% ut there are a fe' reasons $ou shouldn9t use it. The first is that it9s u!l$% al'a$s an im&ortant factor in )*+ desi!n8 The second is that it is not ver$ s&ace efficient 'hen $ou 'ant to run more trac(s on other la$ers. Ena le $our Electrical !rid% 'hich is sometimes referred to as a 6sna& to center7 or 6sna& to nearest7 o&tion. Let the soft'are find the centers of &ads and ends of trac(s automaticall$ for $ou. This is !reat for 'hen $ou have &ads and trac(s 'hich aren9t lined u& to $our current sna& !rid. 3f $ou don9t have these o&tions ena led then $ou ma$ have to (ee& reducin! $our sna& !rid until $ou find one that fits. .ar more trou le than it9s 'orth. There is almost never a reason to have these o&tions disa led. Al'a$s ta(e $our trac( to the center of the &ad% don9t ma(e $our trac( and &ad 65ust touch7. There are fe' reasons for this. The first is that it9s slo&&$ and un&rofessional. The second is that $our &ro!ram ma$ not thin( that the trac( is ma(in! electrical connection to the &ad. )ro&er use of a sna& !rid and electrical !rid 'ill avoid &ro lems here. @se a sin!le trac(% not multi&le trac(s tac(ed to!ether end to end. 3t ma$ ma(e no difference to the loo( of $our final oard% ut it can e a &ain for future editin!. Often $ou9ll have to e/tend a trac( a it. 3n this case it9s est to delete the old one and &lace a ne' one. 3t ma$ ta(e a fe' e/tra seconds% ut it9s 'orth it. )eo&le loo(in! at $our finished oard ma$ not (no'% ut "O@9LL (no'8 3t9s the little touches li(e this that set !ood )*+ desi!ners a&art. 1a(e sure $our trac(s !o ri!ht throu!h the e/act center of &ads and com&onents% and not off to one side. @se of the correct sna& !rid 'ill ensure that $ou !et this ri!ht ever$ time. 3f $our trac( doesn9t !o throu!h the e/act center then $ou are usin! the 'ron! sna& !rid. <h$ do $ou need to do thisF 3t ma(es $our oard neater and more s$mmetrical% and it !ives $ou the most clearance. Onl$ ta(e one trac( et'een A00 thou &ads unless a solutel$ necessar$. Onl$ on lar!e and ver$ dense desi!ns should $ou consider t'o trac(s et'een &ads. Three trac(s et'een &ads is not unheard of% ut 'e are tal(in! seriousl$ fine tolerances here. .or hi!h currents% use multi&le vias 'hen !oin! et'een la$ers. This 'ill reduce $our trac( im&edance and im&rove the relia ilit$. This is a !eneral rule 'henever $ou need to decrease the im&edance of $our trac( or &o'er &lane. Don9t 6dra!7 trac(s to an!les other than 4C de!rees 6Eec( do'n7 et'een &ads 'here &ossi le. E!% a A0 thou trac( throu!h t'o L0 thou &ads !ives a !enerous AC thou clearance et'een trac( and &ad. 3f $our &o'er and !round trac(s are deemed to e critical% then la$ them do'n first. Also% ma(e $our &o'er trac(s as +3; as &ossi le. Nee& &o'er and !round trac(s runnin! in close &ro/imit$ to each other if &ossi le% don9t send them in o&&osite directions around the oard. This lo'ers the loo& inductance of $our &o'er s$stem% and allo's for effective $&assin!. Nee& thin!s s$mmetrical. =$mmetr$ in trac(in! and com&onent &lacement is reall$ nice from a &rofessional aesthetics &oint of vie'. Don9t leave an$ unconnected co&&er fills ,also called 6dead co&&er7-% !round them or ta(e them out. Page 12 of 2+ 12

3f $ou are la$in! out a non:&lated throu!h dou le sided oard% then there are some additional thin!s to 'atch out for. Eon:&late throu!h holes re2uire $ou to solder a lin( throu!h the oard on oth the to& and ottom la$er. Do not &lace vias under com&onents. Once the com&onent is soldered in &lace $ou 'on9t e a le to access the 5oint to solder a feed throu!h. The solder 5oint for the feed throu!h can also interfere 'ith the com&nent. Tr$ and use throu!h hole com&onent le!s to connect to& trac(s to ottom trac(s. This minimises the num er of vias. 4emem er that each via adds t'o solder 5oints to $our oard. The more solder 5oints $ou have% the less relia le $our oard ecomes. Eot to mention that that it ta(es a lot lon!er to assem le.
An example of GOOD power routing (Left) and BAD power routing (Right)
An example of GOOD routing (Left) and BAD routing (Right)
Page 19 of 2+ 19
#inishing Touches
Once $ou have finished all $our routin!% $our oard isn9t done 2uite $et. There are a fe' last minute chec(s and finishin! touches $ou should do.
3f $ou have thin trac(s ,O2C thou- then it9s nice to add a 6chamfer7 to an$ 5unctions% thus eliminatin! an$ 90 de!ree an!les. This ma(es the trac( more &h$sicall$ ro ust% and &revents an$ &otential manufacturin! etchin! &ro lems. +ut most im&ortantl$% it loo(s nice.
6T7
*hec( that $ou have an$ re2uired mountin! holes on the oard. Nee& mountin! holes 'ell clear of an$ com&onents or trac(s. Allo' room for an$ 'ashers and scre's. 1inimise the num er of hole sizes. E/tra hole sizes cost $ou mone$% as the manufacturer 'ill char!e $ou ased on not onl$ the num er of holes in $our oards% ut the num er of different hole sizes $ou have. 3t ta(es time for the ver$ hi!h s&eed drill to s&in do'n% chan!e drill its% and then s&in u& a!ain. *hec( 'ith $our manufacturer for these costs% ut $ou can9t !o 'ron! $ minimisin! the num er of hole sizes. Dou le chec( for correct hole sizes on all $our com&onents. Eothin! is more anno$in! than !ettin! $our &erfectl$ laid out oard ac( from the manufacturer% onl$ to find that a com&onent 'on9t fit in the holes8 This is a ver$ common &ro lem% don9t !et cau!ht out. Ensure that all $our vias are identical% 'ith the same &ad and hole sizes. 4emem er $our &ad to hole ratio. Errors here can cause 6 rea(outs7 in $our via &ad% 'here the hole% if shifted sli!htl$ can e outside of $our &ad. <ith &lated throu!h holes this is not al'a$s fatal% ut 'ithout a com&lete annular rin! around $our hole% $our via 'ill e mechanicall$ unrelia le. *hec( that there is ade2uate &h$sical distance et'een all $our com&onents. <atch out for com&onents 'ith e/&osed metal that can ma(e electrical contact 'ith other com&onents% or e/&osed trac(s and &ads. *han!e $our dis&la$ to 6draft7 mode% 'hich 'ill dis&la$ all $our trac(s and &ads as outlines. This 'ill allo' $ou to see $our oard 6'arts and all7% and 'ill sho' u& an$ trac(s that are tac(ed on or not endin! on &ad centers. 3f $ou 'ish% add 6teardro&s7 to all $our &ads and vias. A teardro& is a nice 6smoothin! out7 the 5unction et'een the trac( and the &ad% not sur&risin!l$% sha&ed li(e a teardro&. This !ives a more ro ust and relia le trac( to &ad interface% etter than the almost ri!ht an!le et'een a standard trac( and &ad. Don9t add teardro&s manuall$ thou!h% it9s a 'aste of time. +ut if $our &ro!ram su&&orts automatic teardro& &lacement% feel free to use it.
of
Single Sided Design

=in!le sided desi!n can !reatl$ reduce the cost of $our oard. 3f $ou can fit $our desi!n on a sin!le sided oard then it is &refera le to do so. Loo( inside man$ of toda$9s consumer items li(e TH9s and DHD &la$ers% and $ou 'ill almost certainl$ find some sin!le sided oards. The$ are still used ecause the$ are so chea& to manufacture. =in!le sided desi!n ho'ever re2uires some uni2ue techni2ues 'hich are aren9t re2uired once $ou !o to dou led sided and multi:la$er desi!n. 3t is certainl$ more challen!in! than a dou le sided la$out. 3n fact% a sin!le sided oard desi!n 'ill e re!arded inversel$ &ro&ortional to the num er of 5um&er lin(s used. Eo 5um&er lin(s earns the admiration of man$ &eers8 3t is all a out a alance et'een oard size and the num er of 5um&er lin(s re2uired. Almost ever$ sin!le sided oard 'ill re2uire some 5um&er lin(s% so it is im&ortant to minimise these. *om&onent &lacement is even more critical on a sin!le sided oard% so this is no time to ma(e all $our com&onents nice and neatl$ ali!ned. Arran!e $our com&onents so that the$ !ive the shortest and most efficient trac(in! &ossi le. 3t is li(e &la$in! a !ame *hess% if $ou don9t thin( man$ moves ahead then $ou 'ill !et $ourself in a corner &rett$ 2uic(l$. ?avin! 5ust one trac( runnin! from one side of $our oard to the other can ruin $our 'hole la$out% as it ma(es routin! an$ other &er&endicular trac(s im&ossi le. 1an$ &eo&le 'ill route their oard as thou!h it is a dou le sided oard% ut onl$ 'ith strai!ht trac(s on the to& la$er. Then 'hen the oard is to e manufactured% the to& la$er trac(s are re&laced 'ith 5um&er lin(s. This can e a rather inefficient 'a$ to a&&roach sin!le sided desi!n% and is not recommended. "ou must e fru!al in $our &lacement% and don9t e afraid to ri& ever$thin! u& and tr$ a!ain if $ou see a etter 'a$ to route somethin!. <ith e/&erience% $ou 'ill e a le to tell efore $ou even start% if a desi!n if 'orth tr$in! to route on a sin!le sided oard.
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Dou$le Sided Design

Dou le sided desi!n !ives an e/tra de!ree of freedom for desi!nin! $our oard. Thin!s that 'ere ne/t to im&ossi le on a sin!le sided oard ecome relativel$ eas$ 'hen $ou add an additional la$er. 1an$ ,ine/&erienced- desi!ners tend to ecome laz$ 'hen la$in! out dou le sided oards. The$ thin( that com&onent &lacement doesn9t matter all that much% and hundreds of vias can e used to !et them out of trou le. The$ 'ill often la$ out com&onents li(e 3*s in neat ro's% and then &roceed to route ever$thin! usin! a ri!ht an!le rules. This means that the$ 'ill route all the trac(s on the ottom la$er in one direction% and then all the trac(s on the to& la$er &er&endicular to the ottom la$er. The theor$ is that if $ou cho& and chan!e et'een la$ers enou!h times $ou can route almost an$thin! usin! a 6ste&7 t$&e &attern. This techni2ue can e u!l$ and inefficient% and is a thro' ac( to the old manual ta&e da$s. 1an$ asic auto routers 'or( in this 'a$. =tic( to usin! !ood com&onent &lacement techni2ues and efficient uildin! loc( routin!. Dou le sided desi!n can also !ive $ou the chance to ma(e use of !ood !round &lane techni2ues% re2uired for hi!h fre2uenc$ desi!ns. This 'ill e discussed later.
Other %ayers
There are a fe' other im&ortant la$ers on $our )*+ eside the co&&er trac( la$ers.
Silkscreen
The 6sil(screen7 la$er is also (no'n as the 6com&onent overla$7 or 6com&onent la$er7. 3t is the la$er on the to& of $our oard ,and ottom if needed- that contains $our com&onent outlines% desi!nators ,*A% 4A etc-% and free te/t. This is added to $our oard usin! a sil(screenin! &rocess. <hite is a standard colour% ut other colours are availa le u&on re2uest. "ou can even mi/ and match colours on the one oard% ut that usuall$ costs e/tra. <hen desi!nin! $our oard% ma(e sure that $ou (ee& all $our com&onent desi!nators the same te/t size% and oriented in the same direction. <hen la$in! out $our o'n com&onent foot&rints% 'ere &ossi le% ma(e sure that $ou add a com&onent overla$ that reflects the actual size of $our com&onent. This 'a$ $ou 'ill e a le to tell at a !lance ho' close $ou can &h$sicall$ &osition $our com&onents. Ensure that all &olarised com&onents are mar(ed% and that &in A is identified. "our sil(screen la$er 'ill e the most inaccuratel$ ali!ned of all $our la$ers% so don9t rel$ on it for an$ &ositional accurac$. Ensure that no &art of the sil(screen overla&s a are &ad. There is no minimum 'idth re2uirement for lines on the com&onent overla$% so feel free to use smaller lines and te/t sizes to fit thin!s in. 3f &arts of the te/t or lines don9t turn out &erfectl$ on $our oard then it does not affect $our desi!n% unli(e trac(s and &ads. As a !eneral rule% don9t &ut com&onent values on the sil(screen% 5ust the com&onent desi!nator.
Solder Mask
A solder mas( is a thin &ol$mer coatin! on $our oard 'hich surrounds $our &ads to hel& &revent solder from rid!in! et'een &ins. This is essential for surface mount and fine &itch devices. The solder mas( t$&icall$ covers ever$thin! e/ce&t &ads and vias. "our )*+ &ro!ram 'ill automaticall$ remove solder mas( from &ads and vias. The !a& it leaves et'een the &ad and the solder mas( is (no'n as the 6mas( e/&ansion7. The mas( e/&ansion should usuall$ e set to at least a fe' thou. +e careful not to ma(e it too i!% or there mi!ht e no solder mas( et'een ver$ fine &itch devices. "our solder mas( is dis&la$ed in $our )*+ &ac(a!e as a ne!ative ima!e% 5ust li(e $our &o'er &lane. @nder normal circumstances $ou don9t need to &ut an$thin! on $our solder mas( la$er. +ut if $ou 'ant to leave the solder mas( off a certain &art of $our oard% $ou can &lace trac(s and fills on $our solder mas( la$er. 3t is often hand$ to remove a small s2uare of solder mas( from the to& of $our oard% 'here there are no trac(s underneath. This leaves a nice are and visi le &art of $our oard to 'rite somethin! 'ith a &en. =older mas(s come in t'o t$&es% sil(screen% or 6&hoto ima!ea le7. )hoto ima!ea le mas(s &rovide etter resolution and ali!nment% and are &referred over sil(screened. "ou can !et different colour solder mas(s% ut the standard colour is !reen. On most standard 2ualit$ oards% the solder mas( is laid directl$ over the are co&&er trac(s. This is (no'n as =older 1as( Over +are *o&&er% or =1O+*. "ou can !et other coatin!s over $our trac(s in addition to the
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PC Design !utorial by David L. Jones solder mas(% ut these are usuall$ for fairl$ e/otic a&&lications.
"ou can have vias covered 'ith solder mas( if $ou 'ish% this is (no'n a tentin!. This is useful for close tolerance desi!ns% to &revent solder from flo'in! into vias.
Mechanical %ayer
The mechanical la$er ,'hich ma$ !o under other names de&endin! on the &ac(a!e- is used to &rovide an outline for $our oard% and other manufacturin! instructions. 3t is not &art of $our actual )*+ desi!n% ut is ver$ useful to tell the )*+ manufacturer ho' $ou 'ant $our oard assem led. There are no hard and fast rules for this la$er% use it ho'ever $ou li(e% 5ust ma(e sure $ou tell $our )*+ manufacturer.
&eepout
The (ee&out la$er !enerall$ defines areas on $our oard that $ou don9t 'ant auto or manuall$ routed. This can include clearance areas around mountin! hole &ads or hi!h volta!e com&onents for instance.
%ayer 'lignment
<hen the )*+ manufacturer ma(es $our oard% there 'ill e ali!nment tolerances on the art'or( film for each la$er. This includes trac(% &lane% sil(screen% solder mas(% and drillin!. 3f $ou don9t allo' for this in $our desi!n% and ma(e $our tolerances too fine% $ou can end u& in i! trou le. *onsult the manufacturer for 'hat ali!nment tolerances the$ can achieve% and also 'hat ali!nment tolerance $ou are &a$in! for8
(etlists
A netlist is essentiall$ a list of connections ,6nets7- 'hich corres&ond to $our schematic. 3t also contains the list of com&onents% com&onent desi!nators% com&onent foot&rints and other information related to $our schematic. The netlist file can e !enerated $ $our schematic &ac(a!e. ;eneratin! a netlist is also called 6schematic ca&ture7. "our )*+ &ac(a!e can then im&ort this netlist file and do man$ thin!s. 3t can automaticall$ load all the re2uired com&onents onto $our lan( oard. 3t can also assi!n a 6net7 name to each of $our com&onent &ins. <ith nets assi!ned to $our )*+ com&onents% it is no' &ossi le to Auto 4oute% do Desi!n 4ule *hec(in!% and dis&la$ com&onent connectivit$. This is the fundamental conce&t ehind modern =chematic and )*+ *AD &ac(a!es.
"ats (est
A Typical Rat !e t" Di play# "our 5o of com&onent &lacement 'ill e made infinitel$ easier $ havin! a 6rats nest7 dis&la$ ena led. 3f there is one reason for !oin! to the trou le of dra'in! u& an accurate schematic and im&ortin! a netlist% this is surel$ it. .or lar!e desi!ns% a rats nest dis&la$ is essential.
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PC Design !utorial by David L. Jones A rats nest dis&la$ is one 'here the &ro!ram 'ill dra' a strai!ht line ,not a trac(- et'een the &ads of com&onents 'hich are connected on the schematic. 3n effect% it sho's the connectivit$ of $our circuit efore $ou start la$in! out trac(s. At the start of $our oard la$out% 'ith all $our com&onents &laced do'n randoml$% this 'ill a&&ear as a hu!e and com&licated random maze of lines. ?ence the name rats nest.
The rats nest ma$ loo( ver$ dauntin! at first% ut 'hen $ou move each com&onent the lines 'ill automaticall$ move 'ith them. 3n this 'a$ $ou can see instantl$ 'hich com&onents are connected to 'hich% 'ithout havin! to refer ac( to the schematic and constantl$ cross reference com&onent desi!nators. Once $ou have used this feature once% $ou 'on9t 'ant to live 'ithout it. Even 'hen doin! sim&le desi!ns 'ith a fe' dozen com&onents% $ou 'ill miss this functionalit$. <ith the rats nest dis&la$ ena led% it 'ill e almost &ossi le to la$ out all of $our com&onents o&timall$ in no time% 'ithout havin! to la$ do'n one sin!le trac(. The rats nest dis&la$ 'ill effectivel$ sho' $ou 'hat $our trac(s 'ill connect to. The rats nest lines should disa&&ear 'hen $ou route $our trac(s et'een com&onents% so $our desi!n 'ill !et less and less 6com&licated loo(in!7 as $ou !o alon!. <hen all the rats nest lines disa&&ear% $our oard is full$ routed.
Design "ule Checking

Desi!n 4ule *hec(in! ,D4*- allo's $ou to automaticall$ chec( $our )*+ desi!n for connectivit$% clearance% and other manufacturin! errors. <ith the lar!e and com&le/ )*+s ein! desi!ned toda$% it is im&ractical to manuall$ chec( a )*+ desi!n. This is 'here the D4* comes into its o'n% it is an a solutel$ essential ste& in &rofessional )*+ desi!n. E/am&les of 'hat $ou can chec( 'ith a D4* are:
*ircuit connectivit$. 3t chec(s that ever$ trac( on $our oard matches the connectivit$ of $our schematic. Electrical clearance. "ou can chec( the clearance et'een trac(s% &ads% and com&onents. 1anufacturin! tolerances li(e minDma/ hole sizes% trac( 'idths% via 'idths% annulus sizes% and short circuits.
A com&lete D4* is usuall$ &erformed after $ou have finished $our )*+. =ome &ac(a!es ho'ever have the a ilit$ to do 6real time7 ,or 6online7- D4* chec(in! as $ou create $our oard. .or instance% it 'ont let $ou connect a trac( to a &ad it shouldn9t !o to% or violate a clearance et'een trac( and &ad. 3f $ou have real: time D4* ca&a ilit$% use it% it9s an invalua le tool.
#or)ard and Back 'nnotation

.or'ard Annotation is 'hen $ou ma(e chan!es to $our e/istin! )*+ la$out via the schematic editor. The &ro!ram 'ill ta(e $our schematic netlist and com&onent desi!nators% and im&ort them into $our )*+ desi!n% and ma(in! an$ relevant chan!es. =ome &ac(a!es 'ill also automaticall$ remove old )*+ trac(s that are no lon!er connected. "ou can do this at an$ time durin! $our )*+ la$out. 3f $ou u&date $our schematic% then $ou must for'ard annotate into $our )*+ desi!n. "ou can do edits li(e this manuall$% ut for'ard annotation automates the &rocess. +ac( Annotation is 'hen $ou chan!e one of the com&onent desi!nators ,e!. 6*A7 to 6*27- on $our )*+ and then automaticall$ u&date this information ac( into $our =chematic. 1ore advanced ac( annotation features allo' $ou to s'a& !ates on chi&s% and &erform other electrical chan!es. There should never e much real need to use ac( annotation.
Multi layer Design
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Typical $ Layer %&B &on truction A multi la$er )*+ is much more e/&ensive and difficult to manufacture than a sin!le or dou le sided oard% ut it reall$ does !ive $ou a lot of e/tra densit$ to route &o'er and si!nal trac(s. +$ havin! $our si!nals runnin! on the inside of $our oard% $ou can &ac( $our com&onents more ti!htl$ on $our oard to !ive $ou a more com&act desi!n. Decidin! to !o from dou le sided to multi la$er can e a i! decision% so ma(e sure that a multi la$er oard is 'arranted on the !rounds of oard size and com&le/it$. "ou can for!et a out ma(in! multi la$er oards $ourself% it re2uires a commercial manufacturer. 1ost of the ho $ oard su&&liers 'ill not do multi la$er oards. 1ulti la$er oards come in even num er of la$ers. <ith 4% L% and K la$er ein! the most common. "ou can !o man$ la$ers a ove this% ut no' $ou are in the realm of the ver$ s&ecialised. Technicall$ $ou can !et an odd num er of la$ers manufactured% li(e a M la$er oard for instance. +ut it reall$ 'on9t save $ou an$ cost over a 4 la$er oard. 3n fact a M la$er oard mi!ht even e more e/&ensive than a 4 la$er oard ecause it calls for a non:standard manufacturin! &rocess. 3f $ou decide to !o multi la$er then ma(e sure $ou ma(e use all of $our la$ers% there is no &oint leavin! one com&letel$ lan(. <ith a multi la$er oard% $ou 'ould t$&icall$ dedicate one com&lete la$er to a !round &lane% and another to $our &o'er. <ith &erha&s a fe' si!nal trac(s thro'n on the &o'er la$er if $ou need to. 3f $ou have a di!ital onl$ oard% then $ou9d often dedicate the entire &o'er la$er also. 3f $ou have room on the to& or ottom la$er% $ou can route an$ additional &o'er rail trac(s on there. )o'er la$ers are almost al'a$s in the middle of the oard% 'ith the !round closer to the to& la$er. Once $ou have $our &o'er ta(en care of on the inner la$ers% $ou9ll e sur&rised at the room $ou no' have availa le for $our si!nal trac(s. 3t reall$ does o&en u& a 'hole ne' dimension to routin!. 3f &o'er &lanes are vital% and $ou have a lot of connections to route% then $ou ma$ have to move from 4 to L la$ers. =i/ la$ers 'ill !ive $ou four full si!nal routin! la$ers and t'o la$ers dedicated to &o'er. "ou can reall$ do some advanced routin! 'ith L la$ers. Ei!ht la$ers and a ove is asicall$ more of the same. <ith multi la$er desi!n comes the o&tions of usin! different t$&es of vias to im&rove $our routin! densit$. There are three t$&es of vias : standard% lind% and uried. =tandard vias !o throu!h the 'hole oard% and can connect an$ of the to&% ottom or inner la$ers. These can e 'asteful of s&ace on la$ers 'hich aren9t connected. 6+lind7 vias !o from the outside surface to one of the inner la$ers onl$. The hole does not &rotrude throu!h the other side of the oard. The via is in effect 6 lind7 from the other side of the oard. 6+uried7 vias onl$ connect t'o or more inner la$ers% 'ith no hole ein! visi le on the outside of the oard. =o the hole is com&letel$ uried inside $our oard. +lind and uried vias cost more to manufacture than standard vias. +ut the$ are ver$ useful% and almost mandator$ for ver$ hi!h densit$ desi!ns li(e those involvin! +all ;rid Arra$ ,+;A- com&onents.
Po)er Planes
3t is !ood &ractice to use 6&o'er &lanes7 to distri ute &o'er across $our oard. @sin! &o'er &lanes can drasticall$ reduce the &o'er 'irin! inductance and im&edance to $our com&onents. This can e vital for hi!h s&eed di!ital desi!n for instance. 3t is !ood desi!n &ractice to use &o'er &lanes 'henever &ossi le. The$ can
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PC Design !utorial by David L. Jones even e used on dou le sided oards% if most of $our si!nal trac(s are on the to& la$er.
A &o'er &lane is asicall$ one solid co&&er la$er of oard dedicated to either $our ;round or )o'er rails% or oth. )o'er &lanes !o in the middle la$ers of $our oard% usuall$ on the la$ers closest to the outer surfaces. On a 4 la$er oard 'ith com&le/ &o'er re2uirements it is common to dedicate one la$er to $our !round &lane% and another la$er to $our various &ositive and ne!ative &o'er trac(s. "our !round rail is usuall$ $our si!nal reference line% so a !round &lane is first &reference efore a &o'er &lane is considered. 1an$ )*+ &ac(a!es have s&ecial )o'er )lane la$ers that are desi!ned and laid out in reverse to $our other normal trac(in! la$ers. On a normal trac(in! la$er% $our oard is assumed to e lan(% and $ou then la$ do'n trac(s 'hich 'ill ecome $our actual co&&er trac(s. On a &o'er &lane ho'ever% $our oard is assumed to e covered 'ith co&&er. La$in! do'n trac(s on a &o'er &lane actuall$ removes the co&&er. This conce&t can ta(e some !ettin! used to. A sim&le &o'er &lane 'ill not have an$ 6trac(s7 ,or removed co&&er its- at all on it% ut 'ill 5ust e one solid la$er of co&&er. 3n 'hich case $ou don9t need to la$ do'n an$ trac(s to remove an$ co&&er. ?o'ever% it is common &ractice on more com&le/ oards to 6s&lit7 the &o'er &lane $ la$in! do'n trac(s. This ma$ e done to se&arate an analo! and a di!ital !round% 'hich 'ill reduce the amount of di!ital !round noise 'hich is cou&led into the more sensitive analo! circuitr$. A t$&ical s&lit &o'er &lane 'ould involve a 6trac(7 ein! &laced from near $our in&ut &o'er connector or main filter ca&acitors and the o&&osite ed!e of the oard. +e careful not to accidentall$ cause a &o'er 6loo&7 on $our oard $ inadvertentl$ connectin! the t'o halves of $our &lane on the other side of the oard. As a matter of course% $ou should &lace 6trac(s7 com&letel$ around the outer ed!e of $our oard. This 'ill ensure that the &o'er &lanes do not e/tend ri!ht to the ed!e of the oard. )o'er &lanes on the ed!es of $our oard can short to not onl$ one another% ut also to an$ !uide rails or mountin! hard'are. "ou don9t have to use the actual )o'er )lane la$er on $our )*+ &ac(a!e if $ou don9t 'ant to. "ou can use a re!ular si!nal la$er and la$ do'n co&&er fills and trac(s $ourself. )o'er )lanes la$ers thou!h often have some advanta!es that 'ill var$ from one )*+ &ac(a!e another.
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Good Grounding
;roundin! is fundamental to the o&eration of man$ circuits. ;ood or ad !roundin! techni2ues can ma(e or rea( $our desi!n. There are several !roundin! techni2ues 'hich are al'a$s !ood &ractices to incor&orate into an$ desi!n.
@se co&&er% and lots of it. The more co&&er $ou have in $our !round &ath% the lo'er the im&edance. This is hi!hl$ desira le for man$ electrical reasons. @se &ol$!on fills and &lanes 'here &ossi le. Al'a$s dedicate one of $our &lanes to !round on multi:la$er oards. 1a(e it the la$er closest to the to& la$er. 4un se&arate !round &aths for critical &arts of $our circuit% ac( to the main filter ca&acitor,s-. This is (no'n as 6star7 !roundin!% ecause the !round trac(s all run out from a central &oint% often loo(in! li(e a star. 3n fact% tr$ and do this as matter of course% even if $our com&onents aren9t critical. =e&arate !round lines (ee& current and noise from one com&onent from affectin! other com&onents. 3f usin! a !round &lane% utilise 6s&lit7 &lane techni2ues to !ive effective star !roundin!. 6stitch7 re2uired &oints strai!ht throu!h to $our !round &lane% don9t use an$ more trac( len!th than $ou need. @se multi&le vias to decrease $our trace im&edance to !round.
Good Bypassing
Active com&onents and &oints in $our circuit 'hich dra' si!nificant s'itchin! current should al'a$s e 6 $&assed7. This is to 6smooth7 out $our &o'er rail !oin! to a &articular device. 6+$&assin!7 is usin! a ca&acitor across $our &o'er rails as &h$sicall$ and electricall$ close to the desired com&onent or &oint in $our circuit as &ossi le. A t$&ical $&ass ca&acitor value is A00n.% althou!h other values such as Au.% A0n. and An. are often used to $&ass different fre2uencies. "ou can even have t'o or three different value ca&acitors in &arallel. <hen $&assin!% $ou *AEEOT re&lace multi&le ca&acitors 'ith one sin!le ca&acitor% it defeats the entire &ur&ose of $&assin!8 3t is not uncommon for a lar!e desi!n to have hundreds of $&ass ca&acitors. As a !eneral rule% $ou should use at least one $&ass ca&acitor &er 3* or other s'itchin! com&onent if &ossi le. *ommon values of $&ass ca&acitors are A00n. for !eneral &ur&ose use% A0n. or An. for hi!her fre2uencies% and Au. or A0u. for lo' fre2uencies. =&ecial lo' E2uivalent =eries 4esistance ,E=4- ca&acitors are sometimes used on critical desi!ns such as s'itch mode &o'er su&&lies.
*igh #re+uency Design Techni+ues

?i!h fre2uenc$ desi!n is 'here $ou reall$ need to consider the effects of &arasitic inductance% ca&acitance and im&edance of $our )*+ la$out. 3f $our si!nal is too fast% and $our trac( is too lon!% then the trac( can ta(e on the &ro&erties of a transmission line. 3f $ou don9t use &ro&er transmission line techni2ues in these situations then $ou can start to !et reflections and other si!nal inte!rit$ &ro lems. A 6critical len!th7 trac( is one in 'hich the &ro&a!ation time of the si!nal starts to !et close to the len!th of the trac(. On standard .44 co&&er oards% a si!nal 'ill travel rou!hl$ L inches ever$ nano second. A rule of thum states that $ou need to !et reall$ concerned 'hen $our trac( len!th a&&roaches half of this fi!ure. +ut in realit$ it can actuall$ e much less than this. 4emem er that di!ital s2uare 'ave si!nals have a harmonic content% so a A001?z s2uare 'ave can actuall$ have si!nal com&onents e/tendin! into the ;?z re!ion. 3n hi!h s&eed desi!n% the !round &lane is fundamental to &reservin! the inte!rit$ of $our si!nals% and also reducin! E13 emissions. 3t allo's $ou to create 6controlled im&edance7 traces% 'hich match $our electrical source and load. 3t also allo's $ou to (ee& si!nals cou&led 6ti!ht7 to their return &ath ,!round-. There are man$ 'a$s to create controlled im&edance 6transmission7 lines on a )*+. +ut the t'o most asic and &o&ular 'a$s are called 1icrostri& and =tri&line. A 1icrostri& is sim&l$ a trace on the to& la$er% 'ith a !round &lane elo'. The calculation involved to find the characteristic im&edance of a 1icrostri& is relativel$ com&le/. 3t is ased on the 'idth and thic(ness of the trace% the hei!ht a ove the !round &lane% and the relative &ermittivit$ of the )*+ material. This is 'h$ it is im&ortant to (ee& the !round &lane as close as &ossi le to ,usuall$- the to& la$er. A =tri&line is similar to the 1icrostri&% ut it has an additional !round &lane on to& of the trace. =o in this case% the trace 'ould have to e on one of the inner la$ers. The advanta!e of stri&line over microstri& is that most of the E13 radiation 'ill e contained 'ithin the !round &lanes.
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PC Design !utorial by David L. Jones There are man$ free &ro!rams and s&readsheets availa le that 'ill calculate all the variations of 1icrostri& and =tri&line for $ou.
=ome useful information and rules of thum for hi!h fre2uenc$ desi!n are:
Nee& $our hi!h fre2uenc$ si!nal trac(s as short as &ossi le. Avoid runnin! critical hi!h fre2uenc$ si!nal trac(s over an$ cutout in $our !round &lane. This causes discontinuit$ in the si!nal return &ath% and can lead to E13 &ro lems. Avoid cutouts in $our !round &lane 'herever &ossi le. A cutout is different to a s&lit &lane% 'hich is fine% &rovided $ou (ee& $our hi!h fre2uenc$ si!nal trac(s over the relevant continuous &lane. ?ave one decou&lin! ca&acitor &er &o'er &in. 3f &ossi le% trac( the 3* &o'er &in to the $&ass ca&acitor first% and then to the &o'er &lane. This 'ill reduce s'itchin! noise on $our &o'er &lane. .or ver$ hi!h fre2uenc$ desi!ns% ta(in! $our &o'er &in directl$ to the &o'er &lane &rovides lo'er inductance% 'hich ma$ e more eneficial than lo'er noise on $our &lane. +e a'are that vias 'ill cause discontinuities in the characteristic im&edance of a transmission line. To minimise crosstal( et'een t'o traces a ove a !round &lane% minimise the distance et'een the &lane and trace% and ma/imise the distance et'een traces. The coefficient of cou&lin! et'een t'o traces is !iven $ AD,AP,Distance et'een traces D hei!ht from &lane-Q2- =maller diameter vias have lo'er &arasitic inductance% and are thus &referred the hi!her in fre2uenc$ $ou !o. Do not connect $our main &o'er in&ut connector directl$ to $our &o'er &lanes% ta(e it via $our main filter ca&acitor,s-.
Dou$le Sided %oading

Loadin! com&onents on oth sides of a )*+ can have man$ enefits. 3ndeed% it is ecomin! an increasin!l$ &o&ular and necessar$ o&tion 'hen la$in! out a oard. There are t'o main drivin! factors ehind a decision to !o 'ith dou le sided loadin!. The first is that of oard size. 3f $ou re2uire a &articular oard size% and all $our com&onents 'on9t fit on one side% then dou le sided load is an o vious 'a$ to !o. The second reason is that it is re2uired to meet certain electrical re2uirements. Often these da$s% 'ith dense hi!h s&eed surface mount devices &ac(ed onto a oard% there is either no room for the man$ $&ass ca&acitors re2uired% or the$ cannot e &laced close enou!h to the device to e effective. +all ;rid Arra$ ,+;A- devices are one such com&onent that enefit from havin! the $&ass ca&acitors on the ottom of the oard. 3ndeed% it is common to find dou le sided loaded oards 'ith nothin! ut $&ass ca&acitors mounted on the ac(. This allo's the $&ass ca&acitor to !et as close to the &h$sical device &o'er &in as &ossi le. +e sure to involve $our )*+ assem ler in discussions durin! the la$out of $our oard. There are man$ thin!s $ou can and can9t do 'ith dou le sided loadin!.
'uto "outing
64eal )*+ desi!ners don9t auto route87% is an a!e old 'ar cr$. <hilst man$ 'ill claim this is true% realit$ ma$ often (ic( in% and there certainl$ are times 'hen $ou do need to consider the use of an auto router. Auto routin! is the &rocess of !ettin! the )*+ soft'are to route the trac(s for $ou. 3t 'ill even attem&t to route $our entire oard if $ou let it. 1ost of the medium to to& ran!e )*+ &ac(a!es 'ill do this% and the technolo!$ and theor$ ehind autoroutin! techni2ues can e mind o!!lin!. Artificial intelli!ence and neural ased technolo!$ are some of the mar(etin! uzz 'ords used. 3f the )*+ &ro!ram can route the oard for $ou% 'h$ not al'a$s use itF Doesn9t it 5ust automate a mundane &rocess li(e la$in! do'n trac(sF The ans'ers can e com&licated and man$% ut no matter ho' 6smart7 an auto router is% it sim&l$ cannot re&lace a !ood human )*+ desi!ner. 3t is li(e tr$in! to as( a com&uter &ro!ram to &aint a &icture for $ou. 3f $ou !ive it enou!h information it ma$ to a le to &roduce somethin! le!i le% ut it 'on9t e artistic% and certainl$ 'on9t e a 1ona Lisa. 1an$ &eo&le thin( that auto routers are a tool to hel& not so e/&erienced )*+ desi!ners. 3n fact% the o&&osite it true8 3n the hands of an ine/&erienced desi!ner% an auto router 'ill &roduce a com&lete mess. +ut in the hands of a ver$ e/&erienced desi!ner% an auto router can &roduce e/cellent results much 2uic(er than the human desi!ner could do. Auto routers come in hand$ 'hen $ou have com&le/ oards 'ith not much routin! s&ace% on non:critical &arts of $our la$out. Eon:critical &arts of a oard mi!ht include lo' fre2uenc$ or static control si!nals to
Page 21 of 2+ 21
PC Design !utorial by David L. Jones com&onents li(e LED dis&la$s% s'itches and rela$s to name a fe'. Advanced autorouters do come 'ith tools to let $ou s&ecif$ e/actl$ ho' $ou 'ant electricall$ im&ortant trac(s laid out. +ut $ the time $ou have told it in e/cruciatin! detail 'hat to do 'ith ever$ trac(% $ou could have la$ed it out $ourself8
Eever use an auto router to do $our com&lete oard% it 'ill e a mess. +ut if $ou let it loose on a ver$ s&ecific non:critical area of $our oard% $ou can !et some e/cellent results% sometimes indistin!uisha le from manual routin!. "ou can even auto route a sin!le connection% and this is sometimes hand$ 'hen $ou are havin! trou le findin! routin! s&ace in the final &hase of $our la$out. @nless $ou are ver$ e/&erienced at )*+ desi!n% sim&l$ sta$ a'a$ from auto routers. This cannot e stressed enou!h. 4eal desi!ners don9t auto route8
'uto Placement
Auto )lacement tools are availa le in man$ hi!her end )*+ &ac(a!es. )rofessional )*+ desi!ners do not use Auto )lacement tools% it9s that sim&le. Don9t rel$ on the Auto )lace feature to select the most o&timum la$out for $ou. 3t 'ill never 'or( ,unless it9s an e/tremel$ sim&le oard-% re!ardless of 'hat the &ro!ram ma(ers claim. These tools do have one useful function ho'ever% the$ !ive $ou an eas$ 'a$ to !et $our com&onents initiall$ s&read across $our oard.
Design #or Manufacturing

Panelisation
3f $ou are loo(in! at !ettin! $our oard automaticall$ assem led 'ith a &ic(:and:&lace machine% then it &a$s $ou to !et as man$ oards onto the one 6&anel7 as $ou can. A &anel is sim&l$ a lar!e )*+ containin! man$ identical co&ies of $our oard. 3t ta(es time to &lace a oard into &osition on a &ic( and &lace machine% so the more oards $ou can load at once% the more cost effective $our manufacturin! 'ill e. A &anel 'ill also contain toolin! stri&s on the to& and ottom% to allo' for automated handlin! of the &anel. Different manufactuers ma$ have different ma/imum &anel sizes the$ can &roduce. Each individual oard can e 6routed out7 and 5oined 'ith 6 rea(out ta s7% or sim&l$ utted to!ether and scoured out 'ith a 6H !roove7. A H !roove is a score mar( &laced on $our oard that allo's $ou to easil$ 6sna&7 the oard alon! the !roove. A rea(out ta is a small stri& of oard &erha&s C:A0mm lon! 5oinin! $our oard to $our &anel. =mall non:&lated holes are also drilled alon! this stri&% 'hich allo's the oard to e sna&&ed or cut out of the &anel after assem l$. "ou 'ill need to consult $our oard loader to determine o&timum &anelisation size and re2uirements.
Tooling Strips
Toolin! stri&s are stri&s of lan( oard do'n the to& and ottom side of $our oard. The$ contain toolin! holes% fiducial mar(s% and other manufacturin! information if re2uired. =tandard toolin! holes are re2uired for automated handlin! of $our oard. 2.4mm and M.2mm are t'o standard hole sizes. .our toolin! holes &er &anel is sufficient% one in each corner. The toolin! tri&s connect to $our oard,s- 'ith rea(out ta s or H ;rooves.
#iducial Marks
.iducial mar(s are visual ali!nment aids &laced on $our )*+. The$ are used $ automated &ic( and &lace machines to ali!n $our oard and find reference &oints. A video camera on the machine can identif$ the center of fiducial mar(s and use these &oints as a reference. On a &anel there should e M fiducial mar(s% (no'n as !lo al fiducials. +ottom leftDri!ht and to& left corners. The$ should e at least Cmm a'a$ from the oard ed!es. The$ can e mounted on the toolin! stri&s. The fiducial mar( should e a circular &ad on the co&&er la$er of diameter A.Cmm t$&icall$. The fiducial should not e covered 'ith solder mas(% and the mas( should e removed for a clearance of at least Mmm around. The &ad can e are co&&er or coated li(e a re!ular &ad. T'o local fiducial ,one in o&&osite corners- is also re2uired ne/t to each lar!e fine &itch surface mount device &ac(a!e on $our oard.
Page 22 of 2+ 22
Thermal "elief
3f $ou solidl$ connect a surface mount &ad to a lar!e co&&er area% the co&&er area 'ill act as a ver$ effective heat sin(. This 'ill conduct heat a'a$ from $our &ad 'hile solderin!. This can encoura!e dr$ 5oints and other solderin! related &ro lems. 3n these situations a thermal relief connection% 'hich com&rises several ,usuall$ 4- smaller trac(s connectin! the &ad to the co&&er &lane. Thermal relief o&tions can e set automaticall$ in man$ &ac(a!es.
Soldering
=olderin! considerations need to ta(en into account 'hen la$in! out $our oard. There are three asic solderin! techni2ues : hand% 'ave% and reflo'. ?and solderin! is the traditional method t$&icall$ used for &rotot$&es and small &roduction runs. 1a5or im&acts 'hen la$in! out $our oard include suita le access for the iron% and thermal reflief for &ads. Eon: &lated throu!h dou le sided oards should allo' for am&le room to !et the solderin! iron onto the to& side &ads. <ave solderin! is a common &rocess used for surface mount and throu!h hole &roduction solderin!. 3t involves &assin! the entire oard over a molten ath of solder. =older mas(s are a solutel$ essential here to &revent rid!in!. The ma5or thin! to 'atch out for 'hen desi!nin! is ensurin! that small com&onents are not in the 'ave solder 6shado'7 of lar!er com&onents. The oard travels throu!h the 'ave solder machine in one direction% so there 'ill e a lac( of solder trailin! ehind lar!er com&onents. =urface mount devices are fi/ed to the oard 'ith an adhesive efore 'ave solderin!. 4eflo' solderin! is the latest techni2ue% and is suita le for all surface mount com&onents. The lan( oard is first coated 'ith a mas( of solder &aste over the &ads ,solder 6stencils7 are used for this-. Then each com&onent is &laced% and is sometimes held in &lace $ an adhesive. The entire oard is then loaded into an infrared or nitro!en oven and 6 a(ed7. The solder &aste melts ,reflo's- on the &ads and com&onent leads to ma(e the 5oint. A ne'er reflo' method called &in:in:&aste or intrusive reflo' is availa le for throu!h hole devices. *om inations of 'ave and reflo' solderin! can e used for mi/ed throu!h hole and surface mount oards. <ave solderin! has the advanta!e of ein! chea&% ut the disadvanta!e of im&osin! &lacement limits on $our com&onents. 4eflo' solderin! is more com&le/ and e/&ensive% ut it allo's for ver$ dense surface mount &ac(in!.
=1D <ave =olderin!
Page 29 of 2+ 29
Throu!h:hole <ave =olderin!
=1D 4eflo' =olderin!
Basic PCB Manufacture

A )*+ usuall$ consists of a lan( fi re!lass su strate ,6the oard7-% 'hich is usuall$ A.Lmm thic(. Other common thic(nesses are 0.Kmm and 2.4mm. There are man$ t$&es )*+ su strate material% ut $ far the most common is a standard 'oven e&o/$ !lass material (no'n as .44. This material has standard (no'n &ro&erties% t$&ical values of 'hich are sho'n in the accom&an$in! ta le. The most often used &arameter is &ro a l$ the dielectric constant. This fi!ure is im&ortant for calculatin! hi!h s&eed transmission line &arameters and other effects. An .44 )*+ is made u& of !lass and resin. ;lass has a dielectric constant of a&&ro/imatel$ L% and the resin has a dielectric constant of a&&ro/imatel$ M. =o an .44 )*+ can t$&icall$ have a fi!ure ran!in! from under 4% to almost C. 3f $ou need an e/act fi!ure $ou 'ill have to consult 'ith $our )*+ manufacturer. ::::::::::::::::::::::::::::::::::::::::::::::::: T$&ical .44 )ro&erties: Dielectric *onstant Dielectric +rea(do'n <ater A sor&tion Dissi&ation .actor Thermal E/&ansion M.9 to 4.K M9(HDmm OA.MJ 0.022 AL:A9&&mDde!*
EOTE: These values can var$ 'ith manufacturers% chec( 'ith $our su&&lier for e/act fi!ures. Other e/otic ase materials li(e Teflon are also availa le% ut are onl$ used for s&ecial desi!ns that re2uire a hi!her !rade ase material for a s&ecific reason. There are chea&er materials than .44% li(e &henolic ase and *E1:A. These are ho $ist !rade oards% ut are also often used in some mass consumer &roducts due to their lo' cost. The$ are not suita le for &lated throu!h holes or fine tolerance desi!ns.
Page 24 of 2+ 24
PC Design !utorial by David L. Jones A lan( ase material coated 'ith co&&er is (no'n as a co&&er clad oard.
A multi:la$er oard is made u& of various individual oards se&arated $ )reim&re!nated +ondin! La$ers% also (no'n as 6&re&re!7. There are different 'a$s to stac( these oard la$ers u&% and this 'ill dictate 'hat $ou can do 'ith &lanes and lindD uried vias. *onsult the manufacturer for their recommendations on this.
Surface #inishies
"ou can !et $our )*+ manufactured 'ith several different t$&es of &ad and trac( surface finish. Her$ lo' cost sin!le and dou le sided oards 'ithout solder mas( t$&icall$ have a asic tin coated finish. +e'are of &otential shorts et'een trac(s 'ith this method. "our standard &rofessionall$ manufactured oard 'ill t$&icall$ have solder mas( over are co&&er ,=1O+*trac(s% and a tin finish on the &ads and vias 'hich is ?ot Air Leveled ,?AL-. ?ot air levelin! hel&s most surface mount com&onents to sit flat on the oard. .or lar!e and critical surface mount com&onents% a !old 6flash7 finish is used on the &ads. This !ives an e/tremel$ flat surface finish for dense fine &itch devices. )eela le solder mas(s are availa le% and are hand$ for tem&orar$ mas(in! of areas on $our oard durin! 'ave solderin! or conformal coatin!.
,lectrical Testing
"ou can have $our finished )*+ chec(ed for electrical continuit$ and shorts at the time of manufacture. This is done 'ith a automated 6fl$in! &ro e7 or 6 ed of nails7 test machine. 3t chec(s that the continuit$ of the trac(s matches $our )*+ file. 3t ma$ cost a fair it e/tra% ut this is &rett$ mandator$ for multi:la$er oards. 3f $ou have a manufacturin! error on one of $our inner la$ers% it can e ver$ difficult to fi/.
Signature
Li(e an$ 'or( of art% no oard is com&lete 'ithout addin! $our name or si!nature to it8 The si!nature can ta(e an$ form $our li(e. =ome &eo&le &ut their name% initials% or a fanc$ s$m ol. <hatever it is% 5ust ma(e sure $ou add somethin!. A si!nature can e &laced on an$ of the co&&er la$ers% or on the com&onent overla$.
Page 2' of 2+ 2'
Su$mitting your design for manufacture

The first thin! to (no' is 'hich format to send $our )*+ file in. 3n Australia the standard format is an$ version of )rotel ,AutoTra/% ).<2.K% 99=E% D>) etc-. Ever$ manufacturer in Australia 'ill ha&&il$ ta(e a )rotel file. 3n fact% )rotel format is their &referred 'a$ to receive a file. 1an$ 'ill also ta(e other &ro&rietar$ formats as 'ell% ut $ou#ll have to chec( 'ith them first. =u&&l$in! the ori!inal )*+ &ac(a!e file 'ill ensure that 'hat $ou see on the screen is 'hat $ou 'ill !et 'hen $our oard is delivered. @nless $ou have a !ood reason to do so% don9t su&&l$ $our file in an$ other format. ;er er files are the traditional and industr$ reco!nised file format% all ma5or manufacturers 'ill acce&t them. 1an$ )*+ desi!ners still insist on !eneratin! and su&&l$in! ;er er files themselves% in order to have total control over the manufacturin! &rocess. 3n all ut a fe' e/treme cases% !eneratin! ;er er files is not necessar$ and a thin! of he &ast. ;eneratin! !er ers adds an e/tra ste& of com&le/it$ to the )*+ &rocess 'here errors can cree& in. =o avoid the use of !er er files 'ere &ossi le% the$ can e trou lesome unless $ou (no' e/actl$ ho' to !enerate them correctl$. The manufacturer 'ill as( for a lot of information efore the$ 2uote% as( them 'hat $ou need to &rovide 'ith $our file. ?ere is a asic chec(list:
A reference code and revision for $our oard. This ma(es it eas$ for oth &arties to trac( the &ro!ress of it. Desired manufacturin! time% (no'n as the 6turn:around7. 24 hours 'ill cost a LOT more than 2 'ee(s8 Guantit$ of oards re2uired +oard thic(ness ,A.Lmm% 0.Kmm% 2.4mm etc-. A.Lmm is standard T$&e of oard ,.44% Teflon etc-. .44 is standard Eum er of la$ers =urface finish ,=1O+*% ?AL% ;old .lash etc-. =1O+* and ?AL is standard. <hat colour $ou 'ant $our solder mas( and com&onent overla$. *o&&er 'ei!ht ,Aoz% 2oz etc-. Aoz is standard. <hether or not $ou 'ant electrical testin!. This is &rett$ necessar$ for multi:la$er oards. The Trac(D=&ace clearance of $our oard ?o' $our oard dimensions are defined. E!% on the mechanical la$er. <hether $ou 'ant oards 6&anelised7 or su&&lied individuall$ cut.
1an$ manufacturers 'ill have 6&rotot$&e7 services 'here the$ 'ill fit as man$ of $our oards onto a standard 6&anel7 as the$ can% all for one fi/ed &rice. 3n most cases $ou 'ill e char!ed a 6toolin!7 cost. This is the cost of &rintin! the &hoto mas(s for $our oard% and also settin! u& their machines. This is usuall$ a one:off cost% so if $ou !et the same oard manufactured a!ain% $ou 'on9t have to &a$ the toolin! char!e. That9s the end of this tutorial. Do $ou elieve that is all there is to (no' a out )*+ desi!nF 3f $ou ans'ered no% then $ou9d e ri!ht8 ;ood )*+ desi!n ta(es lots of e/&erience% so !o !et started on $our ne/t oard.
3a''4 routin%5 -avid 6. 7ones
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PCB Design Tutorial

Revision A - June 29th 2004

PC Design !utorial by David L. Jones

The Old Days

Imperial and Metric

Page ' of 2+ '

PC Design !utorial by David L. Jones

PC Design !utorial by David L. Jones

Working from the top

C0 K0 AA0 AC0 AK0 220 2L0 M00

PC Design !utorial by David L. Jones 2C 40 CC BC 90 AA0 AM0 AC0

A0.M L.4 4.B M.4 2.9 2.M 2.0 A.B

PC Design !utorial by David L. Jones

PC Design !utorial by David L. Jones

&learances #or +lectrical &onductors

Component Placement ! Design

PC Design !utorial by David L. Jones

PC Design !utorial by David L. Jones

An example of GOOD routing (Left) and BAD routing (Right)

PC Design !utorial by David L. Jones

Single Sided Design

PC Design !utorial by David L. Jones

Dou$le Sided Design

Page 1' of 2+ 1'

Design "ule Checking

#or)ard and Back 'nnotation

Multi layer Design

PC Design !utorial by David L. Jones

PC Design !utorial by David L. Jones

*igh #re+uency Design Techni+ues

Dou$le Sided %oading

Design #or Manufacturing

PC Design !utorial by David L. Jones

=1D <ave =olderin!

PC Design !utorial by David L. Jones

Throu!h:hole <ave =olderin!

=1D 4eflo' =olderin!

Basic PCB Manufacture

Page 2' of 2+ 2'

PC Design !utorial by David L. Jones

Su$mitting your design for manufacture

3a''4 routin%5 -avid 6. 7ones

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