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Application Report
Xy dng mt h thng da trn Nios II trn Kit FPGA Leopard I

December 2012 , HFAR01 Rev 1.0 Hoang Nguyen
I. Gii thiu:
Ti liu ny hng dn cho chng ta pht trin mt h thng da trn vi x l Nios II ca Altera. Bng cch s dng phn mm Quartus II v b thit k Nios II nhng EDS, chng ta c th thit k mt h thng Nios II phn cng v giao tip vi cc ngoi vi khc trn board Leopard. Trong phn ny, chng ta ch xem xt cc bc c bn cho php xy dng mt h thng n gin vi y CPU, b nh v cc ngoi vi, cc thit k phc tp khc c th c xem xt chi tit trong cc ti liu khc. Trong ti liu ny ta s thit k mt h thng Nios II trn kit FPGA Leopard I. Kit FPGA Leopard I do phng th nghim H-laboratory pht trin da trn dng chip Cyclone III ca hng Altera . t mua kit Leopard I hoc xem thm cc sn phm khc, vui lng vo website www.titans.com.vn bit thm chi tit , chc nng v hng dn s dng kit FPGA Leopard I, vui lng tham kho ti y: http://titans.com.vn/index.php?page=shop.product_details&product_id=70&option=co m_virtuemart Trong bi vit ny, chng ta s s dng v d thit k mt h thng Nios II nh cho ng dng iu khin. V d ny cho php CPU Nios iu khin Led, nt nhn v giao tip vi my tnh qua cng JTAG UART.
II. Nios II 32-bit CPU v Kit FPGA Leopard I :

1. Nios II 32-bit soft CPU:
Nios II l mt kin trc vi x l 32-bit c thit k chuyn cho cc dng chip FPGA ca Altera Nios II tch hp nhiu tnh nng tin tin v thch hp cho nhiu ng dng t DSP cho ti iu khin. Kin trc ca Nios II l kin trc RISC soft-core, Ngha l Nios II c to thnh hon ton bng cc phn t logic (logic element) v cc memory block ca Altera FPGA. Kin trc soft-core ca vi x l Nios cho php ngi thit k h thng c th ty bin li
Xy dng h thng Nios II trn kit FPGA Leopard I
CPU Nios II theo mc ch thit k. Ngoi ra, ngi thit k c th m rng kh nng ca CPU bng cch thm cc tnh nng nh qun l b nh MMU hoc cc lnh ty bin (custom instruction)
Hnh 1: Nios II 32-bit CPU
Theo nghin cu ca Gartner Research , Altera's Nios II l vi x l soft-core ph bin nht trong ngnh cng nghip FPGA. Nios II bao gm y cc tnh nng ca cc li vi x l hin i nh :

Qun l b nh MMU n v bo v b nh (Memory protection unit MPU ) H thng vector ngt vi cc b iu khin ngt c lp ln ti 32 trn mt b iu khin H thng instruction v data caches ring bit (c th cu hnh t 512 bytes ti 64 KB) Kh nng nh a ch ln ti 2 GB. C th them tightly-coupled memory cho instructions v data tng hiu sut Kin trc 6 tng pipeline t hiu sut MIPS cao (*Dhrystones 2.1 benchmark) trn MHz B nhn v dch phn cng thc thi trong 1 chu k. C th ty chn b chia hardware C kh nng tin on cc lnh r nhnh ng C th thm ti 256 lnh ty bin v khng gii hn cc b tng tc hardware Module JTAG debug c th ty bin Cc tnh nng JTAG debug nng cao, nh hardware breakpoints, data triggers, v realtime trace c th ty chn.
Titans Technology | www.titans.com.vn / www.hlab.com.vn Copyright 2012, Titans Technology
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CPU Nios II c ba cu hnh chnh : Nios II /e core , Nios II /s core , Nios II /f core phn theo hiu sut v chi ph , v c th la chn ph hp cho tng ng dng ring.
Nios II Processor Core Vendor Nios II economy core
Application Power and cost sensitive
Description
Altera With as low as 600 logic elements, the Nios II economy processor core is ideal for microcontroller applications. The Nios II economy processor core, software tools, and device drivers are offered free of charge.
Real time
Nios II Altera Absolutely deterministic, jitter free real-time standard and performance with unique hardware real-time fast core features

Vector Interrupt Controller Tightly Coupled Memory Custom instructions (ability to use FPGA hardware to accelerate a function) Supported by industry-leading RealTime Operating Systems (RTOS) Nios II processor is the ideal real-time processor to use with DSP Builderbased hardware accelerators to provide deterministic, high performance realtime results
Applications processing Nios II fast core
Altera With a simple configuration option, the Nios II fast processor core can use a memory management unit (MMU) to run embedded Linux. Both open source and commercially supported versions of Linux for Nios II processors are available.
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2. Kit FPGA Leopard I ca Titans Technology:

Kit FPGA Leopard I do Titans Technology (www.titans.com.vn ) sn xut theo thit k ca phng th nghim H-laboratory (www.hlab.com.vn) . Kit Leopard thit k da trn FPGA Altera Cyclone III vi kin trc multi-core bao gm chip FPGA giao tip vi chip MCU ARM Cortex M3 ca ST Microelectronics. Board c thit k nhm ti cc thit k v iu khin cn cc b tng tc hardware, hoc cc i tng mi tm hiu v FPGA c th thit k giao tip vi cc ngoi vi c bn nh led, nt nhn, lcd charactor, sd card, uart Ngoi ra, board cng ph hp vi nhng ai pht trin cc li IP cn giao tip vi MCU test nh thit k core I2C, UART, SPI, hay cc giao tip tc cao khc.
Hnh 2: Kit FPGA Leopard I ca Titans technology
FPGA Leopard I Development Kit

Cyclone III EP3C16Q240 ARM Cortex M3 STM32F103RCT 8x User Buttons, 8x general purpose leds USB 2.0 Interface LCD 16x2 charactor. 4x Led 7-Segments 2x RS232 with DB9 Connector MMC/SD Card socket 32KB SRAM 4Mbits EEPROM AS and JTAG configuration support.
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3 Oscilators : 50Mhz, 27Mhz, external SMA 40-Pins Expansion Connector.
Cyclone III EP3C16Q240 o 15.400 LEs. o 56 M9K Memory Blocks. o 516.096 On-chip Memory bits. o 56 18x18 Multipliers. o 4xPLL. o Maximum 160 IOs. STM32F103RCT o ARM 32-bit Cortex-M3 CPU o 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) o 512 Kbytes of Flash memory o 64 Kbytes of SRAM o 3 12-bit, 1 s A/D converters (up to 21 channels) o 2 12-bit D/A converters o DMA: 12-channel DMA controller o Debug Serial wire debug (SWD) & JTAG interfaces o Up to 11 timers 2 o Up to 2 I C interfaces (SMBus/PMBus) o Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) 2 o Up to 3 SPIs (18 Mbit/s), 2 with I S interface multiplexed o USB 2.0 full speed interface o CRC calculation unit, 96-bit unique ID
bit thm chi tit , chc nng v hng dn s dng kit FPGA Leopard I, vui lng tham kho ti y:
http://titans.com.vn/index.php?page=shop.product_details&product_id=70&option=com_virtuemart.
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III. Design Example :

1. H thng Nios II n gin:
Trong ti liu ny, chng ta s thc hin mt h thng Nios II nh cho ng dng iu khin, Nios II s thc hin m v xut ra led, Nios II cng c th giao tip vi nt nhn v giao tip my tnh thng qua JTAG UART. V d v h thng Nios II bao gm nhng thnh phn sau :

Vi x l Nios II /s core (standard) Memory on chip Timer JTAG UART 8-bit parallel I/O (PIO) iu khin LEDs System identification component
Hnh 3 m t h thng v mi quan h gia my tnh, board ,FPGA v h thng Nios II.
5 Hnh 3: H thng Nios II n gin
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Yu cu v phn cng v phn mm: Trong bi ny, chng ta cn cc thnh phn sau.
o Kin thc v Altera Quartus v to project trn phn mm Quartus II (xem ti liu HFAR02 bit cch to project) o Altera Quartus II software version 9.0 hoc cao hn. o Nios II EDS version 9.0 hoc cao hn o Kit FPGA Leopard I (xem ti y ) o Cp USB Blaster (xem ti y ) o Kt ni Kit Leopard vi PC nh hnh 4
Hnh 4: H thng Nios II trn kit Leopard I
2. To Altera Quartus Project s dng block diagram:

Trc tin, ta phi to project trn Quartus trc, tham kho ti liu HFAR02 bit cch to mt project trn Quartus Altera . Sau , ta to mt file mi block diagram cho ton b h thng. t tn file l nios2_9_0.bdf
Hnh 5: To file .bdf cho h thng Titans Technology | www.titans.com.vn / www.hlab.com.vn Copyright 2012, Titans Technology HFAR01
Sau ta thm cc chn input/output cho h thng bng symbol tool :
Hnh 6: To chn in/out cho h thng
To cc chn :CLK (input),VCC (power) , BUTTON[7..0] (input), LED[7..0] (output)
Hnh 7: Giao din thit k ca file Nios2_9_0.bdf
Tip theo, ta s phi to h thng Nios II s dng SoPC Builder:
3. To h thng Nios II s dng Altera SoPC Builder:

Click vo biu tng SOPC Builder to h thng Nios II.
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Hnh 8: SOPC Builder
Hnh 9: Giao din SOPC Builder
Trc tin ta to b nh memory onchip trc.

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Trong h thng no th CPU cng cn phi c b nh cho d liu v lnh. Trong thit k v d ny, ta s 20 KB on-chip memory cho c data v instructions. thm memory vo h thng, thc hin cc bc sau: o Trn tab Component Library (bn tay tri ca tab System Contents), trong
Titans Technology | www.titans.com.vn / www.hlab.com.vn Copyright 2012, Titans Technology HFAR01
Xy dng h thng Nios II trn kit FPGA Leopard I Memories and Memory Controllers, m On-Chip, v click vo On-Chip Memory (RAM or ROM). Click Add. Bng cu hnh thng s xut hin nh hnh 10. Trong danh sch Block type, chn Auto. Trong hp thoi Total memory size, nh vo 20480 c 20 KB. ng thay i cc thng s mc nh no ht .
o o o o
9 Hnh 10: Giao din cu hnh tham s on-chip memory
o Click Finish, quay tr li SoPC Builder Tool.

Xy dng h thng Nios II trn kit FPGA Leopard I o Click chut phi vo on-chip memory mi to, i tn thnh onchip_mem .
Tip theo ta to CPU Nios II Trong phn ny, ta s them CPU Nios II/s core v cu hnh cho n s dng b nh cache lnh 2 KB on-chip. Thc hin cc bc sau thm Nios II/s core vo h thng:
o o o o o o o o o o Trong tab Component Library, m Processors, v click vo Nios II Processor. Click Add. Xut hin hp thoi cu hnh thng s cho Nios II nh hnh 11. Di phn Select a Nios II core, chn Nios II/s. Trong danh sch Hardware multiplication type, chn Embedded Multipliers. Tt mc Hardware divide. Trong phn Reset Vector chn onchip_mem Trong phn Exception Vector chn onchip_mem Trong tab Caches and Memory Intefaces chn Instruction Cache 2 Kbytes Cc mc khc mc nh Click Finish. Quay tr li tab SOPC System Contents, v mt con CPU Nios II xut hin trong bng system contents.
10 Hnh 11: Giao din cu hnh tham s CPU Nios II /s Core
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Xy dng h thng Nios II trn kit FPGA Leopard I o Trong phn connection, m bo kt ni gia Nios II instruction_master , data_master , jtag_debug_module kt ni ti port s1 ca onchip_mem . o Click chut phi vo CPU mi to, i tn thnh cpu .
Thm JTAG UART Module JTAG UART cho php ta giao tip d liu gia vi x l Nios II processor vi my tnh thng qua cp USB-Blaster. Thc hin cc bc sau thm module JTAG UART:
o Trong tab Component Library, M phn Interface Protocols, chn Serial, v click chn JTAG UART. o Click Add. Bng cu hnh thng s cho JTAG UART xut hin nh hnh 12. o ng thay i bt c thng s mc nh no.
Hnh 12: Giao din cu hnh tham s JTAG UART 11
o Click Finish. Quay tr li SOPC System Contents tab , thnh phn JTAG UART xut hin trong bng system contents o Click chut phi vo module JTAG UART, i tn thnh jtag_uart.
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Xy dng h thng Nios II trn kit FPGA Leopard I o m bo c kt ni gia Nios II data_master port vi Avalon_jtag_slave ca JTAG UART
Thm b Interval Timer. Hu ht cc h thng iu khin u s dng thnh phn timer tnh ton thi gian chnh xc. c nhp clock h thng theo chu k, Nios II HAL cn mt timer. Thc hin cc bc sau them timer vo h thng :
o Trong tab Component Library, m Peripherals, chn Microcontroller Peripherals, v click chn Interval Timer. o Click Add. Bng cu hnh thng s cho Interval Timer xut hin nh hnh 13 o Trong danh sch Presets, chn Full-featured. o ng thay i bt c thng s mc nh no.
12 Hnh 13: Giao din cu hnh tham s Interval Timer Titans Technology | www.titans.com.vn / www.hlab.com.vn Copyright 2012, Titans Technology HFAR01
Xy dng h thng Nios II trn kit FPGA Leopard I o Click Finish. Quay tr li SOPC System Contents tab , thnh phn Interval Timer xut hin trong bng system contents o Click chut phi vo module Interval Timer, i tn thnh sys_clk_timer. o m bo c kt ni gia Nios II data_master port vi port s1 ca sys_clk_timer
Thm System ID Peripheral Module system ID peripheral cho php m bo h thng c bin dch ti nhng thi im khc nhau s c s ID khc nhau m bo phn mm s c download xung ng h thng mong mun. Thc hin cc bc sau them system ID Peripheral vo h thng :
o Trong tab Component Library, m Peripherals, chn Debug and Performance , v click chn System ID Peripheral. o Click Add. Bng cu hnh thng s cho System ID Peripheral s xut hin nh hnh 14. o ng thay i bt c thng s mc nh no.
Hnh 14: Giao din cu hnh tham s System ID Peripheral
o Click Finish. Quay tr li SOPC System Contents tab , thnh phn System ID Peripheral xut hin trong bng system contents o Click chut phi vo module System ID Peripheral, i tn thnh sysid. o m bo c kt ni gia Nios II data_master port vi port control_slave ca sysid
Thm PIO Thnh phn PIO l cch d nht Nios II c th nhn tn hiu t bn ngoi, hoc iu khin mt tn hiu output. Cc ng dng iu khin phc tp c th cn hng trm tn hiu PIO, trong v d ny, ta ch cn 8 tn hiu PIO iu khin 8 n led trn board. Thc hin cc bc sau them thnh phn PIO.
o Trong tab Component Library, m Peripherals, chn Microcontroller Peripherals, v click chn PIO (Parallel I/O).
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Xy dng h thng Nios II trn kit FPGA Leopard I o Click Add. Bng cu hnh thng s cho PIO (Parallel I/O) xut hin nh hnh 15 o ng thay i bt c thng s mc nh no.
Hnh 15: Giao din cu hnh tham s PIO
o Click Finish. Quay tr li SOPC System Contents tab , thnh phn PIO xut hin trong bng system contents o Click chut phi vo module PIO, i tn thnh led_pio. o m bo c kt ni gia Nios II data_master port vi port s1 ca led_pio
Gn khng gian a ch v a ch ngt Ti thi im ny, chng ta c tt c cc thnh phn cn thit to thnh mt h thng hon chnh. By gi, ta phi ch nh cch m cc thnh phn giao tip vi nhau. Ta s phi gn a ch base address cho mi thnh phn slave trong khng gian ca nios master , v gn mc u tin ngt (IRQ) cho JTAG UART v interval timer. Ch s ngt cng nh th mc u tin cng ln. Thc hin cc bc sau gn khng gian a ch v u tin ca ngt.
o Trong tab system , chn Auto-Assign base addresses
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Xy dng h thng Nios II trn kit FPGA Leopard I o Trong tab system contents , IRQ bn tay phi, nhp IRQ cho interval timer l 1, cn jtag_uart l 16. V timer cn u tin cao hn duy tr hot ng ca ton h thng.
Hnh 16 m t h thng Nios II hon chnh trong v d ny
Hnh 16: H thng Nios II hon chnh
To h thng (System Generation) Chng ta sn sang to h thng SOPC. Thc hin cc bc sau :
o Click vo tab System Generation. o Chn None cho Create simulation model. o Click Generate. Click Save v ch h thng hon tt nh hnh 17. Nu h thng yu cu t tn th nh nios2_sys
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Hnh 17: Giao din hon tt
o Click Exit. Quay tr li giao din thit k ca quartus
4. Tch hp h thng SoPC Builder vo project Quartus II:

Trong phn ny, chng ta s phi thc hin cc bc sau hon thnh thit k hardware. o Tch hp SoPC system vo project quartus II o Chn chip FPGA v gn chn o Compile project o V test trn kit Leopard I Tch hp SoPC system vo project tch hp h thng SOPC vo h thng quartus .bdf, thc hin cc bc sau:
o Chn hp thoi Symbol trn thanh cng c. o Di mc Libraries, m Project. o Chn nios2_sys. Hp thoi Symbol s hin th symbol nios2_sys nh hnh 18.
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Hnh 18: Symbol nios2_sys
o Click OK. Quay tr l .bdf schematic. Symbol nios2_sys s nm trong khng gian thit k ca quartus. o Ni cc chn to t trc vi cc chn ca Nios_sys. a chut ti gn chn ni dy t chn . o Lu li file .bdf hon chnh, click Save trn menu File. Figure 19 cho ta thy h thng .bdf schematic hon chnh vi cc chn iu khin led.
Hnh 19: H thng hon chnh
Trong ca s qun l project, ta thy cc file nh hnh 20 :
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Hnh 20: Project Navigator
Chn chip FPGA v gn chn Trong phn ny, chng ta s phi chn thit b FPGA ph hp vi board Leopard v gn chn cho ph hp vi board Leopard. gn thit b FPGA, thc hin cc bc sau :
o Trn menu Assignments, click Device. Hp thoi Device xut hin. o Trong danh sch Family list, chn dng Cyclone III. o Torng mc Target device, chn Specific device selected in 'Available devices' list. o Trong mc Available devices, chn EP3C16Q240C8. o Chn OK. Figure 21 m t hp thoi Device .
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Hnh 21: Hp thoi Device Setting
gn chn FPGA, Thc hin cc bc sau:

o Trong menu Processing, Vo Start, v click chn Start Analysis & Elaboration chun b cho vic gn chn. Qu trnh ny c th mt vi pht v kt thc khi c hp thoi xc nhn xut hin. o Click OK. o Trn menu Assignments, click Pin Planner. Bng Quartus II Pin Planner xut hin. o Trong ct Node Name, gn chn theo hnh 22.
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Hnh 22: Hp thoi Pin Planner
o o o o o
Click OK. Trn menu Assignments, click Device. Bng hi thoi Device xut hin. Click Device and Pin Options, Bng hi thoi Device and Pin Options xut hin. Click vo trang Unused Pins . Trong danh sch Reserve all unused pins , chn As input tri-stated with weak pull-up . Vi la chn ny, tt c cc chn khng dng trn thit b FPGA s c trng thi tng tr cao. Ch , lun lun dng option ny trnh lm h cc chn IO v linh kin trn board do cc chn khng dng c mc in p xung t o Click OK ng cc hp thoi.
Bin dch h thng v kim tra timing Chng ta phi bin dch h thng to ra file .sof m c th download xung board. Sau khi bin dch xong, chng ta phi kim tra timing ca thit k c lm vic di iu khin ca phn cng hay khng. m bo thit k t yu cu v timing, thc hin cc bc sau :
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o o o o
Trn menu File, click New. Trong danh sch file, Chn Synopsys Design Constraints File (*.sdc). t tn l hw_leopard.sdc v click OK. M file trong chng trnh Editor Thm dng lnh create_clock : create_clock -name sopc_clk -period 20 [get_ports CLK].
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Xy dng h thng Nios II trn kit FPGA Leopard I o o o o o Click Save Trong menu Assignments , chn Settings . Trong mc Timing Analyzer Setting ,chn TimeQuest Timing Analyzer Browse file hw_leopard.sdc v nhn add thm vo danh sch. Bt mc Enable multicorner timing analysis during compilation nh hnh 23
Hnh 23: TimeQuest Timing Analyzer
o Click OK v bt u bin dch. o Sau khi bin dch xong s hin ra bng thng bo nh hnh 24
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Hnh 24: Compilation Report
o M mc TimeQuest Timing Analyzer trong compilation Report o Click Multicorner Timing Analysis Summary o Kim tra gi tr Worst-case Slack phi dng i vi Setup, Hold , Recovery v Removal. Ch ,ch kim tra cho clock sopc_clk m thi. Nu c bt c gi tr no m th h thng s khng th hot ng trn phn cng c. Trong trng hp ny, gim tn s dao ng xung t c timing theo yu cu.
Chng ta hon tt thit k v sn sang np chng trnh cung board Leopard th nghim. Download v test trn kit Leopard I Trong phn ny, chng ta s download file .sof xung board Leopard. Thc hin cc bc sau:
o Kt ni board Leopard vi my tnh host bng cp USB-Blaster, Sau cm ngun vo board. o Trn menu Tools ca phn mm Quartus II, click Programmer. Cng c Quartus II Programmer xut hin vi file cu hnh mc nh (nios2_9_0.sof) nh Hnh 25.
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Hnh 25: Quartus II Programming
o Nu cha c cp USB-Blaster xut hin, kim tra cp v click vo Hardware

Setup kim tra cp download. Nu vn khng c, kim tra driver ci hay cha o Click Close o Trong hng nios2_9_0 , check vo Program/Configure. o Click Start . Khi thanh Progess t 100% ngha l h thng Nios II c cu hnh v hot ng trn FPGA Leopard. Tuy nhin, n vn cha c chng trnh g thc thi c.
5. Pht trin software s dng Nios II IDE Eclipse :

Trong phn ny,chng ta s lm quen vi chng trnh Nios II SBT for Eclipse v bin dch mt chng trnh C n gin. Phn ny ch nu ra cc bc c bn nht pht trin software da trn phn cng h thng to phn trc. Trong phn ny, chng ta s thc hin cc bc sau :
o To mt Nios II C/C++ application and BSP projects mi o Bin dch project.
thc hin phn ny, chng ta phi c file .ptf c to ra phn trc. To mt project Nios II Application and BSP mi t Template c sn Trong phn ny, chng ta s to mt project Nios II C/C++ application and BSP mi . Thc hin theo cc bc sau :
o Khi ng chng trnh Nios II 9.0 IDE. o Nu hp thoi Workspace Launcher xut hin, click OK chn v tr workspace mc nh. o Trn menu File, chn New, Click vo Nios II C/C++ Application. Ca s wizard cho Nios II C/C++ Application xut hin nh hnh 26.
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Hnh 26: Nios II New C/C++ Application project
o Di mc Select Target Hardware , ti SOPC Builder System PTF Files , o o o o o

browse ti th mc hin ti, chn file nios2_sys.ptf v click Open . Trong Name , nh vo ch count_binary. Trong mc Select Project Template , chn Count Binary. Click Next . Check vo mc Create a New system library named : count_binary_syslib Click Finish
By gi Nios II IDE to v hin th project mi trong ca s Project Explorer , thng nm bn tay tri nh hnh 27
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Hnh 26: Giao din Nios II IDE
Bin dch project Trong phn ny, chng ta s bin dch project to ra mt file thc thi. V trong v d ny ta ch c mt h thng nios nh, do ta s phi iu chnh mt s setting gim thiu kch thc th vin, bi v h thng Nios II hardware ch c 20 KB b nh m thi. Thc hin theo cc bc sau :
o Trong ca s Project Explorer, click phi vo count_binary_syslib v click Properties. Ca s Properties for count_binary_syslib xut hin. o Click vo System Library. iu chnh cc mc sau : Check vo mc Reduced device drivers. Tt mc Support C++. Check vo mc Small C library. Tt mc ModelSim only, no hardware support. o Click OK . o Trong ca s Project Explorer , click Build Project o Sauk hi build hon tt, mt thng tin s xut hin trn ca s Console.
Chy ng dng Nios II trn Kit Leopard I
Trong phn ny, chng ta s download chng trnh xung kit hardware v thc thi n. download file thc thi, thc hin cc bc sau :
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o Click phi vo project count_binary , chn Run As , click vo Nios II Hardware. Nios II IDE s download code thc thi vo board Leopard v chng trnh bt u chy.
Xy dng h thng Nios II trn kit FPGA Leopard I o Nu hp thoi Run Configuration xut hin, th chng ta phi kim tra li tn Project Name , File ELF ,v File .sof c np xung Kit Leopard cha, sau Click Run. o Khi board Leopard chy, Mn hnh Console ca Nios II trn my PC s hin th cc k t m nh hnh 27, v led trn board leopard s m theo s nh phn sau mi giy. o Click vo iocn Terminate (hnh vung mu ) dng CPU Nios II li nu mun CPU ng li.
Hnh 27: Output t hardware ln mn hnh Console ca Nios II IDE
Chng ta c th sa li file chng trnh count_binary.c trong giao din pht trin Nios II IDE v lp li cc bc trn thay i chng trnh theo yu cu thit k ca mi ngi. Nh vy l chng ta hon tt cc bc pht trin mt h thng Nios II trn Kit Leopard I, v chng ta c th pht trin cc ng dng phc tp hn, giao tip vi cc ngoi vi bn ngoi phc tp hn trong cc ti liu hng dn sau.
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IV. Hnh nh Demo trn Kit Leopard I:

V d thit k c thc thi trn Kit Leopard ,v Nios II ang iu khin cc led m theo m nh phn, ng thi xut gi tr m ln PC thng qua cp USB-Blaster
27 Hnh 28: Led trn Kit Leopard ang m theo s nh phn
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Table of Contents
Application Report .................................................................................................... 0 Xy dng mt h thng da trn Nios II trn Kit FPGA Leopard I .......................................... 0 I. II. 1. 2. III. 1. 2. 3. 4. 5. IV. Gii thiu: .................................................................................................................................................... 0 Nios II 32-bit CPU v Kit FPGA Leopard I :............................................................................................ 0 Nios II 32-bit soft CPU:............................................................................................................................ 0 Kit FPGA Leopard I ca Titans Technology: ........................................................................................... 3 Design Example : .................................................................................................................................... 5 H thng Nios II n gin:...................................................................................................................... 5 To Altera Quartus Project s dng block diagram: ............................................................................ 6 To h thng Nios II s dng Altera SoPC Builder:............................................................................... 7 Tch hp h thng SoPC Builder vo project Quartus II: ....................................................................16 Pht trin software s dng Nios II IDE Eclipse : ................................................................................23 Hnh nh Demo trn Kit Leopard I: ......................................................................................................27
Reference .......................................................................................................................................................29 Document Revision History..............................................................................................................................29
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Reference
tt_nios2_hardware_tutorial Wikipedia.com Websites from Internet http://www.altera.com
Document Revision History

HFAR01 Rev 1.0 ( 12/2012 ) Phin bn u tin
Copyright 2009 Titans Technology. Ti liu ny thuc bn quyn ca Titans Technology (www.titans.com.vn), chng ti hy vng cc bn khi s dng vi bt k mc ch no bng bt c hnh thc no bao gm sao chp, in, copy, trch dn cn phi ghi r xut x ngun gc t trang web ca chng ti Hy truy xut trang web ca chng ti thng xuyn c nhng cp nht mi nht v cc thit b mi nht ti website www.titans.com.vn. Nu c bt c kin ng gp cng nh cn h tr, t vn thm thng tin v sn phm, vui lng gi mail n a ch email: support@titans.com.vn
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Application Report

Xy dng mt h thng da trn Nios II trn Kit FPGA Leopard I

II. Nios II 32-bit CPU v Kit FPGA Leopard I :

Xy dng h thng Nios II trn kit FPGA Leopard I

Hnh 1: Nios II 32-bit CPU

Titans Technology | www.titans.com.vn / www.hlab.com.vn Copyright 2012, Titans Technology

Xy dng h thng Nios II trn kit FPGA Leopard I

Application Power and cost sensitive

Applications processing Nios II fast core

Titans Technology | www.titans.com.vn / www.hlab.com.vn Copyright 2012, Titans Technology

Xy dng h thng Nios II trn kit FPGA Leopard I

2. Kit FPGA Leopard I ca Titans Technology:

Hnh 2: Kit FPGA Leopard I ca Titans technology

FPGA Leopard I Development Kit

Titans Technology | www.titans.com.vn / www.hlab.com.vn Copyright 2012, Titans Technology

Xy dng h thng Nios II trn kit FPGA Leopard I

3 Oscilators : 50Mhz, 27Mhz, external SMA 40-Pins Expansion Connector.

Titans Technology | www.titans.com.vn / www.hlab.com.vn Copyright 2012, Titans Technology

Xy dng h thng Nios II trn kit FPGA Leopard I

III. Design Example :

5 Hnh 3: H thng Nios II n gin

Titans Technology | www.titans.com.vn / www.hlab.com.vn Copyright 2012, Titans Technology

Xy dng h thng Nios II trn kit FPGA Leopard I

Hnh 4: H thng Nios II trn kit Leopard I

2. To Altera Quartus Project s dng block diagram:

Xy dng h thng Nios II trn kit FPGA Leopard I

Sau ta thm cc chn input/output cho h thng bng symbol tool :

Hnh 6: To chn in/out cho h thng

To cc chn :CLK (input),VCC (power) , BUTTON[7..0] (input), LED[7..0] (output)

Hnh 7: Giao din thit k ca file Nios2_9_0.bdf

Tip theo, ta s phi to h thng Nios II s dng SoPC Builder:

3. To h thng Nios II s dng Altera SoPC Builder:

Titans Technology | www.titans.com.vn / www.hlab.com.vn Copyright 2012, Titans Technology

Xy dng h thng Nios II trn kit FPGA Leopard I

Hnh 8: SOPC Builder

Hnh 9: Giao din SOPC Builder

Trc tin ta to b nh memory onchip trc.

9 Hnh 10: Giao din cu hnh tham s on-chip memory

o Click Finish, quay tr li SoPC Builder Tool.

10 Hnh 11: Giao din cu hnh tham s CPU Nios II /s Core

Titans Technology | www.titans.com.vn / www.hlab.com.vn Copyright 2012, Titans Technology

Hnh 12: Giao din cu hnh tham s JTAG UART 11

Titans Technology | www.titans.com.vn / www.hlab.com.vn Copyright 2012, Titans Technology

Hnh 14: Giao din cu hnh tham s System ID Peripheral

Hnh 15: Giao din cu hnh tham s PIO

Hnh 16 m t h thng Nios II hon chnh trong v d ny

Hnh 16: H thng Nios II hon chnh

Titans Technology | www.titans.com.vn / www.hlab.com.vn Copyright 2012, Titans Technology

Xy dng h thng Nios II trn kit FPGA Leopard I

Hnh 17: Giao din hon tt

o Click Exit. Quay tr li giao din thit k ca quartus

4. Tch hp h thng SoPC Builder vo project Quartus II:

Titans Technology | www.titans.com.vn / www.hlab.com.vn Copyright 2012, Titans Technology

Xy dng h thng Nios II trn kit FPGA Leopard I

Hnh 18: Symbol nios2_sys

Hnh 19: H thng hon chnh

Trong ca s qun l project, ta thy cc file nh hnh 20 :

Titans Technology | www.titans.com.vn / www.hlab.com.vn Copyright 2012, Titans Technology

Xy dng h thng Nios II trn kit FPGA Leopard I

Hnh 20: Project Navigator

Titans Technology | www.titans.com.vn / www.hlab.com.vn Copyright 2012, Titans Technology

Xy dng h thng Nios II trn kit FPGA Leopard I

Hnh 21: Hp thoi Device Setting