LUN VN TT NGHIP

TI

Lp trnh PIC16F877A
iu khin tc
ng c DC

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MC LC

Chng I: KHI QUT TI

I/ Tm tt ti:
1/ Gii thiu s lc cc modul ca mch:
-Tn ti n 2:Lp trnh PIC16F877A iu khin tc ng c DC
-Yu cu t ra: Lp trnh C cho Pic 16F877A iu khin tc cho ng c DC c
gn encoder hi tip tc .Tc c ci t t bn phm v tc tc thi hi tip
t encoder c hin th trn mn hnh LCD 16x2.
-Tm tt hng thc hin ti:
S dng Pic 16F877A l vi iu khin trung tm. Dng chng trnh CCS lp
trnh C v bin dch chng trnh.
Xy dng khi bn phm gm 16 phm nhp tc v iu khin ng c
DC:
10 phm t 0 n 9 ci t tc (vng /phc).
1 phm SET (hay ENTER) lu tc ci t.
1 phm CLEAR xa tc ci t.
1 phm SAVE lu tc vo epprom.
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V Vn Chnh

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3 phm iu iu khin: quay thun (FORWARD), quay nghich

(REVERSE), dng (STOP).
Hin th tc dng mn hnh LCD 16x2, lp trnh ch 4 bit (s dng 4
chn nhn d liu t Pic).
S dng mch cu H l IC L298N o chiu ng c.
S dng 2 knh PWM ca vi iu khin Pic thay i gi tr p trung bnh t
vo ng c iu khin tc .
i tng iu khin l ng c DC 12V c gn Encoder.
Ngoi ra trn mch cn c 1 phm ngun (POWER) cp in t adapter cho
mch v 1 phm RESET cho pic 16F877A.
cp ngun cho mch ta dng adapter AC/DC (220V/12V) v khi ngun s
dng IC 7805 n p in p 5V cung cp cho Pic.

2/ S nguyn l mch:
VCC

LCD1

R1

R2

R3

R4

5k

5k

5k

5k

FW(16)

RV(15)

STOP (14)

7
8
9
10
a4 11
a5 12
a6 13
a7 14

b0 4
b1 5
b2 6

RV1
1
2
3

0 (10)

CLEAR (11)

D0
D1
D2
D3
D4
D5
D6
D7

RS
RW
E

VSS
VDD
VEE

16_X_2_LCD

13

p0
p1
p2
p3

1K

set (12)

C1

+12V
+12V

30pF

VCC

2
3
4
5
6
7
8
9
10

R5
R9

2k2

10k

RESET

OSC1/CLKIN
OSC2/CLKOUT

RB0/INT
RB1
RB2
RA0/AN0
RB3/PGM
RA1/AN1
RB4
RA2/AN2/VREF-/CVREF
RB5
RA3/AN3/VREF+
RB6/PGC
RA4/T0CKI/C1OUT
RB7/PGD
RA5/AN4/SS/C2OUT
RC0/T1OSO/T1CKI
RE0/AN5/RD
RC1/T1OSI/CCP2
RE1/AN6/WR
RC2/CCP1
RE2/AN7/CS
RC3/SCK/SCL
RC4/SDI/SDA
MCLR/Vpp/THV
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7

C3
10uF

PIC16F877A

15
16
17
18
23
24
25
26

CLK
9

J3

CCP1
CCP2

5
7
10
12
6
11

CCP2
CCP1

5
4
3
2
1

CLK

SIL-100-05

19 b2
20 b0
21 b1
22
27 a4
28 a5
29 a6
30 a7

1
15

VS
OUT1
OUT2
OUT3

SENSA
SENSB GND

R1

R2

0.5

0.5

U1

IN1 VCC
IN2
IN3
IN4
ENA
ENB

OUT4

M1

CLK

M1

13

M2

M2

14

+88.8

L298

U2

+12V

D21N4007

p0
p1
p2
p3

D31N4007

CRYSTAL

D11N4007

X1

33
34
35
36
37
38
39
40

D41N4007

C2

U1
13
14

+5V

7805

J1
JACK

3
2
1

VI

VO

R26

C5

100uF

100nF

J2

1k

GND

C4

30pF

C6

C7

100uF

100nF

D8
LED

2
1
TERMINAL2

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Hnh 1: S nguyn l mch

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3/Cch vn hnh mch:

Bc 1:
Bt ngun (nhn nt POWER), ch cho Pic v mn hnh LCD khi ng, mn hnh
hin th: CHN CH :
Chng trnh c 2 ch lm vic: ch 1 l bm tc t, c lu tc vo
epprom; ch 2 l bm tc c nh thi gian thay i chiu quay.
Bc 2:
Nhp tc t bn phm cc phm t 0 n 9.Nu nhp sai ta nhn phm CLEAR con
tr trn LCD s xa ht cc s nhp, ta phi nhp li t u.Sau khi nhp xong,
nhn phm ENTER lu tc t, tc t c tnh theo n v vng/pht.
Nu l ch 2 th ta phi nhp them thi gian, sau nhn phm ENTER
Bc 3:
iu khin ng c ta nhn phm: quay thun (FORWARD), quay nghch
(REVERSE), dng (STOP).
Bc 4:
nhp li tc ta nhn phm CLEAR ri tin hnh t tc nh bc 2.
-Tc tc thi ca ng c s c cp nht mi 0,5s v s c so snh vi tc
t a ra tnh hiu iu khin, ng thi c mi 0,5s tc s hin th trn mn
hnh LCD.

4/ Khuyt im ca mch:
-Do khng p dng cc phng php iu khin (v d nh: PID, iu khin m,)
nn tc ng c cha c n nh.
-Mch cu H s dng IC L298 ch iu khin c ng c DC c cng sut nh.
-i vi khi hin th, do tnh cht ca mn hnh LCD nn b hn ch quan st gi tr
hin th khong cch xa.

5/ Hng pht trin ti:

-

Ci thin n nh tc ng c bng phng php PID hay iu khin m.

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Tnh ton thit k mch cng sut c th iu khin c ng c c cng sut

ln hn.

S dng led 7 on tng kh nng quan st ca khi hin th.

Kt ni vi my tnh, s dung visual basic lp trnh iu khin tc ng c

DC.

CHNG II:
GII THIU V CC LINH KIN PHN T S DNG TRONG MCH

I.Vi iu khin PIC16F877A

1. Khi qut v vi iu khin PIC16F877A
a/ Khi qut:
-

PIC l tn vit tt ca Programmable Intelligent computer do hng General

Instrument t tn cho con vi iu khin u tin ca h.Hng Micrchip tip tc
pht trin sn phm ny v cho n hng to ra gn 100 loi sn phm khc
nhau.

PIC16F887A l dng PIC kh ph bin, kh y tnh nng phc v cho hu ht

tt c cc ng dng thc t. y l dng PIC kh d cho ngi mi lm quen vi
PIC c th hc tp v to nn tn v h vi iu khin PIC ca mnh.

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PIC 16F877A thuc h vi iu khin 16Fxxx c cc t tnh sau:

Ngn ng lp trnh n gin vi 35 lnh c di 14 bit.
Tt c cc cu lnh thc hin trong 1 chu k lnh ngoi tr 1 s cu lnh r
nhnh thc hin trong 2 chu k lnh. Chu k lnh bng 4 ln chu k dao ng ca
thch anh.
B nh chng trnh Flash 8Kx14 words, vi kh nng ghi xo khong 100
ngn ln.
B nh Ram 368x8bytes.
B nh EFPROM 256x8 bytes.
Kh nng ngt (ln ti 14 ngun c ngt trong v ngt ngoi).
Ngn nh Stack c chia lm 8 mc.
Truy cp b nh bng a ch trc tip hoc gin tip.
Di in th hot ng rng: 2.0V n 5.5V.
Ngun s dng 25mA.
Cng sut tiu th thp:
<0.6mA vi 5V, 4MHz
20uA vi ngun 3V, 32 kHz.
C 3 timer: timer0, 8 bit chc nng nh thi v b m vi h s t l
trc.Timer1, 16 bit chc nng b nh thi, b m vi h s t l trc, kch
hot ch Sleep.Timer2, 8 bit chc nng nh thi v b m vi h s t l
trc v sau.
C 2 knh Capture/ so snh in p (Compare)/iu ch rng xung PWM 10
bit / (CCP).
C 8 knh chuyn i ADC 10 bit.
Cng truyn thong ni tip SSP vi SPI phng thc ch v I 2C (ch/ph).B
truyn nhn thng tin ng b, d b (USART/SCL) c kh nng pht hin 9 bit
a ch.
Cng ph song song (PSP) vi 8 bt m rng, vi RD, WR v CS iu khin.

SVTH: Trn Tng Bng

V Vn Chnh

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Do thi gian lm n c hn nn chng em ch tp trung tm hiu cc tnh

nng ca PIC 16F877A c lin quan n ti, di y l 1 vi tnh nng ca
PIC 16F877A c ng dng trong n nh:
-

T chc b nh ca PIC 16F877A.

Chc nng ca cc Port I/O.

Chc nng v cch thit lp cc tham s ca 3 Timer 0,1,2.

Chc nng v cch thit lp b iu ch rng xung PWM.

nh ngha ngt, cc ngun ngt v tm hiu su v ngt timer v ngt

ngoi l hai chc nng c s dng trong ti ny.

SVTH: Trn Tng Bng

V Vn Chnh

Hnh 2: S nguyn l PIC 16F877A

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b/S chn v s nguyn l ca PIC16F877A

S chn

SVTH: Trn Tng Bng

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Hnh 3: S chn ca PIC 16F877A

GVHD: Nguyn Thanh Tho

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S nguyn l

Hnh 4: S nguyn l cc Port ca PIC 16F877A

c/Nhn xt:
T s chn v s nguyn l trn, ta rt ra cc nhn xt ban u nh sau :
-

PIC16F877A c tt c 40 chn

40 chn trn c chia thnh 5 PORT, 2 chn cp ngun, 2 chn GND, 2

chn thch anh v mt chn dng RESET vi iu khin.

5 port ca PIC16F877A bao gm :

+ PORT B: 8 chn
+ PORT D: 8 chn
+ PORT C: 8 chn
+ PORT A: 6 chn

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+ PORT E: 3 chn
2. T chc b nh:
Cu trc b nh ca vi iu khin PIC16F877A bao gm b nh chng trnh
(Program memory) v b nh d liu (Data Memory).
2.1. B nh chng trnh:
B nh chng trnh ca vi iu khin PIC16F877A l b nh flash, dung lng b
nh 8K word (1 word = 14 bit) v c phn thnh nhiu trang (t page0 n page 3) .
Nh vy b nh chng trnh c kh nng cha c 8*1024 = 8192 lnh (v mt lnh
sau khi m ha s c dung lng 1 word (14 bit). m ha c a ch ca 8K word
b nh chng trnh, b m chng trnh c dung lng 13 bit (PC<12:0>).
Khi vi iu khin c reset, b m chng trnh s ch n a ch 0000h (Reset
vector).Khi c ngt xy ra, b m chng trnh s ch n a ch 0004h (Interrupt
vector). B nh chng trnh khng
bao gm b nh stack v khng c
a ch ha bi b m chng trnh.
2.2. B nh d liu:
-

B nh d liu ca PIC16F877A

Hnh 5: Cu trc b nh chng trnh PIC

16F877A

c chia thnh 4 bank. Mi

bank c dng lng 128 byte.
-

Nu nh 2 bank b nh d liu
ca 8051 phn chia ring bit :
128 byte u tin thuc bank1 l
vng Ram ni ch cha d
liu, 128 byte cn li thuc bank
2 l cng cc thanh ghi c chc
nng c bit SFR m ngi
dng khng c cha d liu
khc, cn 4 bank b nh d liu
ca PIC16F877A c t chc
theo cch khc.

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Mi bank ca b nh d liu PIC16F877A bao gm c cc thanh ghi c chc nng

c bit SFR nm cc cc nh a ch thp v cc thanh ghi mc ch dng
chung GPR nm vng a ch cn li ca mi bank thanh ghi. Vng nh cc
thanh ghi mc ch dng chung ny chnh l ni ngi dng s lu d liu trong
qu trnh vit chng trnh. Tt c cc bin d liu nn c khai bo cha trong
vng a ch ny.

Trong cu trc b nh d liu ca PIC16F877A, cc thanh ghi SFR no m thng

xuyn c s dng (nh thanh ghi STATUS) s c t tt c cc bank
thun tin trong vic truy xut. S d nh vy l v, truy xut mt thanh ghi no
trong b nh ca 16F877A ta cn phi khai bo ng bank cha thanh ghi ,
vic t cc thanh ghi s dng thng xuyn gip ta thun tin hn rt nhiu trong
qu trnh truy xut, lm gim lnh chng trnh.

Da trn s 4 bank b nh d liu PIC16F877A ta rt ra cc nhn xt nh sau :

-Bank0 gm cc nh c a ch t 00h n 77h, trong cc thanh ghi dng chung
cha d liu ca ngi dng a ch t 20h n 7Fh. Cc thanh ghi PORTA,
PORTB, PORTC, PORTD, PORTE u cha bank0, do truy xut d liu cc
thanh ghi ny ta phi chuyn n bank0. Ngoi ra mt vi cc thanh ghi thng dng
khc ( s gii thiu sau) cng cha bank0
- Bank1 gm cc nh c a ch t 80h n FFh. Cc thanh ghi dng chung c a
ch t A0h n Efh. Cc thanh ghi TRISA, TRISB, TRISC, TRISD, TRISE cng c
cha bank1
- Tng t ta c th suy ra cc nhn xt cho bank2 v bank3 da trn s trn.
Cng quan st trn s , ta nhn thy thanh ghi STATUS, FSR c mt trn c 4
bank. Mt iu quan trng cn nhc li trong vic truy xut d liu ca PIC16F877A
l : phi khai bo ng bank cha thanh ghi .Nu thanh ghi no m 4 bank u cha
th khng cn phi chuyn bank.

SVTH: Trn Tng Bng

V Vn Chnh

Hnh 6: Cu trc b nh d liu ca PIC 16F877A

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2.2a/ Thanh ghi chc nng c bit SFR: (Special Function Register)
-

y l cc thanh ghi c s dng bi CPU hoc c dng thit lp v iu

khin cc khi chc nng c tch hp bn trong vi iu khin. C th phn
thanh ghi SFR lm hai lai: thanh ghi SFR lin quan n cc chc nng bn trong
(CPU) v thanh ghi SRF dng thit lp v iu khin cc khi chc nng bn
ngoi (v d nh ADC, PWM, ).

Mt s thanh ghi cc nng c bit:

Thanh ghi STATUS (03h, 83h, 103h, 183h):thanh ghi cha kt qu thc hin
php ton ca khi ALU, trng thi reset v cc bit chn bank cn truy xut
trong b nh d liu.
Thanh ghi OPTION_REG (81h, 181h): thanh ghi ny cho php c v ghi,
cho php iu khin chc nng pull-up ca cc chn trong PORTB, xc lp cc
tham s v xung tc ng, cnh tc ng ca ngt ngoi vi v b m Timer0.

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Thanh ghi INTCON (0Bh, 8Bh,10Bh, 18Bh): thanh ghi cho php c v
,cha cc bt iu khin v cc c hiu khi timer0 b trn, ngt ngoi vi
RB0/INT v ngt interrput-on-change ti cc chn ca PORTB.
Thanh ghi PIE1 (8Ch): cha cc bit iu khin chi tit cc ngt ca cc khi
chc nang ngoai vi.
Thanh ghi PIR1 (0Ch) cha c ngt ca cc khi chc nng ngoi vi, cc ngt
ny c cho php bi cc bit iu khin cha trong thanh ghi PIE1.
Thanh ghi PIE2 (8Dh): cha cc bit iu khin cc ngt ca cc khi chc
nng CCP2, SSP bus, ngt ca b so snh v ngt ghi vo b nh EEPROM.
Thanh ghi PCON (8Eh): cha cc c hiu cho bit trng thi cc ch reset
ca vi iu khin.
2.2b/ Thanh ghi muc ch chung GPR: (General Purpose Register)
Cc thanh ghi ny c th c truy xut trc tip hoc gin tip thng qua thanh ghi
FSG (File Select Register).y l cc thanh ghi d liu thng thng, ngi s dng
c th ty theo mc ch chng trnh m c th dng cc thanh ghi ny cha cc
bin s, hng s, kt qu hoc cc tham s phc v cho chng trnh.

Hnh 7: Cu trc thanh ghi chc nng chung ca PIC

16F877A
2.3. Stack
-

Stack khng nm trong b nh chng trnh hay b nh d liu m l mt vng

nh c bit khng cho php c hay ghi. Khi lnh CALL c thc hin hay khi mt
ngt xy ra lm chng trnh b r nhnh, gi tr ca b m chng trnh PC t ng
c vi iu khin ct vo trong stack. Khi mt trong cc lnh RETURN, RETLW hat
RETFIE c thc thi, gi tr PC s t ng c ly ra t trong stack, vi iu khin
s thc hin tip chng trnh theo ng qui trnh nh trc.
-

B nh Stack trong vi iu khin PIC h 16F87xA c kh nng cha c 8 a

SVTH: Trn Tng Bng

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ch v hot ng theo c ch xoay vng. Nghia l gi tr ct vo b nh Stack ln th 9

s ghi ln gi tr ct vo Stack ln u tin v gi tr ct vo b nh Stack ln th
10 s ghi ln gi tri6 ct vo Stack ln th 2.
-

Cn ch l khng c c hiu no cho bit trng thi stack, do ta khng bit

c khi no stack trn. Bn cnh tp lnh ca vi iu khin dng PIC cng khng
c lnh POP hay PUSH, cc thao tc vi b nh stack s hon ton c iu khin
bi CPU.
3. Khi qut v chc nng ca cc port trong vi iu khin PIC16F877A
a/ PORTA:
-PORTA (RPA) bao gm 6 I/O pin.y l cc chn hai chiu (bidirectional
pin), ngha l c th xut v nhp c.Chc nng I/O ny c iu khin bi thanh
ghi TRISA (a ch 85h). Mun xc lp chc nng ca mt chn trong PORTA l
input, ta set bit iu khin tng ng vi chn trong thanh ghi TRISA v ngc
li, mun xc lp chc nng ca mt chn trong PORTA l output, ta clear bit iu
khin tng ng vi chn trong thanh ghi TRISA. Thao tc ny hon ton tng t
i vi cc PORT v cc thanh ghi iu khin tng ng TRIS (i vi PORTA l
TRISA, i vi PORTB l TRISB, i vi PORTC l TRISC, i vi PORTD l
TRISD vi vi PORTE l TRISE).
-Ngoi ra, PORTA cn c cc chc nng quan trng sau :
Ng vo Analog ca b ADC : thc hin chc nng chuyn t Analog
sang Digital
Ng vo in th so snh
Ng vo xung Clock ca Timer0 trong kin trc phn cng : thc hin
cc nhim v m xung thng qua Timer0
Ng vo ca b giao tip MSSP (Master Synchronous Serial Port)
- Cc thanh ghi SFR lin quan n PORTA bao gm:
PORTA (a ch 05h)

: cha gi tr cc pin trong PORTA.

TRISA (a ch 85h)

: iu khin xut nhp.

CMCON (a ch 9Ch)

: thanh ghi iu khin b so snh.

CVRCON (a ch 9Dh)

: thanh ghi iu khin b so snh in p.

ADCON1 (a ch 9Fh)

: thanh ghi iu khin b ADC.

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b/PORTB:
-

PORTB (RPB) gm 8 pin I/O. Thanh ghi iu khin xut nhp tng ng l
TRISB.

Bn cnh mt s chn ca PORTB cn c s dng trong qu trnh np

chng trnh cho vi iu khin vi cc ch np khc nhau. PORTB cn lin
quan n ngt ngoi vi v b Timer0. PORTB cn c tch hp chc nng in
tr ko ln c iu khin bi chng trnh.

Cc thanh ghi SFR lin quan n PORTB bao gm:

PORTB (a ch 06h, 106h)

: cha gi tr cc pin trong PORTB

TRISB (a ch 86h, 186h)

: iu khin xut nhp

OPTION_REG (a ch 81h, 181h): iu khin ngt ngoi vi v b Timer0.

c/PORTC:
PORTC c 8 chn v cng thc hin c 2 chc nng input v output di s iu
khin ca thanh ghi TRISC tng t nh hai thanh ghi trn.
Ngoi ra PORTC cn c cc chc nng quan trng sau :
- Ng vo xung clock cho Timer1 trong kin trc phn cng
- B PWM thc hin chc nng iu xung lp trnh c tn s, duty cycle: s
dng trong iu khin tc v v tr ca ng c v.v.
- Tch hp cc b giao tip ni tip I2C, SPI, SSP, USART
d/PORTD:
-PORTD c 8 chn. Thanh ghi TRISD iu khin 2 chc nng input v output ca
PORTD tng t nh trn.PORTD cng l cng xut d liu ca chun giao tip song
song PSP (Parallel Slave Port).
-Cc thanh ghi lin quan n PORTD bao gm:
Thanh ghi PORTD: cha gi tr cc pin trong PORTD.
Thanh ghi TRISD: iu khin xut nhp.
Thanh ghi TRISE: iu khin xut nhp PORTE v chun giao tip PSP.
e/PORTE:
-PORTE c 3 chn.Thanh ghi iu khin xut nhp tng ng l TRISE.Cc chn
ca PORTE c ng vo analog Bn cnh PORTE cn l cc chn iu khin ca
chun giao tip PSP.
SVTH: Trn Tng Bng
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-Cc thanh ghi lin quan n PORTE bao gm:

PORTE: cha gi tr cc chn trong PORTE.
TRISE: iu khin xut nhp v xc lp cc thng s cho chun giao tip PSP.
ADCON1: thanh ghi iu khin khi ADC.

4. Cc vn v Timer
PIC16F877A c tt c 3 timer : timer0 (8 bit), timer1 (16 bit) v timer2 (8 bit).
4.1. Timer0
a/ L b nh thi hoc b m c nhng u im sau:
8 bit cho b nh thi hoc b m.
C kh nng c v vit.
C th dng ng bn trong hoc bn ngoi.
C th chn cnh xung ca xung ng h.
C th chn h s chia u vo (lp trnh bng phn mn).
Ngt trn.
b/ Hot ng ca Timer 0:
Timer 0 c th hot ng nh mt b nh thi hoc mt b m.Vic chn b
nh thi hoc b m c th c xc lp bng vic xo hoc t bt TOCS
ca thanh ghi OPTION_REG<5>.
Nu dng h s chia xung u vo th xo bit PSA ca thanh ghi
OPTION_REG<3>.
Trong ch b nh thi c la chn bi vic xo bit T0CS (OPTION
REG<5>), n s c tng gi tr sau mt chu k lnh nu khng chn h s
chia xung u vo.V gi tr ca n c vit ti thanh ghi TMR0.
Khi dng xung clock bn ngoi cho b nh thi Timer0 v khng dng h s
chia clock u vo Timer0 th phi p ng cc iu kin cn thit c th
hot ng l phi bo m xung clock bn ngoi c th ng b vi xung
clock bn trong (TOSC).
H s chia dng cho Timer 0 hoc b WDT. Cc h s nay khng c kh nng
c v kh nng vit. chn h s chia xung cho b tin nh ca Timer0

SVTH: Trn Tng Bng

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hoc cho b WDT ta tin hnh xo hoc t bt PSA ca thanh ghi

OPTION_REG<3>
Nhng bt PS2, PS1, PS0 ca thanh ghi OPTION_REG<2:0> dng xc lp
cc h s chia.
B tin nh c gi tr 1:2 chng hn, c ngha l : bnh thng khng s dng
b tin nh ca Timer0 (ng ngha vi tin nh t l 1:1) th c khi c tc
ng ca 1 xung clock th timer0 s tng thm mt n v. Nu s dng b tin
nh 1:4 th phi mt 4 xung clock th timer0 mi tng thm mt n v. V
hnh chung, gi tr ca timer0 (8 bit) lc ny khng cn l 255 na m l
255*4=1020.

c/ Ngt ca b Timer0
Ngt ca b Timer 0 c pht sinh ra khi thanh ghi TMR0 b trn tc t
FFh quay v 00h.Khi bt T0IF ca thanh ghi INTCON<2> s c t.
Bt ny phi c xa bng phn mm nu cho php ngt bit T0IE ca
thanh ghi INTCON<5> c set.Timer0 b dng hot ch SLEEP
ngt Timer 0 khng nh thc b x l ch SLEEP.
d/ Cc thanh ghi lin quan n Timer0 bao gm:
-

Thanh ghi OPTION_REG : iu khin hot ng ca Timer0

Hnh 8: Cu trc thanh ghi OPTION_REG REGISTER

iu khin hot ng ca Timer0

bit 5 TOCS la chn ngun clock

1=Clock ngoi t chn T0CKI
0=Clock trong Focs/4
bit 4 T0SE bit la chon sn xung clock
1=Timer 0 tng khi chn T0CKI t cao xung thp(sn xung)
SVTH: Trn Tng Bng
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0=Timer 0 tng khi chn T0CKI t thp ln cao(sn xung)

bit 3 PSA bit gn b chia xung u vo
1=gn b chia Prescaler cho WDT
0=gn b chia Prescaler cho Timer 0
bit 2:0 PS2:PS1 la chn h s chia h s xung theo bng sau:
PS2:PS0
000
001
010
011
100
101
110
111

Timer0
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256

WDT
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128

Thanh ghi TMR0 i ch 01h v 101h : cha gi tr ca b nh thi Timer0

Thanh ghi INTCON : cho php ngt hot ng

Thanh ghi cha cc bit iu khin v cc bt c hiu khi timer0 b trn, ngt ngoi
vi RB0/INT v ngt interrupt_on_change ti cc chn ca PORTB.

Hnh 9: Cu trc thanh ghi INTCON cho php ngt

Timer0 hot ng

Bit 7 GIE Global Interrupt Enable bit

GIE = 1 cho php tt c cc ngt.
GIE = 0 khng cho php tt c cc ngt.
Bit 6 PEIE Pheripheral Interrupt Enable bit
PEIE = 1 cho php tt c cc ngt ngoi vi.
PEIE = 0 khng cho php tt c cc ngt ngoi vi.
Bit 5 TMR0IE Timer0 Overflow Interrupt Enable bit
TMR0IE = 1 cho php ngt Timer0.
TMR0IE = 0 khng cho php ngt Timer0.
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Bit 4 RBIE RB0/INT External Interrupt Enable bit

RBIE = 1 cho php tt c cc ngt ngoi vi RB0/INT
RBIE = 0 khng cho php tt c cc ngt ngoi vi RB0/INT
Bit 3 RBIE RB Port change Interrupt Enable bit
RBIE = 1 cho php ngt RB Port change
RBIE = 0 khng cho php ngt RB Port change
Bit 2 TMR0IF Timer0 Interrupt Flag bit
TMR0IF = 1 thanh ghi TMR0 b trn (phi xa c hiu bng chng
trnh).
TMR0IF = 0 thanh ghi TMR0 cha b trn.
Bit 1 INTF BR0/INT External Interrupt Flag bit
INTF = 1 ngt RB0/INT xy ra (phi xa c hiu bng chng trnh).
INTF = 0 ngat RB0/INT cha xay ra.
Bit 0 RBIF RB Port Change Interrupt Flag bit
RBIF = 1 t nht c mt chn RB7:RB4 c s thay i trng thi. Bt ny
phi c xa bng chng trnh sau khi kim tra li cc gi tr chn
ti PORTB.
RBIF = 0 khng c s thay i trng thi cc chn RB7:RB4.
4.2.TIMER1
a/Timer1 l b nh thi 16 bit, gi tr ca Timer1 s c lu trong hai thanh ghi 8
bit TMR1H:TMR1L. C ngt ca Timer1 l bit TMR1IF, bit iu khin ca Timer1 l
TRM1IE.Cp thanh ghi ca TMR1 s tng t 0000h ln n FFFFh ri sau trn v
0000h. Nu ngt c cho php, n s xy ra khi khi gi tr ca TMR1 trn t FFFFh
ri v 0000h, lc ny TMR1IF s bt ln.
b/ Timer1 c 3 ch hot ng :
Ch hot ng nh thi ng b: Ch c la chn bi bit TMR1CS.
Trong ch ny xung cp cho Timer1 l Fosc/4, bit T1SYNC khng c tc
dng.
Ch m ng b: trong ch ny, gi tr ca timer1 s tng khi c xung
cnh ln vo chn T1OSI/RC1. Xung clock ngoi s c ng b vi xung
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clock ni, hot ng ng b c thc hin ngay sau b tin nh t l xung

(prescaler).
Ch m bt ng b:ch ny xy ra khi bit T1SYNC c set. B nh
thi s tip tc m trong sut qu trnh ng (Sleep) ca vi iu khin v c kh
nng to mt ngt khi b nh thi trn v lm cho vi iu khin thot khi
trng thi ng.
c/ Cc thanh ghi lin quan n Timer1 bao gm:
INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ngt hot ng (2 bit GIE
v PEIE).
PIR1 (a ch 0Ch): cha c ngt Timer1 (TMR1IF).
PIE1 (a ch 8Ch): cho php ngt Timer1 (TMR1IE).
Ba thanh ghi va nu trn s c trnh by phn chng trnh ngt ca PIC
TMR1L (a ch 0Eh): cha gi tr 8 bt thp ca b m Timer1.
TMR1H (a ch 0Eh): cha gi tr 8 bt cao ca b m Timer1.
Hai thanh ghi TMR1L v TMR1H l 2 thanh ghi cha d liu 16 bit (ln lt
cha 4 bit thp v 4 bit cao) ca b m Timer1
T1CON (a ch 10h): xc lp cc thng s chi Timer

Hnh 10: Cu trc thanh ghi T1CON iu khin hot ng

ca Timer1

- bit 7,6 khng s dng

- bit 5,4 T1CKPS1: T1CKPS0 la chn h s chia xung vo.
T1CKPS1
T1CKPS0
00
1:1
01
1:2
10
1:4
11
1:8
- bit 3 T1OSCEN bit iu khin b dao ng Timer1
1= B dao ng hot ng
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0= B dao ng khng hot ng

- bit 2 bit iu khin xung clock ngoi ng b
khi TMR1CS=1
- bit2=0 c ng clock ngoai
=1 khng ng b clock ngoi
khi TMR1CS=0 bit ny khng c tc dng
- bit 1 TMR1CS bit la chn ngun xung clock vo
TMR1CS=1 clock t chn RC0/T1OSO/T1CKI (sn ln)
TMR1CS=0 clock trong Fosc/4
- bit 0 bit bt tt Timer
1= Timer 1 enable
0=Timer 1 Disable
4.3.Timer 2
a/ Timer2: l b nh thi 8 bit bao gm mt b tin nh (prescaler), mt b hu nh
Postscaler v mt thanh ghi chu k vit tt l PR2. Vic kt hp timer2 vi 2 b nh t
l cho php n hot ng nh mt b inh thi 16 bit. Module timer2 cung cp thi
gian hot ng cho ch iu bin xung PWM nu module CCP c chn.

SVTH: Trn Tng Bng

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Hnh 11: S khi Timer2

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b/ Hot ng ca b Timer2
-

Timer2 c dng ch yu phn iu ch xung ca b CCP, thanh ghi

TMR2 c kh nng c v vit, n c th xa bng vic reset li thit b.
u vo ca xung c th chn cc t s sau; 1:1; 1:4 hoc 1:16 vic la
chn cc t s ny c th iu khin bng cc bit sau T2CKPS1 v bit
T2CKPS0.

B Timer2 c 1 thanh ghi 8 bt PR2 . Timer 2 tng t gi tr 00h cho n

khp vi PR2 v tip theo n s reset li gi tr 00h v lnh k tip thc
hin.Thanh ghi PR2 l mt thanh ghi c kh nng c v kh nng vit.

c/ Thanh ghi T2CON: iu khin hot ng ca Timer2

Hnh 12: Cu trc thanh ghi T2CON iu khin hot ng

ca Timer2

- bit 7 khng s dng

- bit 6-3 TOUTPS3: TOUTPS0 bit la chn h s u ra Timer 2
0000=1:1
0001=1:2
0010=1:3

1111=1:16
- bit 2 TMR2ON bit bt tt hot ng Timer 2
1= enable
0= disable
- bit 1- 0 T2CKPS1:T2CKPS0 chn h chia u vo
00 = 1:1
01 = 1:4
1x=1:16
5. NGT (INTERRUPT):
- PIC16F877A c n 14 ngun to ra hot ng ngt c iu khin bi thanh ghi
INTCON (bit GIE). Bn cnh mi ngt cn c mt bit iu khin v c ngt
SVTH: Trn Tng Bng
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ring. Cc c ngt vn c set bnh thng khi tha mn iu kin ngt xy ra bt

chp trng thi ca bit GIE, tuy nhin hot ng ngt vn ph thuc vo bit GIE v
cc bit iu khin khc. Bit iu khin ngt RB0/INT v TMR0 nm trong thanh ghi
INTCON, thanh ghi ny cn cha bit cho php cc ngt ngoi vi PEIE. Bit iu
khin cc ngt nm trong thanh ghi PIE1 v PIE2.C ngt ca cc ngt nm trong
thanh ghi PIR1 v PIR2.
- Trong mt thi im ch c mt chng tr nh ngt c thc thi, chng trnh ngt
c kt thc bng lnh RETFIE. Khi chng trnh ngt c thc thi, bit GIE t
ng c xa, a ch lnh tip theo ca chng trnh chnh c ct vo trong b
nh Stack v b m chng trnh s ch n a ch 0004h. Lnh RETFIE c
dng thot khi chng trnh ngt v quay tr v chng trnh chnh, ng thi
bit GIE cng s c set cho php cc ngt hot ng tr li. Cc c hiu c
dng kim tra ngt no ang xy ra v phi c xa bng chng trnh trc khi
cho php ngt tip tc hot ng tr li ta c th pht hin c thi im tip
theo m ngt xy ra.
- i vi cc ngt ngoi vi nh ngt t chn INT hay ngt t s thay i trng thi cc
pin ca PORTB (PORTB Interrupt on change), vic xc nh ngt no xy ra cn 3
hoc 4 chu k lnh ty thuc vo thi im xy ra ngt.
-

Cn ch l trong qu trnh thc thi ngt, ch c gi tr ca b m chng

trnh c ct vo trong Stack, trong khi mt s thanh ghi quan trng s khng c
ct v c th b thay i gi tr trong qu trnh thc thi chng trnh ngt.iu ny nn
c x l bng chng trnh trnh hin tng trn xy ra.
-

Cc ngun ngt ca Pic 16F877A:

1) RTCC hoc TIMER0: ngt trn Timer0.
2) RB: ngt khi c s thay i trng thi 1 trong cc chn t RB4 n RB7 ca
PORTB.
3) EXT: (External Interrupt) ngt ngoi khi c s thay i trng thi chn
RB0 ca PORTB.
4) AD: ngt khi b chuyn i tnh hiu tng t sang tnh hiu s chuyn i
hon tt 1 tnh hiu.
5) TBE: ngt khi b m ca cng RS232 rng.

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6) RDA: ngt khi cng RS232 nhn tnh hiu.

7) TIMER1: ngt khi timer1 b trn.
8) TIMER2: ngt khi timer2 b trn.
9) CCP1; CCP2: ngt khi b capture hoc b Compare (b so snh in p)
hot ng; knh 1 hoc 2.
10) SSP: ngt khi SPI hoc I2C hot ng.
11) PSP: ngt khi truyn nhn d liu song song.
12) BUSCOL: ngt khi xung t ng truyn.
13) EEPROM: ngt khi ghi xong d liu.
14) COMP: ngt sau khi thc hin so snh tnh hiu.

SVTH: Trn Tng Bng

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Hnh 13: S hot ng ngt ca PIC 16F877A

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Vi ti iu khin tc ng c DC chng em s dng hai loi ngun ngt l

ngt ngoi khi c s thay i trng thi chn RB0 ca PORTB v ngt trn Timer1,
v th chng em s trnh by c th hn v nguyn l hot ng v cc ci t ca hai
loi ngt ny trong phn di y:
a/ Ngt ngoi (External Interrupt):
-

Ngt ny da trn s thay i trng thi ca pin RB0/INT. Cnh tc ng gy ra

ngt c th l cnh ln hay cnh xung v c iu khin bi bit INTEDG (thanh ghi
OPTION_ REG <6>). Khi c cnh tc ng thch hp xut hin ti pin RB0/INT, c
ngt INTF c set bt chp trng thi cc bit iu khin GIE v PEIE. Ngt ny c
kh nng nh thc vi iu khin t ch sleep nu bit cho php ngt c set trc
khi lnh SLEEP c thc thi.
-

Thanh ghi OPTION_REG: a ch 81h, 181h

Thanh ghi ny cho php iu khin chc nng pull-up ca cc pin trong PORTB, xc
lp cc tham s v xung tc ng, cnh tc ng ca ngt ngoi vi RB0 (External
Interrupt) v b m Timer0.

Hnh 14: Cu trc thanh ghi OPTION_REG cho php ngt

ngoi v ngt timer0
Bit 7 PORTB pull-up enable bit
= 1 khng cho php chc nng pull-up ca PORTB
= 0 cho php chc nng pull-up ca PORTB
Bit 6 INTEDG Interrupt Edge Select bit
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INTEDG = 1 ngt xy ra khi cnh dng chn RB0/INT xut hin.

INTEDG = 0 ngt xy ra khi cnh m chn BR0/INT xut hin.
Bit 5 TOCS Timer0 Clock Source select bit
TOSC = 1 clock ly t chn RA4/TOCK1.
TOSC = 0 dng xung clock bn trong (xung clock ny bng vi xung clock
dng thc thi lnh).
Bit 4 TOSE Timer0 Source Edge Select bit
TOSE = 1 tc ng cnh ln.
TOSE = 0 tc ng cnh xung.
Bit 3 PSA Prescaler Assignment Select bit
PSA = 1 b chia tn s (prescaler) c dng cho WDT
PSA = 0 b chia tn s c dng cho Timer0
Bit 2:0 PS2:PS0 Prescaler Rate Select bit
Cc bit ny cho php thit lp t s chia tn s ca Prescaler.

b/ Ngt trn Timer1:

-

Cp thanh ghi TMR1H v TMR1L cha gi tr m ca Timer1, chng tng t

ga tr 0000h n ga tr FFFFh n gi tr ny tip tc tng th timer1 trn v
quay li gi tr 0000h.V ngt xut hin khi trn qu gi tr FFFFh khi ny c
ngt TMR1IF s c t.Ngt c th hot ng hoc khng hot ng nh
vic t hoc xa bt TMR1IE.

Thanh ghi iu khin Timer1 T1CON:

SVTH: Trn Tng Bng

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bit 7,6 khng s dng

bit 5,4 T1CKPS1:T1CKPS0 la chn h s chia xung vo

T1CKPS1:T1CKPS0
00
01
10
11

t l chia u vo
1:1
1:2
1:4
1:8

bit 3 T1OSCEN bit iu khin b dao ng Timer1

1= B dao ng hot ng
0= B dao ng khng hot ng
bit 2 bit iu khin xung clock ngoi ng b
khi TMR1CS=1
bit2=0 c ng clock ngoi
=1 khng ng b clock ngoi
khi TMR1CS=0 bit ny khng c tc dng
bit 1 TMR1CS bit la chn ngun xung clock vo
TMR1CS=1 clock t chn RC0/T1OSO/T1CKI (sn ln)
TMR1CS=0 clock trong Fosc/4
bit 0 bit bt tt Timer
1= Timer 1 enable
0=Timer 1 Disable

6. Phng php iu ch xung PWM:

iu khin tc ng c DC ngi ta c th dng nhiu phng php khc nhau
trong c mt phng php ht sc quan trng v thng dng l phng php iu
ch rng xung kch (PWM).

6.1. iu ch PWM l g?
Phng php iu ch rng xung PWM (Pulse Width Modulation) l phng php
iu chnh in p ra ti hay ni cch khc l phng php iu ch da trn s thay
i rng ca chui xung kch iu khin linh kin ng ngt (SCR hay
Transistor) dn n s thay i in p ra ti.

th dng xung iu ch PWM

SVTH: Trn Tng Bng
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Hnh 15: th dng xung iu ch PWM

6.2. Nguyn l ca PWM:

y l phng php c thc hin theo nguyn tc dng ngt ngun c ti mt cch
c chu k theo lut iu chnh thi gian ng ngt.Phn t thc hin nhim v ng ct
l cc van bn dn.S nguyn l iu khin ti dng PWM.

NGUON

PWM xung vung

Q1

Q1(B)

NPN

TAI

Hnh 16: S nguyn l dng PWM iu khin in p ti (tri)

S xung van iu khin v u ra (phi)
SVTH: Trn Tng Bng
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Trong khong thi gian 0 - to ta cho van Q1 m ton b in p ngun Ud c a ra ti.

Cn trong khong thi gian t t0 n T cho van Q1 kha, ct ngun cung cp cho ti.V vy
vi thi gian t0 thay i t 0 cho n T ta s cung cp ton b , mt phn hay kha hon ton
in p cung cp cho ti.

Cng thc tnh gi tr trung bnh ca in p ra ti l:

Ud = Umax . (t0/T) hay Ud = Umax.D
Trong Ud: l in p trung bnh ra ti.
Umax: l in p ngun.
t0: l thi gian xung sn dng (van kha m)
.

T: thi gian c thi gian xung sn dng v sn m.

D = t0/T: h s iu chnh hay PWM c tnh bng %

V d: in p ngun l 12V.
Nu h s iu chnh l 20% => Ud = 12.20% = 2.4 V
Nu h s iu chnh l 50% => Ud = 12.50% = 6 V
V vy, trong ti: iu khin tc ng c DC chng em s dng phng php
iu ch rng xung PWM thay i in p DC cp cho ng c t thay i
tc ca ng c DC. i vi PIC16F877A s dng phng php ny ta c th
s dng b iu ch rng xung (PWM) tch hp sn bn trong PIC vi 2 ng ra
xung ti hai chn CCP1 (17) v CCP2 (16).Ti cc chn ny khi hot ng s xut
chui xung vung vi rng iu chnh c d dng.Xung ra ny dng to tn
hiu ng ngt Trasistor trong mch ng lc, vi rng xc nh s to ra mt in
p trung bnh xc nh.
6.3. Cch thit lp ch PWM cho PIC16F877A
-

Khi hot ng ch PWM (Pulse Width Modulation _ khi iu ch

rng xung), tnh hiu sau khi iu ch s c a ra cc pin ca khi CCP
(cn n nh cc pin ny l output ). s dng chc nng iu ch ny trc
tin ta cn tin hnh cc bc ci t sau:

Thit lp thi gian ca 1 chu k ca xung iu ch cho PWM (period) bng cch
a gi tr thch hp vo thanh ghi PR2.

SVTH: Trn Tng Bng

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Thit lp rng xung cn iu ch (duty cycle) bng cch a gi tr vo

thanh ghi CCPRxL v cc bit CCP1CON<5:4>.
iu khin cc pin ca CCP l output bng cch clear cc bit tng ng trong
thanh ghi TRISC.
Thit lp gi tr b chia tn s prescaler ca Timer2 v cho php Timer2 hot
ng bng cch a gi tr thch hp vo thanh ghi T2CON.
Cho php CCP hot ng ch PWM.
-

Trong gi tr 1 chu k (period) ca xung iu ch c tnh bng cng thc:

PWM period = [(PR2) +1]*4*TOSC*(gia tr bo chia tan

so cua TMR2).
o rong cua xung ieu che (duty cycle) c tnh theo cong
thc:

PWM duty cycle = (CCPRxL:CCPxCON<5:4>)*TOSC*(gia tr bo chia tan

so TMR2)

SVTH: Trn Tng Bng

V Vn Chnh

Hnh 17: S khi CCP (PWMmode)(tri)

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Khi gia tr thanh ghi PR2 bang vi gia tr thanh ghi TMR2 th
qua trnh sau xay ra:
Thanh ghi TMR2 t ng c xa.
Pin ca khi CCP c set.
Gi tr thanh ghi CCPR1L (cha gi tr n nh rng xung iu ch duty
cycle) c a vo thanh ghi CCPRxH.

II. Mch cu H ( H-Bridge Circuit ).

1/ Cng dng v nguyn l hot ng:
Mch cu H l mt mch in gip o chiu dng in qua mt i tng .i
tng l ng c DC m chng ta cn iu khin .Mc ch iu khin l cho php
dng in qua i tng theo chiu A n B hoc B n A .T gip i chiu quay
ca ng c.
Hin nay, ngoi loi mch cu H c thit k t cc linh kin ri nh: BJT
cng sut, Mosfet, Cn c cc loi mch cu H c tch hp thnh cc IC nh:
L293D v L298D. Do i tng iu khin trong ti ny l ng c DC c in p
12V v cng sut nh nn chng em dng mch cu H o chiu ng c l IC L298.

SVTH: Trn Tng Bng

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Hnh 18: Mch cu H

Kho st hot ng ca mch cu H

Hnh19: Nguyn l hot ng ca mch cu H

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2/ Mch cu H L298D:
L298D l mt chip toch1 hp 2 mch trong gi 15 chn. L298D c in p danh
ngha cao (ln hn 50V) v dng in danh ngha ln hn 2A nn rt thch hp cho
cc ng dng cng sut nh nh cc ng c DC loi va v nh.

Hnh 20: S chn ca IC L298D (phi)

IC L298D (tri)

Hnh 21: S nguyn l ca IC L298D

SVTH: Trn Tng Bng
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C 2 mch cu H trn mi chip L298D nn c th iu khin 2 i tng ring vi 1

chip ny. Mi mch cu H bao gm 1 ng ngun Vs (tht ra l ng chung cho 2
mch cu), mt chn current sensing (cm bin dng) phn cui ca mch cu H,
chn ny khng c ni t m b trng cho ngi dng ni 1 in tr nh gi l
sensing resistor.Bng cacch1 o in p ri trn in tr ny chng ta c th tnh c
dng qua in tr, cng l dng qua ng c, mc ch ca vic ny l xc nh
dng qu ti. Nu vic o lng l khng cn thit th ta c th ni chn ny vi GND.
ng c s c ni vi 2 chn OUT1, OUT2 hoc OUT3, OUT4.Chn EN (ENA v
ENB) cho php mch cu hot ng, khi chn ny c ko ln mc cao.
L298D khng ch c dng o chiu ng c m cn iu khin vn tc ng c
bng PWM.Trong thc t, cng sut thc ma L298D c th ti nh hn gi tr danh
ngha ca n (U =50V, I =2A). tng dng ti ca chp ln gp i, chng ta c th
ni hai mch cu H song song vi nhau (cc chn c chc nng nh nhau ca 2 mch
cu c ni chung).

III/LCD
1/Chc nng v hnh dng LCD.
Ngy nay, thit b hin th LCD (Liquid Crystal Display) c s dng trong rt nhiu
cc ng dng ca vi iu khin.LCD c rt nhiu u im so vi cc dng hin th
khc: n c kh nng hin th k t a dng, trc quan (ch, s v k t ha), d
dng a vo mch ng dng theo nhiu giao thc giao tip khc nhau, tn rt t ti
nguyn h thng v gi thnh r

Hnh 22: LCD v s chn

SVTH: Trn Tng Bng

V Vn Chnh

34

GVHD: Nguyn Thanh Tho

n 2

2/ Chc nng cc chn

Bng Chc nng cc chn ca LCD
Chn
s

Tn

Chc nng

VSS

Chn ni t cho LCD, khi thit k mch ta ni chn ny vi GND

ca mch iu khin

VDD

Chn cp ngun cho LCD, khi thit k mch ta ni chn ny vi

VCC=5V ca mch iu khin

Vee

Chn ny dng iu chnh tng phn ca LCD.

Chn chn thanh ghi (Register select). Ni chn RS vi logic 0
(GND) hoc logic 1 (VCC) chn thanh ghi.
+ Logic 0: Bus DB0-DB7 s ni vi thanh ghi lnh IR ca LCD (
4
RS
ch ghi - write) hoc ni vi b m a ch ca LCD ( ch
c - read) .
+ Logic 1: Bus DB0-DB7 s ni vi thanh ghi d liu DR bn
trong LCD
Chn chn ch c/ghi (Read/Write). Ni chn R/W vi logic 0
5
R/W LCD hot ng ch ghi, hoc ni vi logic 1 LCD ch
c.
Chn cho php (Enable). Sau khi cc tn hiu c t ln bus DB0DB7, cc lnh ch c chp nhn khi c 1 xung cho php ca chn E.
+ ch ghi: D liu bus s c LCD chuyn vo (chp nhn)
thanh ghi bn trong khi pht hin mt xung (high-to-low transition)
6
E
ca tn hiu chn E.
+ ch c: D liu s c LCD xut ra DB0-DB7 khi pht
hin cnh ln (low-to-high transition) chn E v c LCD gi
bus n khi no chn E xung mc thp.
Tm ng ca bus d liu dng trao i thng tin vi MPU. C
2 ch s dng 8 ng bus ny :
DB0- + Ch 8 bit: D liu c truyn trn c 8 ng, vi bit MSB l
7-14
DB7 bit DB7.
+ Ch 4 bit: D liu c truyn trn 4 ng t DB4 ti DB7,
bit MSB l DB7.
* Ghi ch: ch c, ngha l MPU s c thng tin t LCD thng qua cc chn
DBx.
Cn khi ch ghi,ngha l MPU xut thng tin iu khin cho LCD thng qua
cc chn DBx.

SVTH: Trn Tng Bng

V Vn Chnh

35

GVHD: Nguyn Thanh Tho

n 2

3/c tnh in ca cc chn giao tip:

LCD s b hng nghim trng, hoc hot ng sai lch nu bn vi phm khong
c tnh in sau y:
Chn cp ngun (Vcc-GND)

Min:-0.3V , Max+7V

Cc chn ng vo (DBx, E, )

Min:-0.3V , Max:

Nhit hot ng

(Vcc+0.3V)
Min:-30C , Max:+75C

Nhit bo qun

Min:-55C , Max:+125C

4/ Tp lnh ca LCD:
Cc lnh ca LCD c th chia thnh 3 nhm nh sau:
Cc lnh v kiu hin th.
VD: Kiu hin th (1 hng / 2 hng), chiu di d liu (8 bit / 4 bit),
Ch nh a ch RAM ni.
Nhm lnh truyn d liu trong RAM ni.
Vi mi lnh, LCD cn mt khong thi gian hon tt, thi gian ny c th kh lu
i vi tc ca MPU, nn ta cn kim tra c BF hoc i (delay) cho LCD thc thi
xong lnh hin hnh mi c th ra lnh tip theo.
Tn lnh
Clear

Texe

Hot ng

(max)

M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1

Display

DB0
DBx = 0

Lnh Clear Display (x a hin th) s ghi mt khong trngblank (m hin k t 20H) vo tt c nh trong DDRAM, sau
tr b m a AC=0, tr li kiu hin th gc nu n b thay
i. Ngha l : Tt hin th, con tr di v g c tri (hng u
Return
home

tin), ch tng AC.

M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1
DB0

SVTH: Trn Tng Bng

V Vn Chnh

1.52
ms
36

GVHD: Nguyn Thanh Tho

n 2

DBx = 0

Lnh Return home tr b m a ch AC v 0, tr li kiu hin

th gc nu n b thay i. Ni dung ca DDRAM khng thay
i.
M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1

Entry
mode set

37 us

DB0
DBx = 0

1 [I/D] [S]

I/D : Tng (I/D=1) hoc gim (I/D=0) b m a ch hin th

AC 1 n v mi khi c hnh ng ghi hoc c vng
DDRAM. V tr con tr cng di chuyn theo s tng gim ny.
S : Khi S=1 ton b ni dung hin th b dch sang phi
(I/D=0) hoc sang tri (I/D=1) mi khi c hnh ng ghi vng
DDRAM. Khi S=0: khng dch ni dung hin th.
Ni dung hin th khng dch khi c DDRAM hoc c/ghi
Display
on/off

vng CGRAM.
M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1

37 us

DB0

control

DBx = 0

1 [D]

[C] [B]

D: Hin th mn hnh khi D=1 v ngc li. Khi tt hin th,

ni dung DDRAM khng thay i.
C: Hin th con tr khi C=1 v ngc li. V tr v hnh dng
con tr, xem hnh 8
B: Nhp nhy k t ti v tr con tr khi B=1 v ngc li. Xem
thm hnh 8 v kiu nhp nhy. Chu k nhp nhy khong
409,6ms khi mch dao ng ni LCD l
Cursor or
display

250kHz
M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1

37 us

DB0

shift

DBx = 0

1 [S/C] [R/L] *

Lnh Cursor or display shift dch chuyn con tr hay d liu

SVTH: Trn Tng Bng
V Vn Chnh

37

GVHD: Nguyn Thanh Tho

n 2

hin th sang tri m khng cn hnh ng ghi/c d liu. Khi

hin th kiu 2 dng, con tr s nhy xung dng di khi dch
qua v tr th 40 ca hng u tin. D liu hng u v hng 2
dch cng mt lc.
Function
set

M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1

37 us

DB0
DBx = 0

1 [DL] [N]

[F]

DL: Khi DL=1, LCD giao tip vi MPU bng giao thc 8 bit
(t bit DB7 n DB0).
Ngc li, giao thc giao tip l 4 bit (t bit DB7 n bit
DB0). Khi chn giao thc 4 bit, d liu c truyn/nhn
2 ln lin tip. vi 4 bit cao gi/nhn trc,
4 bit thp gi/nhn sau.
N: Thit lp s hng hin th. Khi N=0: hin th 1 hng, N=1:
hin th 2 hng.
F: Thit lp kiu k t. Khi F=0: kiu k t 5x8 im nh, F=1:
kiu k t 5x10 im
* Ch :
Ch thc hin thay i Function set u chng trnh.
V sau khi c thc
thi 1 ln, lnh thay i Function set khng c LCD
chp nhn na ngoi tr thit lp chuyn i giao thc
giao tip.
Khng th hin th kiu k t 5x10 im nh kiu hin
Set
CGRAM

th 2 hng
M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1

37 us

DB0

address
SVTH: Trn Tng Bng
V Vn Chnh

DBx = 0

1 [ACG][ACG][ACG][ACG]
38

GVHD: Nguyn Thanh Tho

n 2

[ACG][ACG]
Lnh ny ghi vo AC a ch ca CGRAM. K hiu [ACG] ch
1 bit ca chui d liu
6 bit. Ngay sau lnh ny l lnh c/ghi d liu t CGRAM ti
a ch c ch nh
Set
DDRAM

M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1

37 us

DB0

address

DBx = 1 [AD] [AD] [AD] [AD] [AD] [AD]

[AD]
Lnh ny ghi vo AC a ch ca DDRAM, dng khi cn thit
lp ta hin th mong mun. Ngay sau lnh ny l lnh
c/ghi d liu t DDRAM ti a ch c ch nh.
Khi ch hin th 1 hng: a ch c th t 00H n 4FH.
Khi ch hin th 2 hng, a ch t 00h n 27H cho hng
th nht, v t 40h n 67h cho hng th 2.
Xem chi tit hnh 4.

Read BF
and

M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1

0 us

DB0

address

DBx = [BF] [AC] [AC] [AC] [AC] [AC] [AC]

[AC]

(RS=0, R/W=1)

Nh cp trc y, khi c BF bt, LCD ang lm vic

v lnh tip theo (nu
c) s b b qua nu c BF cha v mc thp. Cho nn, khi lp
trnh iu khin, bn phi kim tra c BF trc khi ghi d liu
vo LCD.
Khi c c BF, gi tr ca AC cng c xut ra cc bit
[AC]. N l a ch ca
CG hay DDRAM l ty thuc vo lnh trc c
Write

M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1

SVTH: Trn Tng Bng

V Vn Chnh

37 us
39

GVHD: Nguyn Thanh Tho

n 2

data to

DB0

CG or
DDRAM

DBx =

[Write data]

(RS=1, R/W=0)
Khi thit lp RS=1, R/W=0, d liu cn ghi c a vo
cc chn DBx t mch
ngoi s c LCD chuyn vo trong LCD ti a ch c
xc nh t lnh ghi a ch trc (lnh ghi a ch cng xc
nh lun vng RAM cn ghi)
Sau khi ghi, b m a ch AC t ng tng/gim 1 ty
theo thit lp Entry mode.
Lu l thi gian cp nht AC khng tnh vo thi gian thc
thi lnh.

Read

M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 37 us

data from

DB0

CG

DBx =

[Read data]

(RS=1, R/W=1)

IV. i tng iu khin: ng c DC

-

y l ng c s dng trong ti:

SVTH: Trn Tng Bng

V Vn Chnh

Hnh 23: ng c DC c gn encoder s dng

trong n

40

GVHD: Nguyn Thanh Tho

n 2

Bn trong ng c c gn mt encoder ng trc vi n dng xc nh tc v

v tr ca ng c.

Cc thng s ca ng c nh sau:
+ in p DC cp cho ng c: 12VDC
+ Tc ti a 2000 vng/pht
+ S xung ca encoder 60xung/vng
+ in cm L=102mH

ng c c tt c 5 dy ra:
+ 2 dy cung cp ngun 12 V cho ng c
+ 2 dy ngun 5V cung cp ngun cho encoder
+ 1 dy tn hiu a xung encoder ra ngoi

Phng php iu khin: Thay i tc ng c bng cch thay i p cp vo

cho ng c.

Nguyn l hot ng ca cm bin encoder: c nhiu loi encoder khc nhau. Mi

loi li c mt nguyn l hot ng khc nhau, trong khun kh bo co n, em
xin trnh by phn nguyn l loi encoder trong ti m em s dng: incremental
encoder.

M hnh th 1

41

SVTH: Trn Tng Bng

V Vn Chnh

Hnh 24: Encoder

GVHD: Nguyn Thanh Tho

n 2

Incremental encoder v c bn l mt a trn quay quanh mt trc c c l

nh hnh trn.

a khc
vch

B thu
pht quang

Hnh 25: Cu to Encoder

2 bn mt ca ci a trn , s c mt b thu pht quang. Trong qu trnh

encoder quay quanh trc, nu gp l rng th nh sng chiu qua c, nu gp mnh
chn th tia sng khng chiu qu c. Do tn hiu nhn c t sensor quang l
mt chui xung.Mi encoder c ch to s bit sn s xung trn mt vng. Do ta
c th dng vi iu khin m s xung trong mt n v thi gian v tnh ra tc
ng c.
Encoder m em s dng trong n ca mnh, hon ton ging vi m hnh trn.
Tuy nhin, m hnh trn c nhc im ln l: ta khng th xc nh c ng c
quay tri hay quay phi, v c quay theo chiu no i na th ch c mt dng xung a
ra. Ngoi ra im bt u ca ng c, ta cng khng th no bit c.
Ci tin m hnh 1 bng m hnh 2 nh sau:
SVTH: Trn Tng Bng
V Vn Chnh

42

GVHD: Nguyn Thanh Tho

n 2

M hnh th 2

Hnh 26: a khc 2 cng vch lch pha nhau 900

Trong m hnh ny, ngi ta c tt c l 2 vng l. Vng ngoi cng ging

nh m hnh 1, vng gia lch pha so vi vng ngoi l 90 . Khi , dng xung ra
t 2 vng trn nh sau :

Hnh 27: th xung ca encoder c 2 vng vch lnh pha nhau 900

Hai xung a ra t 2 vng lch nhau 90 , nu vng ngoi nhanh pha hn vng
trong th chc chn ng c quay t tri sang phi v ngc li.

SVTH: Trn Tng Bng

V Vn Chnh

43

GVHD: Nguyn Thanh Tho

n 2

L vng trong cng dng pht hin im bt u ca ng c.C th vit

chng trnh cho vi iu khin nhn bit: nu c mt xung pht ra t vng trong cng
ny, tc l ng c quay ng mt vng.
Vi nhng c tnh trn, encoder dng rt ph bin trong vic xc nh v tr gc
ca ng c..
Mt loi encoder th 2 cng ph bin hin nay, l: absolute encoder.
M hnh a quang ca loi ny nh sau:

Hnh 28: a khc nhiu vng vch khc nhau

CHNG 3:
THIT K MCH PHN CNG
CODE CHNG TRNH V LU GII THUT
I/ THIT K MCH PHN CNG:
SVTH: Trn Tng Bng
V Vn Chnh

44

GVHD: Nguyn Thanh Tho

n 2

Mch c thit k gm c cc khi nh sau: khi ngun, khi bn phm, khi hin
th, khi mch cng sut, khi iu khin.
1/Khi ngun:
Mch ly ngun xoay chiu qua adapter AC/DC 220VAC/12VDC, v c n p nh
IC 7805.S nguyn l mch:
U2

+12V

+5V

7805
3
2
1

VI

VO

R26

1k

GND

JACK

C4

C5

100uF

100nF

J1

C6

C7

D8

100uF

100nF

LED

J2
2
1
TERMINAL2

Hnh 29: Khi mch n p

Chc nng ca cc phn t trong mch:

-

IC 7805: chc nng n p in p 5V

Hnh 30: IC7805

C4 t ha (c phn cc) n p ng vo, in dung ca t ny cng ln th in

p vo IC 7805 cng phng.

J2 t lc nhiu tng s cao ng vo v

C5 v C7 t giy (khng phn cc) l1 hai

ng R2
ra.

R1
10k

PHIM 1

10k

R3

R4

10k

10k

SIL-100-03

C6 t ha c tc dng dp dao ng t kch khi s dng IC n p dng 78xx.

PHIM 2

PHIM 3

BUTTON

BUTTON

PHIM 10

BUTTON

4
PHIM bn
5
PHIM 6
2/ PHIM
Khi
mch
phm:
1

2
3

2
FW
PHIM 11

Mch bn phm gm 16 phm, c b tr thnh 4 hng v 4 ct nh hnh v:

BUTTON

BUTTON

PHIM 7
1

PHIM 8
2

BUTTON

PHIM 12
2

BUTTON

PHIM 15
2

RV

PHIM 9
2

BUTTON

PHIM 16
1

BUTTON

STOP

PHIM 14
2

SAVE

SVTH: Trn Tng Bng

V Vn Chnh

PHIM 13
2

CLEAR

J1
2

2
ENTER

B4 1
B5 2
B6 3
B7 4
A0 5
A1 6
A2 7
A3 8

45
SIL-100-08

Hnh 31: Khi mch bn

GVHD: Nguyn Thanh Tho

n 2

Bn hng c ni vi Port B (t B4 n B7) ca vi x l, bn ct c ni vi Port A

(t A0 n A3) ca vi x l v c ni vi ngun VCC qua in tr (ngha l cc
chn ca Port A t A0 n A3 s lun nhn mc 1 khi khng c phm nhn), vic lm
ny nhm phc v cho gii thut qut phm s c trnh by phn sau.
Trong s 16 phm c 10 phm nhp d liu s t 0 n 9, 6 phm iu khin (FW,
RV, STOP, ENTER, CLEAR, SAVE).
LCD1

Ngun VCC
trong s mch bn phm l 5V, c cp t khi mch n p trn.V
RT1602C
mch bn phm truyn nhn d liu trc tip vi PIC nn cn in p n nh.
3/Khi mch hin th:
A
K

D0
D1
D2
D3
D4
D5
D6
D7

RS
RW
E

VSS
VDD
VEE

RV1
Mch
hin th bao gm mn hnh LCD giao tip vi PIC qua Port D vi giao thc 4

15
16

7
8
9
10
11
12
13
14

4
5
6

1
2
3

48%

bit, ngoi ra cn c bin tr iu chnh sng ca LCD.

Ngoi ra, cn c khi hin th gm 8 led n c hn dng bng in tr 220, c
10k

D4
D5
D6
D7

D0
D1
D2

tc dng text chng trnh,cc khi khc v cng c dng bo hiu o chiu
trong ch c
J5 ci t thi gian.

1
2
3
4
5
6
7
8

SIL-100-08

Hnh 32: Khi mch LCD

v LED n

R2
330

R3
330

R4
330

R5
330

R6
330

R7
330

R8
330

R9
330

D2

D3

D4

D5

D6
LED

D7
LED

D9
LED

D10
LED

LED Trn
LEDTng
LED Bng
LED
SVTH:

V Vn Chnh

46

GVHD: Nguyn Thanh Tho

n 2

4/Khi mch cng sut:

Mch cng sut s dng IC cu H L298, vi 2 knh A v B,mi knh vi in p
nh mc 50V v dng nh mc cho ti l 2A.Khi u song song 2 knh ta c
dng cp cho ti ln n 4A (gp i).in p iu khin 5V.
+12V

CLK

SIL-100-05

1
15
R1

R2

0.5

0.5

+12V
IN1 VCC
IN2
IN3
IN4
ENA
ENB
SENSA
SENSB

VS
OUT1
OUT2
OUT3
OUT4

M1

M1

Motor

14

GND
8

1
2
Motor

2
1
M2

J2
M2
M1

J4

3
13

D2 1N4007

U1

M2
+88.8

D3 1N4007

5
4
3
2
1

5
7
10
12
6
11

D4 1N4007

9
J3

D1 1N4007

+12V

J1
CLK

1
2
3
Encoder

L298

Hnh 33: Khi mch cng sut s sng IC L298

Cu Diode dng chng dng in ngc, do ti ng c c tnh cht cm

khng.Ngun cp cho ng c 12V
S dung IC cu H ny, khng nhng dng o chiu ng c m cn iu khin
tc ng c bng phng php bm xung (PWM).
5/ Khi mch iu khin:
SVTH: Trn Tng Bng
V Vn Chnh

47

GVHD: Nguyn Thanh Tho

n 2

Vi iu khin trung tm l PIC 16F877A.Vi chc nng ca cc port nh sau:

Port A (t A0 n A3) c set l ng vo nhn tnh hiu t 4 ct ca bm
phm.
Port B (t B3 n B7) l ng ra xut tnh hiu ra 4 hng ca khi bn phm,
chn RB0 nhn tnh hiu xung t Encoder (v ngt ngoi xy ra khi tnh hiu
thay i trn chn RB0);
Ta s dung 2 chn RC1(CCP2) v RC2 (CCP1) ca Port C xut tnh hiu
PWM iu khin ng c.
Port D (tr chn RD3) gi tnh hiu n khi hin th LCD.Ba chn t RD0 n
RD2 ni vi 3 chn iu khin ca LCD.Bn chn t RD4 n RD7 ni vi 4
bt cao ca cc chn nhn d liu ca LCD.

J4

C1
8
7
6
5
4
3
2
1

R1
R2
R3
R4
C1
C2
C3
C4

X1
20M

C2
U1
13
14

SIL-100-08
J10
C1
C2
C3
C4
SIL-100-06

D1

R1

1N4148

10k

SW1
BUTTON

J9

33

6
5
4
3
2
1

2
3
4
5
6
7

3
2
1

8
9
10

SIL-100-03

R10

33

OSC1/CLKIN
OSC2/CLKOUT

RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD

RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RC0/T1OSO/T1CKI
RE0/AN5/RD
RC1/T1OSI/CCP2
RE1/AN6/WR
RC2/CCP1
RE2/AN7/CS
RC3/SCK/SCL
RC4/SDI/SDA
MCLR/Vpp/THV
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7

C3
10uF

10k

J8
33
34
35
36
37
38
39
40

1
2
3
4
5
6
7
8

15
16
17
18
23
24
25
26

1
2
3
4
5
6
7
8

19
20
21
22
27
28
29
30

1
2
3
4
5
6
7
8

PIC16F877A

R1
R2
R3
R4
J3

SIL-100-08
5
4
3
2
1

J7

J6

SIL-100-05
SIL-100-08
E
RS
RW
D4
D5
D6
D7
SIL-100-08

Thch anh dng trong mch

gi
20MHz,
vi 2khin
t C1,C2
l t giy vi in dung
Hnh
34:tr
Khi
mch iu
PIC 16F877A
33uF. Pic reset khi chn s 1 MCLR ni mass.T C3 c tc dng chng nhiu chn
s 1.
II/ Gii thiu v chng trnh vit code v bin dch:
Trong n ny nhm chng em s dng chng trnh vit code CCS, chng trnh
cho php lp trnh ngn ng C cho vi iu khin PIC ca Microchip.

SVTH: Trn Tng Bng

V Vn Chnh

48

GVHD: Nguyn Thanh Tho

n 2

Chng trnh ny c cc cu lnh n gin, d hiu, h tr bin dch vi chc nng

hin th li v cnh bo chng trnh khng kh dng. Ngoi ra n cn c th bin
dch t code C ra file.hex v c code Assemble.

Cu trc 1 chng trnh trong CCS:

-

u tin l cc ch th tin x l : ( # . . . ) c nhim v bo cho CCS cn s

dng nhng g trong chng trnh C nh dng vi x l g , c dng giao tip PC
khng , ADC khng , DELAY khng , c s dng ngt hay khng

Cc khai bo bin.

Cc hm con.

Cc hm phc v ngt theo sau bi 1 ch th tin x l cho bit dng ngt no.

Chng trnh chnh.

V d v cu trc 1 chng trnh trong CCS:

//------khai bo tin x l------#include<16F877.h>
#device PIC16F877 *=16 ADC=10
#use delay (clock=20000000)

// khai bo them nu c
//------khai bo bin------Int a,b;
Int16 x,y;
..
//----------cc chng trnh con------SVTH: Trn Tng Bng
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Void xu_ly_ADC ()
{
}
Int cai_dat_PWM ()
{.
Return(bin);}
//------hm ngt------#INT_TIMER1
Void xu_ly_ngt()
{
}
//-------chng trnh chnh-------Void main()
{
..}
III/ Lu gii thut:
Lu gii thut gm: lu chng trnh chnh, chng trnh qut phm, chng
trnh ngt ca timer1.
Chng trnh chnh l 1 vng lp v hn c nhng chng trnh con nh:
qut phm, check phm, chn ch , tnh PWM, nhp d liu tc , nhp
d liu thi gian, save vo epprom.
Chng trnh qut phm th hin gii thut nhn phm nhn v nhn bit gi
tr ca phm (phm nhn l phm no) .
Chng trnh ngt timer 1 c tc dng cp nht gi tr tc , tnh ton gi
tr PWM, v xut tnh hiu n khi hin th.

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CODE CHNG TRNH

#include"E:/TL/DOAN2\cauH\MACH\15\main.h"
#include <LCD.C>
//#include <math.h> //dung cac ham toan hoc
#use delay(clock=20000000)
#use fast_io(a)
#use fast_io(b)
#use fast_io(c)
#use fast_io(d)
//==================khai bao ham con=============
int quetphim();
int checkphim(b);
void pwm();
void ghi_tocdo();
void ghi_thoigian();
void clear();
void read_rom();
//==================khai bao bien================
int8 i,t,a,b,c,d,sttphim,duty,ct,l,m;
int16 s_xung,s_vong,setpoint,error,luu,tg,tg1,dem;
//================ bien luu eeprom==============
int8 e0,e1,e2,e3,j,k;
int16 e;
//================chuong trinh quet phim==========
//quet phim so
int quetphim()
{
output_b(0xe0);// B4=0
a=0;
b=1;
checkphim(b);
if (a!=0)
{delay_ms(200);
return (sttphim);}
output_b(0xd0);// B5=0
a=0;
b=2;
checkphim(b);
if (a!=0)
{delay_ms(200);
return (sttphim);}
output_b(0xb0);// B6=0
a=0;
b=3;
checkphim(b);
if (a!=0)
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{delay_ms(200);
return (sttphim);}
output_b(0x70);// B6=0
a=0;
b=4;
checkphim(b);
if (a!=0)
{delay_ms(200);
return (sttphim);}}
//============chuong trinh check phim=============
int checkphim(b)
{
switch (b)
{
case 1:
if(!input(pin_a0))
{sttphim=1;
a=1;}
else if(!input(pin_a1))
{sttphim=2;
a=1;}
else if(!input(pin_a2))
{sttphim=3;
a=1;}
else if(!input(pin_a3))
{ sttphim=10;//thuan
a=1;}
else {}
break;
case 2:
if(!input(pin_a0))
{sttphim=4;
a=1;}
else if(!input(pin_a1))
{sttphim=5;
a=1;}
else if(!input(pin_a2))
{sttphim=6;
a=1;}
else if(!input(pin_a3))
{sttphim=11;//nghich
a=1;}
else {}
break;
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case 3:
if(!input(pin_a0))
{sttphim=7;
a=1;}
else if(!input(pin_a1))
{sttphim=8;
a=1;}
else if(!input(pin_a2))
{sttphim=9;
a=1;}
else if(!input(pin_a3))
{sttphim=12;//stop
a=1;}
else {}
break;
case 4:
if(!input(pin_a0))
{sttphim=0;//0
a=1;}
else if(!input(pin_a1))
{sttphim=15;//save
a=1;}
else if(!input(pin_a2))
{sttphim=14;//clear
a=1;}
else if(!input(pin_a3))
{sttphim=13;//set
a=1;}
else {}
break;}
return (sttphim);
}
// chuong trinh nhan xung tu encoder
//ngat ngoai, nhan xung tu encoder
#int_ext
void RB0_isr()
{
s_xung++;//dem so xung o chan RB0
}
//ngat timer1, tinh toan pwm va hien thi
#int_timer1
void timer1_isr()
{
set_timer1(-62500);
if (t==5){
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S_vong=s_xung*2;//xung tren phut

//ht
lcd_gotoxy(1,1);
printf(lcd_putc,"
");
if(ct==1)
{
lcd_gotoxy(1,1);
printf(lcd_putc,"TD_dat=%lu v/p",luu);}
else {
lcd_gotoxy(1,1);
printf(lcd_putc,"TG_dat=%lu s",tg);}
lcd_gotoxy(1,2);
printf(lcd_putc,"
");
if (d==2)
{lcd_gotoxy(1,2);
printf(lcd_putc,"TD_tt=-%luv/p",s_vong);}
if (d==1)
{lcd_gotoxy(1,2);
printf(lcd_putc,"TD_tt= %luv/p",s_vong);}
//=========================
//xuat pwm
pwm();
//========================
s_xung=0;
s_vong=0;
t=0;
set_timer1(-62500);
}
else
t++;
set_timer1(-62500);
}
//ngat timer0, dat thoi gian
#int_timer0
void time0_irs()
{
set_timer0(-235);
if (dem>=tg1)
{
output_high(pin_e0);
delay_us(100);
output_low(pin_e0);
dem=0;
if (d==1)
{d=2;}
else if (d==2)
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{d=1;}
else{}
set_timer0(-235);
}
else {
dem++;
set_timer0(-235);}
}
//chuong trinh chinh
void main()
{
i=0;
sttphim=0;
setpoint=0;tg=0;
duty=0;
c=0;
d=0;
ct=0;l=0;m=0;
e0=0;e1=0;e2=0;e3=0;e=0;k=0;
//================================================
============
//1:ngo vao;0: la ngo ra
set_tris_b(0b00001111);//4 chan RB4-RB7 xuat du lieu ra ban phim
set_tris_a(0b00001111);//4 chan RA0-RA3 nhan du lieu tu ban phim
set_tris_c(0b00000000);//2 chan RC0 va RC1 xuat PWM
set_tris_D(0b00000000);//port D la port xuat du lieu ra LCD
//================================================
============
setup_timer_1(T1_INTERNAL|T1_DIV_BY_8);
/* timer1 la bo dinh thoi su dung xung noi,bo chia 1:8 thay doi moi
1600ns
Dung timer1 de ngat moi 0.1s do vay ta dat gia tri cho timer1 la :
0.1s/1600ns=62500(D)=F424(H) =>gia tri nap la FFFF-F424=BDB*/
setup_timer_0(RTCC_INTERNAL|RTCC_DIV_256);
enable_interrupts(int_ext);//khoi dong ngat ngoai
ext_int_edge(H_TO_L); // xung tu cao xuong thap
enable_interrupts(global);// khoi dong bit ngat GIE
setup_timer_2(T2_DIV_BY_4,249,1);
/*timer2 dung dinh thoi cho bo PWM
mode: bo chia thoi gian (prescale) cua timer2 1:4
period: gia tri nap chi thanh ghi PR2
postscale : bo chi ra,chon 1:1 PWM khong dung
Thach anh 20MHz, PWM fre: 10000Hz, thay doi duty cycle(%) de
thay doi toc do*/
setup_ccp1(CCP_PWM);
setup_ccp2(CCP_PWM);
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set_pwm1_duty(0);
set_pwm2_duty(0);
//================================================
===========
lcd_init()
lcd_send_byte(0,0x01);
lcd_gotoxy(1,1);
printf(lcd_putc,"CHUONG TRINH DK ");
lcd_gotoxy(1,2);
printf(lcd_putc," TD DONG CO DC ");
delay_ms(1000);
lcd_gotoxy(1,1);
printf(lcd_putc,"
");
lcd_gotoxy(1,2);
printf(lcd_putc,"
");
read_rom();
lcd_gotoxy(1,1);
printf(lcd_putc,"CHON CHE DO :_ ");
while (true)
{
while (c==0)
{
quetphim();
if (a!=0)
{
if (sttphim==1)
{ ct=1;
c=1;
lcd_gotoxy(1,1);
printf(lcd_putc,"CHON CHE DO :_%u",ct);}
if (sttphim==2)
{ ct=2;
c=1;
lcd_gotoxy(1,1);
printf(lcd_putc,"CHON CHE DO :_%u",ct);}
}
}
if (ct==1)
{lcd_gotoxy(1,1);
printf(lcd_putc,"TD_dat=_ v/p");
lcd_gotoxy(1,2);
printf(lcd_putc,"TD_luu=%lu v/p",e);}
else {
lcd_gotoxy(1,1);
printf(lcd_putc,"TD_dat=_ v/p");
lcd_gotoxy(1,2);
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printf(lcd_putc,"TG_dat=_
While (c==1)
{
quetphim();

s");}

if (a!=0)
{
if (sttphim>=0 && sttphim<=9)//ban phim tu 0--->9
{
if (m==0)
{ghi_tocdo();}
if((ct==2)&&(m==1))
{ghi_thoigian();}
}
if (sttphim==14)
{clear();}
if ((sttphim==13)&&(i==0)&&(e==0))
{
lcd_gotoxy(1,1);
printf(lcd_putc,"
");
lcd_gotoxy(1,1);
printf(lcd_putc,"Phai nhap TD_dat");
delay_ms(1000);
lcd_gotoxy(1,1);
printf(lcd_putc,"
");
lcd_gotoxy(1,1);
printf(lcd_putc,"TD_dat=_");
}
if ((sttphim==15)&&(i!=0)) //luu vao eeprom
{
write_eeprom(0,e0);
delay_ms(100);
write_eeprom(1,e1);
delay_ms(100);
write_eeprom(2,e2);
delay_ms(100);
write_eeprom(3,e3);
delay_ms(100);
write_eeprom(4,i);
delay_ms(100);
lcd_gotoxy(1,2);
printf(lcd_putc,"
");
lcd_gotoxy(1,2);
printf(lcd_putc," LUU THANH CONG ");
}
if ((sttphim==13)&&((i!=0)||(e!=0)))
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{
if (ct==1)
{
c=2;
if (e!=0 && i==0)
luu=e;}
if ((ct==2)&&(l>=2))
{
c=2;}
m=1;
}}}
while (c==2)
{
quetphim();
if(a!=0)
{
if(sttphim==10)
{
lcd_gotoxy(1,2);
printf(lcd_putc,"
");
lcd_gotoxy(1,2);
printf(lcd_putc," QUAY THUAN ");
if (ct==2)
{enable_interrupts(int_timer0);
set_timer1(-235);}
enable_interrupts(int_timer1);
enable_interrupts(global);
set_timer1(-62500);
set_pwm1_duty(duty);
d=1;
}
if (sttphim==11)
{
lcd_gotoxy(1,2);
printf(lcd_putc,"
");
lcd_gotoxy(1,2);
printf(lcd_putc," QUAY NGHICH ");
if (ct==2)
{enable_interrupts(int_timer0);
set_timer1(-235);}
enable_interrupts(int_timer1);
enable_interrupts(global);
set_timer1(-62500);
set_pwm2_duty(duty);
d=2;
}
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if (sttphim==12)//stop
{
disable_interrupts(int_timer0);
set_timer0(0);
disable_interrupts(int_timer1);
set_pwm1_duty(0);
set_pwm2_duty(0);
lcd_gotoxy(1,2);
printf(lcd_putc,"
");
lcd_gotoxy(1,2);
printf(lcd_putc," STOP ");
duty=0;
d=0;
}
if (sttphim==14)
{
clear();
c=0;
lcd_gotoxy(1,1);
printf(lcd_putc,"
");
lcd_gotoxy(1,2);
printf(lcd_putc,"
");
lcd_gotoxy(1,1);
printf(lcd_putc,"CHON CHE DO :_ ");
}}}}}
void pwm()
{
if ((luu>s_vong)&& duty<250)
{error=luu-s_vong;
if (error>1000)
duty=duty+50;
else if (error>100)
duty=duty+20;
else if (error>30)
{duty=duty+5;}
else if (error>20)
duty=duty+1.5;
else if (error>10)
duty=duty+(0.05*error);
else {duty=duty+(0.025*error);}
}
if (luu<(s_vong-2)&& (duty>0))
{error=s_vong-luu;
if (error>=10)
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duty=duty-(0.05*error);
else (duty=duty-(0.02*error));
}
if(luu==s_vong)
duty=duty;
if((duty>=250)&&(luu>s_vong))
{ lcd_gotoxy(1,1);
printf(lcd_putc,"
");
lcd_gotoxy(1,1);
printf(lcd_putc," TD_tt=MAX ");}
if (d==0)
{set_pwm1_duty(0);
set_pwm2_duty(0);}
else if (d==1)
{set_pwm1_duty(duty);
set_pwm2_duty(0);}
else
{set_pwm1_duty(0);
set_pwm2_duty(duty);}
}
//========chuong trinh con nhap toc do=======
void ghi_tocdo()
{
if(i>=0&&i<=3)
{
// giai thuat luu eeprom
if (i==0)
e0=sttphim;
else if (i==1)
e1=sttphim;
else if (i==2)
e2=sttphim;
else {e3=sttphim;}
//===============================
setpoint*=10;
setpoint+=sttphim;
i++;
lcd_gotoxy(1,1);
printf(lcd_putc,"
");
lcd_gotoxy(1,1);
printf(lcd_putc,"TD_dat=%lu v/p",setpoint);
luu=setpoint;
}
else {
lcd_gotoxy(1,1);
printf(lcd_putc,"
");
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lcd_gotoxy(1,1);
printf(lcd_putc,"0<TD_dat<=9999");
delay_ms(1000);
lcd_gotoxy(1,1);
printf(lcd_putc,"
");
lcd_gotoxy(1,1);
printf(lcd_putc,"TD_dat=%lu s",setpoint);
}}
//=========chuong trnh con nhap thoi gian=========
void ghi_thoigian()
{
if(l>=0&&l<=3)
{
tg*=10;
tg+=sttphim;
l++;
lcd_gotoxy(1,2);
printf(lcd_putc,"
");
lcd_gotoxy(1,2);
printf(lcd_putc,"TG_dat=%lu s",tg);
tg1=tg/0.12;
}
else {
lcd_gotoxy(1,2);
printf(lcd_putc,"
");
lcd_gotoxy(1,2);
printf(lcd_putc," 0<TG_dat<=999 ");
delay_ms(1000);
lcd_gotoxy(1,2);
printf(lcd_putc,"
");
lcd_gotoxy(1,2);
printf(lcd_putc,"TG_dat=%lu s",tg);
}}
//============chuong trinh con clear=========
void clear()
{
setpoint=0;
tg=0;
i=0;l=0;m=0;
e0=0;e1=0;e2=0;e3=0;
lcd_gotoxy(1,1);
printf(lcd_putc,"
");
lcd_gotoxy(1,1);
printf(lcd_putc,"TD_dat=_");
lcd_gotoxy(1,2);
printf(lcd_putc,"
");
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lcd_gotoxy(1,2);
printf(lcd_putc,"TG_dat=_");
}
//=======chuong trinh con luu toc do vao epprom======
void read_rom()
{
k=read_eeprom(4);
for (j=0;j<k;j++)
{
e=e*10;
e=e+read_eeprom(j);
}}

//==========THE END========

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