BSIM3v3.2.2 MOSFET Model: Users' Manual

BSIM3v3.2.
2 MOSFET Model
Users Manual
Weidong Liu, Xiaodong Jin, James Chen, Min-Chie Jeng, Zhihong Liu, Yuhua Cheng, Kai Chen, Mansun Chan, Kelvin Hui, Jianhui Huang, Robert Tu, Ping K. Ko and Chenming Hu
Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA 94720
Copyright 1999 The Regents of the University of California All Rights Reserved
Developers: The BSIM3v3.2.2 MOSFET model is developed by Prof. Chenming Hu, UC Berkeley Dr. Weidong Liu, UC Berkeley Mr. Xiaodong Jin, UC Berkeley
Developers of Previous Versions: Dr. Mansun Chan, USTHK Dr. Kai Chen, IBM Dr. Yuhua Cheng, Rockwell Dr. Jianhui Huang, Intel Corp. Dr. Kelvin Hui, Lattice Semiconductor Dr. James Chen, UC Berkeley Dr. Min-Chie Jeng, Cadence Design Systems Dr. Zhi-Hong Liu, BTA Technology Inc. Dr. Robert Tu, AMD Prof. Ping K. Ko, UST, Hong Kong Prof. Chenming Hu, UC Berkeley
Web Sites to Visit: BSIM web site: http://www-device.eecs.berkeley.edu/~bsim3 Compact Model Council web site: http://www.eia.org/eig/CMC
Technical Support: Dr. Weidong Liu: liuwd@bsim.eecs.berkeley.edu
Acknowledgment:
The development of BSIM3v3.2.2 benefited from the input of many BSIM3 users, especially the Compact Model Council (CMC) member companies. The developers would like to thank Keith Green, Tom Vrotsos, Britt Brooks and Doug Weiser at TI, Min-Chie Jeng at WSMC, Joe Watts and Cal Bittner at IBM, Bob Daniels and Wenliang Zhang at Avant!, Bhaskar Gadepally, Kiran Gullap and Colin McAndrew at Motorola, Zhihong Liu and Chune-Sin Yeh at BTA, Paul Humphries and Seamus Power at Analog Devices, Mishel Matloubian and Sally Liu at Rockwell, Bernd Lemaitre and Peter Klein at Siemens, Ping-Chin Yeh and Dick Dowell at HP, Shiuh-Wuu Lee, Sananu Chaudhuri and Ling-Chu Chien at Intel, Judy An at AMD, Medhat Karam, Ariel Cao and Hisham Haddara at Mentor Graphics, Peter Lee at Hitachi, Toshiyuki Saito at NEC, Richard Taylor at NSC, and Boonkhim Liew at TSMC for their valuable assistance in identifying the desirable modifications and testing of the new model. Special acknowledgment goes to Dr. Keith Green, Chairman of the Technical Issue Subcommittee of CMC; Britt Brooks, chair of CMC, Dr. Joe Watts, Secratary of CMC, and Bhaskar Gadepally, former co-chair of CMC, and Dr. Min-Chie Jeng for their guidance and support. The BSIM3 project is partially supported by SRC, CMC and Rockwell International.
Table of Contents
CHAPTER 1: Introduction 1-1
1.1 General Information 1-1 1.1 Backward compatibility 1-2 1.2 Organization of This Manual 1-2
CHAPTER 2:
Physics-Based Derivation of I-V Model 2-1
2.1 Non-Uniform Doping and Small Channel Effects on Threshold Voltage 2-1 2.1.1 Vertical Non-Uniform Doping Effect 2-3 2.1.2 Lateral Non-Uniform Doping Effect 2-5 2.1.3 Short Channel Effect 2-7 2.1.4 Narrow Channel Effect 2-12 2.2 Mobility Model 2-15 2.3 Carrier Drift Velocity 2-17 2.4 Bulk Charge Effect 2-18 2.5 Strong Inversion Drain Current (Linear Regime) 2-19 2.5.1 Intrinsic Case (Rds=0) 2-19 2.5.2 Extrinsic Case (Rds>0) 2-21 2.6 Strong Inversion Current and Output Resistance (Saturation Regime) 2-22 2.6.1 Channel Length Modulation (CLM) 2-25 2.6.2 Drain-Induced Barrier Lowering (DIBL) 2-26 2.6.3 Current Expression without Substrate Current Induced Body Effect 2-27 2.6.4 Current Expression with Substrate Current Induced Body Effect 2-28 2.7 Subthreshold Drain Current 2-30 2.8 Effective Channel Length and Width 2.9 Poly Gate Depletion Effect 2-33 2-31
CHAPTER 3:
Unified I-V Model

3-6
3-1
3-1
3.1 Unified Channel Charge Density Expression 3.2 Unified Mobility Expression
BSIM3v3.2.2 Manual Copyright 1999 UC Berkeley
3.3 Unified Linear Current Expression 3-7 3.3.1 Intrinsic case (Rds=0) 3-7 3.3.2 Extrinsic Case (Rds > 0) 3-9 3.4 Unified Vdsat Expression 3-9 3.4.1 Intrinsic case (Rds=0) 3-9 3.4.2 Extrinsic Case (Rds>0) 3-10 3.5 Unified Saturation Current Expression 3-11 3.6 Single Current Expression for All Operating Regimes of Vgs and Vds 3.7 Substrate Current 3.8 A Note on Vbs 3-15 3-15 3-12
CHAPTER 4:
Capacitance Modeling
4-1
4-1
4.1 General Description of Capacitance Modeling 4.2 Geometry Definition for C-V Modeling 4-2
4.3 Methodology for Intrinsic Capacitance Modeling 4-4 4.3.1 Basic Formulation 4-4 4.3.2 Short Channel Model 4-7 4.3.3 Single Equation Formulation 4-9 4.4 Charge-Thickness Capacitance Model 4-14 4.5 Extrinsic Capacitance 4-19 4.5.1 Fringing Capacitance 4-19 4.5.2 Overlap Capacitance 4-19
CHAPTER 5:
5.2 The NQS Model 5-1 5.3 Model Formulation 5.3.1 5.3.2 5.3.3 5.3.4
Non-Quasi Static Model

5-1
5-1
5.1 Background Information
5-2 SPICE sub-circuit for NQS model 5-3 Relaxation time 5-4 Terminal charging current and charge partitioning Derivation of nodal conductances 5-7
5-5
CHAPTER 6:
6.1 Optimization strategy 6.2 Extraction Strategies
Parameter Extraction
6-1 6-2
6-1
6.3 Extraction Procedure 6-2 6.3.1 Parameter Extraction Requirements 6-2 6.3.2 Optimization 6-4 6.3.3 Extraction Routine 6-6 6.4 Notes on Parameter Extraction 6-14 6.4.1 Parameters with Special Notes 6-14 6.4.2 Explanation of Notes 6-15
CHAPTER 7:
7.1 Benchmark Test Types 7.2 Benchmark Test Results
Benchmark Test Results

7-1 7-2
7-1
CHAPTER 8:
Noise Modeling
8-1
8.1 Flicker Noise 8-1 8.1.1 Parameters 8-1 8.1.2 Formulations 8-2 8.2 Channel Thermal Noise 8-4 8.3 Noise Model Flag 8-5
CHAPTER 9:
9.1 Diode IV Model 9-1 9.1.1 9.1.2 9.2.1 9.2.2 9.2.3
MOS Diode Modeling 9-1

Modeling the S/B Diode 9-1 Modeling the D/B Diode 9-3 S/B Junction Capacitance 9-5 D/B Junction Capacitance 9-7 Temperature Dependence of Junction Capacitance 9-10
9.2 MOS Diode Capacitance Model 9-5
9.2.4
Junction Capacitance Parameters 9-11
APPENDIX A:
A.2 DC Parameters A.4 NQS Parameters A-1
Parameter List
A-1
A-1
A.1 Model Control Parameters A.3 C-V Model Parameters A-8
A-6
A.5 dW and dL Parameters A-9 A.6 Temperature Parameters A-10 A.7 Flicker Noise Model Parameters A.8 Process Parameters A-13 A-14 A-14 A.9 Geometry Range Parameters A.10 Model Parameter Notes A-12
APPENDIX B:
Equation List
B-1
B.1 I-V Model B-1 B.1.1 Threshold Voltage B-1 B.1.2 Effective (Vgs-Vth) B-2 B.1.3 Mobility B-3 B.1.4 Drain Saturation Voltage B-4 B.1.5 Effective Vds B-5 B.1.6 Drain Current Expression B-5 B.1.7 Substrate Current B-6 B.1.8 Polysilicon Depletion Effect B-7 B.1.9 Effective Channel Length and Width B-7 B.1.10 Source/Drain Resistance B-8 B.1.11 Temperature Effects B-8 B.2 Capacitance Model Equations B-9 B.2.1 Dimension Dependence B-9 B.2.2 Overlap Capacitance B-10 B.2.3 Instrinsic Charges B-12
APPENDIX C: APPENDIX D:
D.2 DC Parameters D.4 NQS Parameters D-2 D-9
References
C-1 D-1
Model Parameter Binning

D-2
D.1 Model Control Parameters
D.3 AC and Capacitance Parameters D-7 D.5 dW and dL Parameters D-9 D.6 Temperature Parameters D-11 D.7 Flicker Noise Model Parameters D.8 Process Parameters D-13 D-14 D.9 Geometry Range Parameters D-12
CHAPTER 1: Introduction
1.1 General Information

BSIM3v3 is the latest industry-standard MOSFET model for deep-submicron digital and analog circuit designs from the BSIM Group at the University of California at Berkeley. BSIM3v3.2.2 is based on its predecessor, BSIM3v3.2, with the following changes:
A bias-independent Vfb is used in the capacitance models, capMod=1 and 2 to eliminate small negative capacitance of Cgs and Cgd in the accumulationdepletion regions.
A version number checking is added; a warning message will be given if userspecified version number is different from its default value of 3.2.2. Known bugs are fixed.
1.2 Organization of This Manual

This manual describes the BSIM3v3.2.2 model in the following manner: Chapter 2 discusses the physical basis used to derive the I-V model. Chapter 3 highlights a single-equation I-V model for all operating regimes. Chapter 4 presents C-V modeling and focuses on the charge thickness model. Chapter 5 describes in detail the restrutured NQS (Non-Quasi-Static) Model. Chapter 6 discusses model parameter extraction. Chapter 7 provides some benchmark test results to demonstrate the accuracy and performance of the model.
1-1
Organization of This Manual
Chapter 8 presents the noise model. Chapter 9 describes the MOS diode I-V and C-V models. The Appendices list all model parameters, equations and references.
1-2
CHAPTER 2: Physics-Based Derivation of I-V Model
The development of BSIM3v3 is based on Poisson's equation using gradual channel approximation and coherent quasi 2D analysis, taking into account the effects of device geometry and process parameters. BSIM3v3.2.2 considers the following physical phenomena observed in MOSFET devices [1]: Short and narrow channel effects on threshold voltage. Non-uniform doping effect (in both lateral and vertical directions). Mobility reduction due to vertical field. Bulk charge effect. Velocity saturation. Drain-induced barrier lowering (DIBL). Channel length modulation (CLM). Substrate current induced body effect (SCBE). Subthreshold conduction. Source/drain parasitic resistances.
2.1 Non-Uniform Doping and Small Channel Effects on Threshold Voltage

Accurate modeling of threshold voltage (Vth) is one of the most important requirements for precise description of device electrical characteristics. In addition, it serves as a useful reference point for the evaluation of device operation regimes. By using threshold voltage, the whole device operation regime can be divided into three operational regions.
2-1
Non-Uniform Doping and Small Channel Effects on Threshold Voltage
First, if the gate voltage is greater than the threshold voltage, the inversion charge density is larger than the substrate doping concentration and MOSFET is operating in the strong inversion region and drift current is dominant. Second, if the gate voltage is smaller than Vth, the inversion charge density is smaller than the substrate doping concentration. The transistor is considered to be operating in the weak inversion (or subthreshold) region. Diffusion current is now dominant [2]. Lastly, if the gate voltage is very close to Vth, the inversion charge density is close to the doping concentration and the MOSFET is operating in the transition region. In such a case, diffusion and drift currents are both important. For MOSFETs with long channel length/width and uniform substrate doping concentration, Vth is given by [2]: (2.1.1)
Vth =VFB + s + s Vbs =VTideal+ s Vbs s
where VFB is the flat band voltage, VTideal is the threshold voltage of the long channel device at zero substrate bias, and is the body bias coefficient and is given by: (2.1.2)
2 si qN a Cox
where Na is the substrate doping concentration. The surface potential is given by: (2.1.3)
s = 2 k BT N a ln n q i
2-2
Equation (2.1.1) assumes that the channel is uniform and makes use of the one dimensional Poisson equation in the vertical direction of the channel. This model is valid only when the substrate doping concentration is constant and the channel length is long. Under these conditions, the potential is uniform along the channel. Modifications have to be made when the substrate doping concentration is not uniform and/or when the channel length is short, narrow, or both.
2.1.1 Vertical Non-Uniform Doping Effect

The substrate doping profile is not uniform in the vertical direction as shown in Figure 2-1.
Nch
Nsub
Figure 2-1. Actual substrate doping distribution and its approximation.
The substrate doping concentration is usually higher near the Si/SiO2 interface (due to Vth adjustment) than deep into the substrate. The distribution of impurity atoms inside the substrate is approximately a half
2-3
gaussian distribution, as shown in Figure 2-1. This non-uniformity will make in Eq. (2.1.2) a function of the substrate bias. If the depletion
width is less than Xt as shown in Figure 2-1, Na in Eq. (2.1.2) is equal to Nch; otherwise it is equal to Nsub. In order to take into account such non-uniform substrate doping profile, the following Vth model is proposed:
Vth = VTideal + K1 s Vbs s K 2Vbs

For a zero substrate bias, Eqs. (2.1.1) and (2.1.4) give the same result. K1 and K2 can be determined by the criteria that Vth and its derivative versus Vbs should be the same at Vbm, where Vbm is the maximum substrate bias voltage. Therefore, using equations (2.1.1) and (2.1.4), K1 and K2 [3] will be given by the following: (2.1.5)
K 1 = 2 2 K 2 s V bm
(2.1.4)
K2 =
2 s
( 1 2 )(
s Vbx s
s Vbm s + Vbm
(2.1.6)
where 1 and 2 are body bias coefficients when the substrate doping concentration are equal to Nch and Nsub, respectively: (2.1.7)
1 =
2q si N ch Cox
2-4
(2.1.8)
2 =
2 q si N sub Cox
Vbx is the body bias when the depletion width is equal to Xt. Therefore, Vbx satisfies: (2.1.9)
qN ch X t = s Vbx 2 si
If the devices are available, K1 and K2 can be determined experimentally. If the devices are not available but the user knows the doping concentration distribution, the user can input the appropriate parameters to specify doping concentration distribution (e.g. Nch, Nsub and Xt). Then, K1 and K2 can be calculated using equations (2.1.5) and (2.1.6).
2.1.2 Lateral Non-Uniform Doping Effect

For some technologies, the doping concentration near the source/drain is higher than that in the middle of the channel. This is referred to as lateral non-uniform doping and is shown in Figure 2-2. As the channel length becomes shorter, lateral non-uniform doping will cause Vth to increase in magnitude because the average doping concentration in the channel is larger. The average channel doping concentration can be calculated as follows:
2-5
(2.1.10)
Neff = 2Lx Npocket 2Lx Na Na (L 2Lx ) + Npocket = Na 1+ L L Na
Nlx Na 1+ L
Due to the lateral non-uniform doping effect, Eq. (2.1.4) becomes:
Vth = Vth 0 + K 1
s Vbs s K 2Vbs
(2.1.11)
Nlx + K1 1 + 1 s Leff
Eq. (2.1.11) can be derived by setting Vbs = 0, and using K1 (Neff)0.5. The fourth term in Eq. (2.1.11) is used to model the body bias dependence of the lateral non-uniform doping effect. This effect gets stronger at a lower body bias. Examination of Eq. (2.1.11) shows that the threshold voltage will increase as channel length decreases [3].
Npocket
Npocket
N(x)
Na Lx Lx
X
Figure 2-2. Lateral doping profile is non-uniform.
2-6
2.1.3 Short Channel Effect

The threshold voltage of a long channel device is independent of the channel length and the drain voltage. Its dependence on the body bias is given by Eq. (2.1.4). However, as the channel length becomes shorter, the threshold voltage shows a greater dependence on the channel length and the drain voltage. The dependence of the threshold voltage on the body bias becomes weaker as channel length becomes shorter, because the body bias has less control of the depletion region. The short-channel effect is included in the Vth model as: (2.1.12)
Vth = Vth 0 + K 1 s Vbs s K 2Vbs Nlx + K1 1 + 1 s Vth Leff
where Vth is the threshold voltage reduction due to the short channel effect. Many models have been developed to calculate Vth. They used either numerical solutions [4], a two-dimensional charge sharing approach [5,6], or a simplified Poisson's equation in the depletion region [7-9]. A simple, accurate, and physical model was developed by Z. H. Liu et al. [10]. This model was derived by solving the quasi 2D Poisson equation along the channel. This quasi-2D model concluded that: (2.1.13)
Vth = th (L)(2(Vbi s ) + Vds )

where Vbi is the built-in voltage of the PN junction between the source and the substrate and is given by
2-7
(2.1.14) Vbi = KBT N N ln( ch 2 d ) q ni
where Nd in is the source/drain doping concentration with a typical value of around

1 10
20
cm-3. The expression th(L) is a short channel effect
coefficient, which has a strong dependence on the channel length and is given by: (2.1.15)
th ( L ) = [exp( L 2 lt ) + 2 exp( L lt )]
lt is referred to as the characteristic length and is given by (2.1.16)

lt =
si Tox Xdep ox
Xdep is the depletion width in the substrate and is given by (2.1.17)

X dep = 2 si ( s Vbs ) qN ch
Xdep is larger near the drain than in the middle of the channel due to the drain voltage. Xdep / represents the average depletion width along the channel. Based on the above discussion, the influences of drain/source charge sharing and DIBL effects onVth are described by (2.1.15). In order to make the model fit different technologies, several parameters such as Dvt0, Dvt2,
2-8
Dsub, Eta0 and Etab are introduced, and the following modes are used to account for charge sharing and DIBL effects separately. (2.1.18)
th ( L ) = Dvt 0 [exp( Dvt 1 L / 2lt ) + 2 exp( Dvt 1 L / lt )]

(2.1.19) Vth (L) = th (L)(Vbi s ) (2.1.20)
lt =
si Tox Xdep ox
(1 + Dvt 2 Vbs )
(2.1.21)
dibl ( L ) = [exp( Dsub L / 2lt 0 ) + 2 exp( Dsub L / lt 0 )]

(2.1.22)
Vth(Vds) = dibl( L)(Eta0 + EtabVbs)Vds

where lt0 is calculated by Eq. (2.1.20) at zero body-bias. Dvt1 is basically equal to 1/()1/2 in Eq. (2.1.16). Dvt2 is introduced to take care of the dependence of the doping concentration on substrate bias since the doping concentration is not uniform in the vertical direction of the channel. Xdep is calculated using the doping concentration in the channel (Nch). Dvt0, Dvt1,Dvt2, Eta0, Etab and Dsub, which are determined experimentally, can improve accuracy greatly. Even though Eqs. (2.1.18), (2.1.21) and (2.1.15) have different coefficients, they all still have the same functional forms. Thus the device physics represented by Eqs. (2.1.18), (2.1.21) and (2.1.15) are still the same.
2-9
As channel length L decreases, Vth will increase, and in turn Vth will decrease. If a MOSFET has a LDD structure, Nd in Eq. (2.1.14) is the doping concentration in the lightly doped region. Vbi in a LDD-MOSFET will be smaller as compared to conventional MOSFETs; therefore the threshold voltage reduction due to the short channel effect will be smaller in LDD-MOSFETs. As the body bias becomes more negative, the depletion width will increase as shown in Eq. (2.1.17). Hence Vth will increase due to the increase in lt. The term:
VTideal + K1 s Vbs K 2Vbs

will also increase as Vbs becomes more negative (for NMOS). Therefore, the changes in
VTideal + K1 s Vbs K 2Vbs

and in Vth will compensate for each other and make Vth less sensitive to Vbs. This compensation is more significant as the channel length is shortened. Hence, the Vth of short channel MOSFETs is less sensitive to body bias as compared to a long channel MOSFET. For the same reason, the DIBL effect and the channel length dependence of Vth are stronger as Vbs is made more negative. This was verified by experimental data shown in Figure 2-3 and Figure 2-4. Although Liu et al. found an accelerated Vth roll-off and non-linear drain voltage dependence [10] as the channel became very short, a linear dependence of Vth on Vds is nevertheless a good approximation for circuit simulation as shown in Figure 2-4. This figure shows that Eq. (2.1.13) can fit the experimental data very well.
2-10
Furthermore, Figure 2-5 shows how this Vth model can fit various channel lengths under various bias conditions.
Figure 2-3. Threshold voltage versus the drain voltage at different body biases.
Figure 2-4. Channel length dependence of threshold voltage.
2-11
Figure 2-5. Threshold voltage versus channel length at different biases.
2.1.4 Narrow Channel Effect

The actual depletion region in the channel is always larger than what is usually assumed under the one-dimensional analysis due to the existence of fringing fields [2]. This effect becomes very substantial as the channel width decreases and the depletion region underneath the fringing field becomes comparable to the "classical" depletion layer formed from the vertical field. The net result is an increase in Vth. It is shown in [2] that this increase can be modeled as: (2.1.23)
T qN a X d max = 3 ox s 2C ox W W
2
2-12
The right hand side of Eq. (2.1.23) represents the additional voltage increase. This change in Vth is modeled by Eq. (2.1.24a). This formulation includes but is not limited to the inverse of channel width due to the fact that the overall narrow width effect is dependent on process (i.e. isolation technology) as well. Hence, parameters K3, K3b, and W0 are introduced as (2.1.24a)
(K 3 + K3bVbs )
Tox s Weff '+W0
Weff is the effective channel width (with no bias dependencies), which will be defined in Section 2.8. In addition, we must consider the narrow width effect for small channel lengths. To do this we introduce the following: (2.1.24b) Weff Leff Weff Leff DVT 0 w exp( DVT 1w ) + 2 exp( DVT 1w ) (Vbi s ) 2ltw ltw
' '
When all of the above considerations for non-uniform doping, short and narrow channel effects on threshold voltage are considered, the final complete Vth expression implemented in SPICE is as follows:
2-13
(2.1.25)
Vth = Vth0ox + K1ox s Vbseff K2oxVbseff Nlx T + K1ox 1 + 1 s + (K3 + K3bVbseff ) ox s Leff Weff '+W0 Weff ' Leff Weff ' Leff DVT0w (Vbi s ) exp DVT1w 2l + 2exp DVT1w l tw tw Leff Leff DVT0 + D D exp 2 exp VT VT 1 1 (Vbi s ) l l 2 t t Leff Leff exp + D D 2 exp sub sub (Etao + EtabVbseff )Vds l 2 l to to
where Tox dependence is introduced in the model parameters K1 and K2 to improve the scalibility of Vth model with respect to Tox. Vth0ox, K1ox and K2ox are modeled as
Vth0ox =Vth0 K1 s
and K 1ox = K 1 K 2 ox = K 2 Tox Toxm Tox Toxm
Toxm is the gate oxide thickness at which parameters are extracted with a default value of Tox. In Eq. (2.1.25), all Vbs terms have been substituted with a Vbseff expression as shown in Eq. (2.1.26). This is done in order to set an upper bound for the body bias value during simulations since unreasonable values can occur if this expression is not introduced (see Section 3.8 for details).
2-14
Mobility Model
(2.1.26)
Vbseff = Vbc + 0.5[Vbs Vbc 1 + (Vbs Vbc 1) 2 4 1Vbc ]
where 1 = 0.001V. The parameter Vbc is the maximum allowable Vbs value and is calculated from the condition of dVth/dVbs=0 for the Vth expression of 2.1.4, 2.1.5, and 2.1.6, and is equal to:
2 K1 Vbc = 0.9 s 2 4K 2
2.2 Mobility Model

A good mobility model is critical to the accuracy of a MOSFET model. The scattering mechanisms responsible for surface mobility basically include phonons, coulombic scattering, and surface roughness [11, 12]. For good quality interfaces, phonon scattering is generally the dominant scattering mechanism at room temperature. In general, mobility depends on many process parameters and bias conditions. For example, mobility depends on the gate oxide thickness, substrate doping concentration, threshold voltage, gate and substrate voltages, etc. Sabnis and Clemens [13] proposed an empirical unified formulation based on the concept of an effective field Eeff which lumps many process parameters and bias conditions together. Eeff is defined by Q + ( Qn 2 ) Eeff = B si (2.2.1)
The physical meaning of Eeff can be interpreted as the average electrical field experienced by the carriers in the inversion layer [14]. The unified formulation of mobility is then given by
2-15
Mobility Model
eff =
1 + ( Eeff E0 )
(2.2.2)
Values for 0, E0, and were reported by Liang et al. [15] and Toh et al. [16] to be the following for electrons and holes
Parameter 0 (cm2/Vsec) E0 (MV/cm)
Electron (surface) 670 0.67 1.6
Hole (surface) 160 0.7 1.0
Table 2-1. Typical mobility values for electrons and holes.
For an NMOS transistor with n-type poly-silicon gate, Eq. (2.2.1) can be rewritten in a more useful form that explicitly relates Eeff to the device parameters [14]
Vgs + Vth Eeff 6 Tox
(2.2.3)
Eq. (2.2.2) fits experimental data very well [15], but it involves a very time consuming power function in SPICE simulation. Taylor expansion Eq. (2.2.2) is used, and the coefficients are left to be determined by experimental data or to be obtained by fitting the unified formulation. Thus, we have
2-16
Carrier Drift Velocity
(mobMod=1)
o eff = V gsteff + 2Vth 2 Vgst gsteff + 2Vth 1 + (Ua + Uc Vbseff )( ) + Ub ( gst ) TOX TOX
(2.2.4)
where Vgst=Vgs-Vth. To account for depletion mode devices, another mobility model option is given by the following (mobMod=2) (2.2.5)
o eff = V gsteff V Vgsteff 1 + (Ua + UcVbseff )( gst ) + Ub ( gst ) 2 TOX TOX

The unified mobility expressions in subthreshold and strong inversion regions will be discussed in Section 3.2. To consider the body bias dependence of Eq. 2.2.4 further, we have introduced the following expression:
(For mobMod=3)
(2.2.6)
eff =
o Vgst Vgsteff + 2Vth 2 gsteff + 2Vth 1 + [Ua ( ) + Ub ( gst ) ](1 + UcVbseff ) TOX TOX
2.3 Carrier Drift Velocity

Carrier drift velocity is also one of the most important parameters. The following velocity saturation equation [17] is used in the model
2-17
Bulk Charge Effect
v=
eff E
1 + ( E Esat )
(2.3.1) , E < Esat E > Esat
= vsat ,
The parameter Esat corresponds to the critical electrical field at which the carrier velocity becomes saturated. In order to have a continuous velocity model at E = Esat, Esat must satisfy: (2.3.2)
Esat = 2 vsat eff
2.4 Bulk Charge Effect

When the drain voltage is large and/or when the channel length is long, the depletion "thickness" of the channel is non-uniform along the channel length. This will cause Vth to vary along the channel. This effect is called bulk charge effect [14]. The parameter, Abulk, is used to take into account the bulk charge effect. Several extracted parameters such as A0, B0, B1 are introduced to account for the channel length and width dependences of the bulk charge effect. In addition, the parameter Keta is introduced to model the change in bulk charge effect under high substrate bias conditions. It should be pointed out that narrow width effects have been considered in the formulation of Eq. (2.4.1). The Abulk expression is given by (2.4.1)
K1ox Abulk = 1 + 2 s Vbseff A0 Leff Leff 1 AgsVgsteff + + L 2 X X L 2 X X eff J dep J dep eff
2
B0 1 + W '+B 1 + KetaV eff 1 bseff
2-18
Strong Inversion Drain Current (Linear Regime)
where A0, Ags, B0, B1 and Keta are determined by experimental data. Eq. (2.4.1) shows that Abulk is very close to unity if the channel length is small, and Abulk increases as channel length increases.
2.5 Strong Inversion Drain Current (Linear Regime)

2.5.1 Intrinsic Case (Rds=0)
In the strong inversion region, the general current equation at any point y along the channel is given by (2.5.1) I ds = WCox (V gst AbulkV ( y ))v ( y ) The parameter Vgst = (Vgs - Vth), W is the device channel width, Cox is the gate capacitance per unit area, V(y) is the potential difference between minority-carrier quasi-Fermi potential and the equilibrium Fermi potential in the bulk at point y, v(y) is the velocity of carriers at point y. With Eq. (2.3.1) (i.e. before carrier velocity saturates), the drain current can be expressed as (2.5.2) I ds = WCox (Vgs Vth AbulkV ( y )) Eq. (2.5.2) can be rewritten as follows
eff E ( y )
1 + E ( y ) E sat
2-19
(2.5.3) E ( y) =
eff WCox (V
gst
I ds dV ( y ) = AbulkV ( y )) I ds E sat dy
By integrating Eq. (2.5.2) from y = 0 to y = L and V(y) = 0 to V(y) = Vds, we arrive at the following (2.5.4) I ds = eff Cox W 1 (Vgs Vth Abulk Vds 2)Vds L 1 + Vds E sat L
The drain current model in Eq. (2.5.4) is valid before velocity saturates. For instances when the drain voltage is high (and thus the lateral electrical field is high at the drain side), the carrier velocity near the drain saturates. The channel region can now be divided into two portions: one adjacent to the source where the carrier velocity is field-dependent and the second where the velocity saturates. At the boundary between these two portions, the channel voltage is the saturation voltage (Vdsat) and the lateral electrical is equal to Esat. After the onset of saturation, we can substitute v = vsat and Vds = Vdsat into Eq. (2.5.1) to get the saturation current: (2.5.5) I ds = WCox (V gst AbulkVdsat )v sat By equating eqs. (2.5.4) and (2.5.5) at E = Esat and V ds = Vdsat, we can solve for saturation voltage Vdsat (2.5.6)
Vdsat = E sat L(V gs Vth ) AbulkE sat L + (V gs Vth )
2-20
2.5.2 Extrinsic Case (Rds>0)

Parasitic source/drain resistance is an important device parameter which can affect MOSFET performance significantly. As channel length scales down, the parasitic resistance will not be proportionally scaled. As a result, Rds will have a more significant impact on device characteristics. Modeling of parasitic resistance in a direct method yields a complicated drain current expression. In order to make simulations more efficient, the parasitic resistances is modeled such that the resulting drain current equation in the linear region can be calculateed [3] as (2.5.9)
I ds = V ds V ds = R tot R ch + R ds ( Vgst A bulk Vds 2 ) Vds 1 W W ( Vgst A bulk Vds 2 ) L 1 + Vds ( E sat L ) 1 + R ds eff C ox 1 + Vds ( E sat L ) L
= eff C ox
Due to the parasitic resistance, the saturation voltage Vdsat will be larger than that predicted by Eq. (2.5.6). Let Eq. (2.5.5) be equal to Eq. (2.5.9). Vdsat with parasitic resistance Rds becomes (2.5.10)
Vdsat = b b 2 4 ac 2a
The following are the expression for the variables a, b, and c:
2-21
Strong Inversion Current and Output Resistance (Saturation Regime)
(2.5.11)
2 a = Abulk Rds Cox Wv sat + (
1 1) Abulk
b = (Vgst (
2 1) + Abulk E sat L + 3 Abulk Rds Cox Wv sat Vgst ) 2 c = Esat LVgst + 2 Rds Cox Wvsat Vgst = A1Vgst + A 2
The last expression for is introduced to account for non-saturation effect of the device. The parasitic resistance is modeled as: (2.5.11)
Rds = Rdsw 1 + PrwgVgsteff + Prwb s Vbseff s
(10 W ')
6 eff
))
Wr
The variable Rdsw is the resistance per unit width, Wr is a fitting parameter, Prwb and Prwg are the body bias and the gate bias coeffecients, repectively.
2.6 Strong Inversion Current and Output Resistance (Saturation Regime)

A typical I-V curve and its output resistance are shown in Figure 2-6. Considering only the drain current, the I-V curve can be divided into two parts: the linear region in which the drain current increases quickly with the drain voltage and the saturation region in which the drain current has a very weak dependence on the drain voltage. The first order derivative reveals more detailed information about the physical mechanisms which are involved during device operation. The output resistance (which is the reciprocal of the first order derivative of the I-V curve)
2-22
curve can be clearly divided into four regions with distinct Rout dependences.
v s. V ds
The first region is the triode (or linear) region in which carrier velocity is not saturated. The output resistance is very small because the drain current has a strong dependence on the drain voltage. The other three regions belong to the saturation region. As will be discussed later, there are three physical mechanisms which affect the output resistance in the saturation region: channel length modulation (CLM) [4, 14], drain-induced barrier lowering (DIBL) [4, 6, 14], and the substrate current induced body effect (SCBE) [14, 18, 19]. All three mechanisms affect the output resistance in the saturation range, but each of them dominates in only a single region. It will be shown next that channel length modulation (CLM) dominates in the second region, DIBL in the third region, and SCBE in the fourth region.
3.0 14
Triode
2.5
CLM
DIBL
SCBE
12
10 2.0
Rout (KOhms)
Ids (mA)
8 1.5 6 1.0 4 0.5
0.0 0 1 2 3 4
V ds (V)
Figure 2-6. General behavior of MOSFET output resistance.
2-23
Generally, drain current is a function of the gate voltage and the drain voltage. But the drain current depends on the drain voltage very weakly in the saturation region. A Taylor series can be used to expand the drain current in the saturation region [3]. (2.6.1) Ids (Vgs , Vds ) = Ids (Vgs , Vdsat ) +
Ids (Vgs , Vds ) Vds
(Vds Vdsat )
V Vdsat Idsat (1 + ds ) VA where (2.6.2)

I dsat = I ds ( Vgs ,Vdsat ) = Wv sat Cox ( Vgst Abulk Vdsat )
and (2.6.3)
VA = I dsat (
Ids 1 ) Vds
The parameter VA is called the Early voltage and is introduced for the analysis of the output resistance in the saturation region. Only the first order term is kept in the Taylor series. We also assume that the contributions to the Early voltage from all three mechanisms are independent and can be calculated separately.
2-24
2.6.1 Channel Length Modulation (CLM)

If channel length modulation is the only physical mechanism to be taken into account, then according to Eq. (2.6.3), the Early voltage can be calculated by (2.6.4) I L 1 Abulk Esat L + Vgst L 1 ) = ( ) VACLM = I dsat ( ds L Vds Vds Abulk Esat where L is the length of the velocity saturation region; the effective channel length is L-L. Based on the quasi-two dimensional approximation, VACLM can be derived as the following
Abulk Esat L + Vgst Abulk Esat l
(2.6.5)
(Vds Vdsat )
VACLM =
where VACLM is the Early Voltage due to channel length modulation alone. The parameter Pclm is introduced into the VACLM expression not only to compensate for the error caused by the Taylor expansion in the Early voltage model, but also to compensate for the error in XJ since
l XJ
and the junction depth XJ can not generally be determined very accurately. Thus, the VACLM became
Abulk Esat L + Vgst Abulk Esat l
(2.6.6)
( Vds Vdsat )
VACLM =
1 Pclm
2-25
2.6.2 Drain-Induced Barrier Lowering (DIBL)

As discussed above, threshold voltage can be approximated as a linear function of the drain voltage. According to Eq. (2.6.3), the Early voltage due to the DIBL effect can be calculated as: (2.6.7) VADIBLC = I dsat ( VADIBLC =
I ds Vth 1 1 1 ) = + (Vgst ( Vth Vds th ( L ) Abulk Vdsat V
(Vgsteff + 2vt) AbulkVdsat 1 rout(1+ PDIBLCBVbseff ) AbulkVdsat + Vgsteff + 2vt
During the derivation of Eq. (2.6.7), the parasitic resistance is assumed to be equal to 0. As expected, VADIBLC is a strong function of L as shown in Eq. (2.6.7). As channel length decreases, VADIBLC decreases very quickly. The combination of the CLM and DIBL effects determines the output resistance in the third region, as was shown in Figure 2-6. Despite the formulation of these two effects, accurate modeling of the output resistance in the saturation region requires that the coefficient th(L) be replaced by rout(L). Both th(L) and rout(L) have the same channel length dependencies but different coefficients. The expression for rout(L) is (2.6.8) rout ( L ) = Pdiblc1 [exp( Drout L / 2lt ) + 2 exp( Drout L / lt )] + Pdiblc 2 Parameters Pdiblc1, Pdiblc2, Pdiblcb and Drout are introduced to correct for DIBL effect in the strong inversion region. The reason why Dvt0 is not
2-26
equal to Pdiblc1 and Dvt1 is not equal to Drout is because the gate voltage modulates the DIBL effect. When the threshold voltage is determined, the gate voltage is equal to the threshold voltage. But in the saturation region where the output resistance is modeled, the gate voltage is much larger than the threshold voltage. Drain induced barrier lowering may not be the same at different gate bias. Pdiblc2 is usually very small (may be as small as 8.0E-3). If Pdiblc2 is placed into the threshold voltage model, it will not cause any significant change. However it is an important parameter in VADIBL for long channel devices, because Pdiblc2 will be dominant in Eq. (2.6.8) if the channel is long.
2.6.3 Current Expression without Substrate Current Induced Body Effect

In order to have a continuous drain current and output resistance expression at the transition point between linear and saturation region, the VAsat parameter is introduced into the Early voltage expression. VAsat is the Early Voltage at Vds = Vdsat and is as follows: (2.6.9) Esat L + Vdsat + 2 Rds vsat Cox W ( Vgst Abulk Vds / 2 ) VAsat = 1 + Abulk Rds vsat Cox W Total Early voltage, VA, can be written as (2.6.10)
VA = VAsat + ( 1 VACLM + 1 VADIBL ) 1
2-27
The complete (with no impact ionization at high drain voltages) current expression in the saturation region is given by (2.6.11) Idso = Wv sat Cox (Vgst Abulk Vdsat )(1 + Vds Vdsat ) VA
Furthermore, another parameter, Pvag, is introduced in VA to account for the gate bias dependence of VA more accurately. The final expression for Early voltage becomes (2.6.12)
VA = VAsat + (1 +
gsteff PvagVgs 1 1 + )( ) 1 E satLeff VACLM VADIBLC
2.6.4 Current Expression with Substrate Current Induced Body Effect

When the electrical field near the drain is very large (> 0.1MV/cm), some electrons coming from the source will be energetic (hot) enough to cause impact ionization. This creates electron-hole pairs when they collide with silicon atoms. The substrate current Isub thus created during impact ionization will increase exponentially with the drain voltage. A well known Isub model [20] is given as: (2.6.13)
I sub = Ai Bil I ds (Vds Vdsat )exp Bi Vds Vdsat
2-28
The parameters Ai and Bi are determined from extraction. Isub will affect the drain current in two ways. The total drain current will change because it is the sum of the channel current from the source as well as the substrate current. The total drain current can now be expressed [21] as follows (2.6.14) I ds = Idso + I sub (Vds Vdsat ) = Idso 1 + Bi Bil exp( ) Ai Vds Vdsat The total drain current, including CLM, DIBL and SCBE, can be written as (2.6.15) I ds = Wv sat Cox (Vgst Abulk Vdsat )(1 + Vds Vdsat Vds Vdsat )(1 + ) VA VASCBE
where VASCBE can also be called as the Early voltage due to the substrate current induced body effect. Its expression is the following (2.6.16)
VASCBE Bi Bil = exp( ) Ai Vds Vdsat
From Eq. (2.6.16), we can see that VASCBE is a strong function of Vds. In addition, we also observe that VASCBE is small only when Vds is large. This is why SCBE is important for devices with high drain voltage bias. The channel length and gate oxide dependence of VASCBE comes from Vdsat and l. We replace Bi with PSCBE2 and Ai/Bi with PSCBE1/L to yield the following expression for VASCBE
2-29
Subthreshold Drain Current
(2.6.17) P P l = SCBE 2 exp( SCBE1 ) VASCBE L Vds Vdsat The variables Pscbe1 and Pscbe2 are determined experimentally. 1
2.7 Subthreshold Drain Current

The drain current equation in the subthreshold region can be expressed as [2, 3] (2.7.1) I ds = I s 0 (1 exp( Vgs Vth Voff Vds )) exp( ) nv vt nvttm (2.7.2)
I s0 = 0 W L q si N ch 2 vt 2 s
Here the parameter vt is the thermal voltage and is given by KBT/q. Voff is the offset voltage, as discussed in Jeng's dissertation [18]. Voff is an important parameter which determines the drain current at Vgs = 0. In Eq. (2.7.1), the parameter n is the subthreshold swing parameter. Experimental data shows that the subthreshold swing is a function of channel length and the interface state density. These two mechanisms are modeled by the following (2.7.3) Leff Leff (Cdsc + CdscdVds + Cdscb Vbseff ) exp(DVT1 ) + 2 exp(DVT1 ) Cd lt Cit 2lt + + n = 1 + Nfactor Cox Cox Cox
where the term
2-30
Effective Channel Length and Width
Leff Leff (Cdsc + CdscdVds + Cdscb Vbseff ) ) + 2 exp( DVT 1 ) exp( DVT 1 lt 2lt
represents the coupling capacitance between the drain or source to the channel. The parameters Cdsc, Cdscd and Cdscb are extracted. The parameter Cit in Eq. (2.7.3) is the capacitance due to interface states. From Eq. (2.7.3), it can be seen that subthreshold swing shares the same exponential dependence on channel length as the DIBL effect. The parameter Nfactor is introduced to compensate for errors in the depletion width capacitance calculation. Nfactor is determined experimentally and is usually very close to 1.
2.8 Effective Channel Length and Width

The effective channel length and width used in all model expressions is given below (2.8.1)
L eff = L drawn 2 dL
(2.8.2a)
Weff = Wdrawn 2 dW
(2.8.2b)
Weff = Wdrawn 2 dW
The only difference between Eq. (2.8.2a) and (2.8.2b) is that the former includes bias dependencies. The parameters dW and dL are modeled by the following
2-31
Effective Channel Length and Width
(2.8.3)
dW = dW '+ dWgV gsteff + dWb dW ' = Wint +
Vbseff s
Wl Ww W + Wwn + W ln wl Wwn W ln L W L W
(2.8.4) dL = Lint + Ll L Lw + Lwn + L ln wl Lwn L ln W L L W
These complicated formulations require some explanation. From Eq. (2.8.3), the variable Wint models represents the tradition manner from which "delta W" is extracted (from the intercepts of straights lines on a 1/Rds vs. Wdrawn plot). The parameters dWg and dWb have been added to account for the contribution of both front gate and back side (substrate) biasing effects. For dL, the parameter Lint represents the traditional manner from which "delta L" is extracted (mainly from the intercepts of lines from a Rds vs. Ldrawn plot). The remaining terms in both dW and dL are included for the convenience of the user. They are meant to allow the user to model each parameter as a function of Wdrawn, Ldrawn and their associated product terms. In addition, the freedom to model these dependencies as other than just simple inverse functions of W and L is also provided for the user. For dW, they are Wln and Wwn. For dL they are Lln and Lwn. By default all of the above geometrical dependencies for both dW and dL are turned off. Again, these equations are provided for the convenience of the user. As such, it is up to the user to adopt the correct extraction strategy to ensure proper use.
2-32
Poly Gate Depletion Effect
2.9 Poly Gate Depletion Effect

When a gate voltage is applied to a heavily doped poly-silicon gate, e.g. NMOS with n+ poly-silicon gate, a thin depletion layer will be formed at the interface between the poly-silicon and gate oxide. Although this depletion layer is very thin due to the high doping concentration of the poly-Si gate, its effect cannot be ignored in the 0.1m regime since the gate oxide thickness will also be very small, possibly 50 or thinner. Figure 2-7 shows an NMOSFET with a depletion region in the n+ poly-silicon gate. The doping concentration in the n+ poly-silicon gate is Ngate and the doping concentration in the substrate is Nsub. The gate oxide thickness is Tox. The depletion width in the poly gate is Xp. The depletion width in the substrate is Xd. If we assume the doping concentration in the gate is infinite, then no depletion region will exist in the gate, and there would be one sheet of positive charge whose thickness is zero at the interface between the poly-silicon gate and gate oxide. In reality, the doping concentration is, of course, finite. The positive charge near the interface of the poly-silicon gate and the gate oxide is distributed over a finite depletion region with thickness Xp. In the presence of the depletion region, the voltage drop across the gate oxide and the substrate will be reduced, because part of the gate voltage will be dropped across the depletion region in the gate. That means the effective gate voltage will be reduced.
2-33
Ngate
Figure 2-7. Charge distribution in a MOSFET with the poly gate depletion effect. The device is in the strong inversion region.
The effective gate voltage can be calculated in the following manner. Assume the doping concentration in the poly gate is uniform. The voltage drop in the poly gate (Vpoly) can be calculated as (2.9.1)
poly =
1 X poly E poly = 2
2 Ngate qN poly X poly
2 si
where Epoly is the maximum electrical field in the poly gate. The boundary condition at the interface of poly gate and the gate oxide is (2.9.2)
ox Eox = si E poly = 2q si Ngate polyV poly
2-34
where Eox is the electrical field in the gate oxide. The gate voltage satisfies (2.9.3)
Vgs VFB s = V poly + Vox

where Vox is the voltage drop across the gate oxide and satisfies Vox = EoxTox. According to the equations (2.9.1) to (2.9.3), we obtain the following (2.9.4)
a(Vgs VFB s Vpoly) Vpoly = 0

2
where
(2.9.5)
a=
ox 2
2q si N gateTox
2
By solving the equation (2.9.4), we get the effective gate voltage (Vgs_eff) which is equal to: (2.9.6)
Vgs_ eff
2 2 q si NgateTox 2ox (Vgs VFB s ) 1+ = VFB + s + 1 2 ox2 q si NgateTox
Figure 2-8 shows Vgs_eff / Vgs versus the gate voltage. The threshold voltage is assumed to be 0.4V. If Tox = 40 , the effective gate voltage can be reduced by 6% due to the poly gate depletion effect as the applied gate voltage is equal to 3.5V.
2-35
1.00
Tox=80A 80
Vgs_eff / Vgs Vgs_eff/Vgs
Tox=60A 60
0.95
To x = 40 Tox=40A
0.90 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Vgs V g s (V) (V) Figure 2-8. The effective gate voltage versus applied gate voltage at different gate oxide thickness.
The drain current reduction in the linear region as a function of the gate voltage can now be determined. Assume the drain voltage is very small, e.g. 50mV. Then the linear drain current is proportional to Cox(Vgs - Vth). The ratio of the linear drain current with and without poly gate depletion is equal to: (2.9.7) I ds (V gs _ eff ) I ds (V gs ) = (V gs _ eff Vth ) (V gs Vth )
Figure 2-9 shows Ids(Vgs_eff) / Ids(Vgs) versus the gate voltage using Eq. (2.9.7). The drain current can be reduced by several percent due to gate depletion.
2-36
1.00
Tox=80A 80 Ids(Vgs_eff)/Ids(Vgs) Ids(Vgs_eff) / Ids(Vgs)
60 Tox=60A 0.95
To x = 40 Tox=40A
0.90 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Vgs V (V) (V) Figure 2-9. Ratio of linear region current with poly gate depletion effect and that without.
2-37
2-38
2-39
2-40
CHAPTER 3: Unified I-V Model
The development of separate model expressions for such device operation regimes as subthreshold and strong inversion were discussed in Chapter 2. Although these expressions can accurately describe device behavior within their own respective region of operation, problems are likely to occur between two well-described regions or within transition regions. In order to circumvent this issue, a unified model should be synthesized to not only preserve region-specific expressions but also to ensure the continuities of current and conductance and their derivatives in all transition regions as well. Such high standards are kept in BSIM3v3.2.1 . As a result, convergence and simulation efficiency are much improved. This chapter will describe the unified I-V model equations. While most of the parameter symbols in this chapter are explained in the following text, a complete description of all IV model parameters can be found in Appendix A.
3.1 Unified Channel Charge Density Expression

Separate expressions for channel charge density are shown below for subthreshold (Eq. (3.1.1a) and (3.1.1b)) and strong inversion (Eq. (3.1.2)). Both expressions are valid for small Vds.
3-1
Unified Channel Charge Density Expression
(3.1.1a) Qchsubs 0 = Q0 exp( where Q0 is (3.1.1b)

Q0 = qsiNch Voff vt exp( ) nvt 2s
Vgs Vth ) nvt
(3.1.2)
Qchs 0 = Cox (Vgs Vth )
In both Eqs. (3.1.1a) and (3.1.2), the parameters Qchsubs0 and Qchs0 are the channel charge densities at the source for very small Vds. To form a unified expression, an effective (Vgs-Vth) function named Vgsteff is introduced to describe the channel charge characteristics from subthreshold to strong inversion (3.1.3)
Vgs Vth 2 n vt ln 1 + exp( ) 2 n vt = 2 s Vgs Vth 2Voff 1 + 2 n COX exp( ) 2 n vt qsiNch
Vgsteff
The unified channel charge density at the source end for both subthreshold and inversion region can therefore be written as (3.1.4)
Qchs0 = CoxVgsteff
Figures 3-1 and 3-2 show the smoothness of Eq. (3.1.4) from subthreshold to strong inversion regions. The Vgsteff expression will be used again in subsequent sections of this chapter to model the drain current.
3-2
3.0 2.5 2.0 1.5
Vgsteff Function
exp[(Vgs-Vth)/n*vt]
Vgsteff (V)
1.0 0.5 0.0
-0.5 -1.0
Vgs=Vth
(Vgs-Vth)
-1.5 -1.0 -0.5 0.0
Vgs-Vth V gs-Vth (V)(V)
0.5
1.0
1.5
2.0
Figure 3-1. The Vgsteff function vs. (Vgs-Vth) in linear scale.

4 2 0
Log(Vgsteff)
Log(Vgsteff)
-2 -4 -6 -8 -10 -12 -14 -16 -1.0
(Vgs-Vth)
exp[(Vgs-Vth)/n*vt]
Vgs=Vth
-0.5 0.0 0.5 1.0 1.5 2.0 2.5
Vgs-Vth V gs-Vth (V) (V)
Figure 3-2. Vgsteff function vs. (Vgs-Vth) in log scale.
3-3
Eq. (3.1.4) serves as the cornerstone of the unified channel charge expression at the source for small Vds. To account for the influence of Vds, the Vgsteff function must keep track of the change in channel potential from the source to the drain. In other words, Eq. (3.1.4) will have to include a y dependence. To initiate this formulation, consider first the re-formulation of channel charge density for the case of strong inversion (3.1.5)
Qchs( y) = Cox(Vgs Vth AbulkVF( y))

The parameter VF(y) stands for the quasi-Fermi potential at any given point y, along the channel with respect to the source. This equation can also be written as (3.1.6)
Qchs ( y ) = Qchs0 + Qchs( y )
The term Qchs(y) is the incremental channel charge density induced by the drain voltage at point y. It can be expressed as (3.1.7)
Qchs ( y ) = CoxAbulkVF ( y )
For the subthreshold region (Vgs<<Vth), the channel charge density along the channel from source to drain can be written as (3.1.8)
Vgs Vth AbulkVF ( y ) Qchsubs( y ) = Q0 exp( ) nvt AbulkVF ( y ) = Qchsubs0 exp( ) nvt
3-4
A Taylor series expansion of the right-hand side of Eq. (3.1.8) yields the following (keeping only the first two terms) (3.1.9)
Qchsubs( y) = Qchsubs 0(1
AbulkVF( y) ) nvt
Analogous to Eq. (3.1.6), Eq. (3.1.9) can also be written as (3.1.10)
Qchsubs( y) = Qchsubs0 + Qchsubs( y)

The parameter Qchsubs(y) is the incremental channel charge density induced by the drain voltage in the subthreshold region. It can be written as (3.1.11)
Qchsubs( y) =
AbulkVF ( y ) Qchsubs0 nvt
Note that Eq. (3.1.9) is valid only when VF(y) is very small, which is maintained fortunately, due to the fact that Eq. (3.1.9) is only used in the linear regime (i.e. Vds 2vt). Eqs. (3.1.6) and (3.1.10) both have drain voltage dependencies. However, they are decupled and a unified expression for Qch(y) is needed. To obtain a unified expression along the channel, we first assume (3.1.12)
Qchs ( y ) Qchsubs( y ) Qch ( y ) = Qchs ( y ) + Qchsubs ( y )
Here, Qch(y) is the incremental channel charge density induced by the drain voltage. Substituting Eq. (3.1.7) and (3.1.11) into Eq. (3.1.12), we obtain
3-5
Unified Mobility Expression
(3.1.13) Qch ( y ) = VF ( y ) Qchs 0 Vb
where Vb = (Vgsteff + n*vt)/Abulk. In order to remove any association between the variable n and bias dependencies (Vgsteff) as well as to ensure more precise modeling of Eq. (3.1.8) for linear regimes (under subthreshold conditions), n is replaced by 2. The expression for Vb now becomes (3.1.14)
Vb =
Vgsteff + 2vt Abulk
A unified expression for Qch(y) from subthreshold to strong inversion regimes is now at hand (3.1.15)
Qch( y ) = Qchs 0(1

The variable Qchs0 is given by Eq. (3.1.4).
VF ( y) ) Vb
3.2 Unified Mobility Expression

Unified mobility model based on the Vgsteff expression of Eq. 3.1.3 is described in the following.
3-6
Unified Linear Current Expression
(mobMod = 1)
eff =
1 + (Ua + Uc Vbseff )(
Vgsteff TOX
o + 2Vth
(3.2.1)
) + Ub ( Vgsteff + 2Vth 2 ) TOX
To account for depletion mode devices, another mobility model option is given by the following (mobMod = 2) (3.2.2)
o eff = Vgsteff 2 Vgsteff 1 + (Ua + UcVbseff )( ) + Ub ( ) TOX TOX

To consider the body bias dependence of Eq. 3.2.1 further, we have introduced the following expression (For mobMod = 3) (3.2.3)
eff =
o Vgsteff + 2Vth 2 Vgsteff + 2Vth 1 + [Ua ( ) + Ub ( ) ](1 + UcVbseff ) TOX TOX
3.3 Unified Linear Current Expression

3.3.1 Intrinsic case (Rds=0)
Generally, the following expression [2] is used to account for both drift and diffusion current
3-7
Unified Linear Current Expression
(3.3.1)
Id ( y ) = WQch ( y ) ne ( y ) dVF ( y ) dy
where the parameter une(y) can be written as (3.3.2)
ne ( y ) =
eff Ey 1+ Esat
Substituting Eq. (3.3.2) in Eq. (3.3.1) we get (3.3.3) Id ( y ) = WQchso(1 VF ( y ) eff dVF ( y ) ) Vb 1 + Ey dy Esat
Eq. (3.3.3) resembles the equation used to model drain current in the strong inversion regime. However, it can now be used to describe the current characteristics in the subthreshold regime when Vds is very small (Vds<2vt). Eq. (3.3.3) can now be integrated from the source to drain to get the expression for linear drain current in the channel. This expression is valid from the subthreshold regime to the strong inversion regime (3.3.4)
V ds 1 W eff Q chs 0V ds 2V b = V ds + 1 L E L sat
I ds 0
3-8
Unified Vdsat Expression
3.3.2 Extrinsic Case (Rds > 0)

The current expression when Rds > 0 can be obtained based on Eq. (2.5.9) and Eq. (3.3.4). The expression for linear drain current from subthreshold to strong inversion is: (3.3.5)
Ids =
Idso RdsIdso 1+ Vds
3.4 Unified Vdsat Expression

3.4.1 Intrinsic case (Rds=0)
To get an expression for the electric field as a function of y along the channel, we integrate Eq. (3.3.1) from 0 to an arbitrary point y. The result is as follows (3.4.1)
Ey = (WQchs 0 eff Idso Idso 2 2 Ids 0 WQchs 0 eff y ) Esat Vb
If we assume that drift velocity saturates when Ey=Esat, we get the following expression for Idsat (3.4.2)
Idsat WeffQchs 0 EsatLVb = 2 L( EsatL + Vb )
3-9
Unified Vdsat Expression
Let Vds=Vdsat in Eq. (3.3.4) and set this equal to Eq. (3.4.2), we get the following expression for Vdsat (3.4.3) Vdsat = EsatL(Vgsteff + 2 vt ) AbulkEsatL + Vgsteff + 2 vt
3.4.2 Extrinsic Case (Rds>0)

The Vdsat expression for the extrinsic case is formulated from Eq. (3.4.3) and Eq. (2.5.10) to be the following (3.4.4a)
Vdsat =
where
b b 4ac 2a
2
(3.4.4b)
a = A bulk 2WeffsatCoxR DS + (
1 1) A bulk
(3.4.4c)
2 b = (Vgsteff + 2vt )( 1) + AbulkEsatLeff + 3 Abulk (Vgsteff + 2vt )WeffsatCoxRDS

(3.4.4d)
c = (Vgsteff + 2vt ) EsatLeff + 2(Vgsteff + 2 vt ) WeffsatCoxR DS

2
(3.4.4e)
= A1Vgsteff + A2
3-10
Unified Saturation Current Expression
The parameter is introduced to account for non-saturation effects. Parameters A1 and A2 can be extracted.
3.5 Unified Saturation Current Expression

A unified expression for the saturation current from the subthreshold to the strong inversion regime can be formulated by introducing the Vgsteff function into Eq. (2.6.15). The resulting equations are the following (3.5.1)
Ids =
Idso ( Vdsat ) Vds Vdsat Vds Vdsat 1 + 1 + RdsIdso ( Vdsat ) V V A ASCBE 1+ Vdsat
where (3.5.2)
VA = VAsat + (1 +
PvagVgsteff 1 1 + )( ) 1 E satLeff VACLM VADIBLC

(3.5.3)
EsatLeff + Vdsat + 2 RDSsatCoxWeffVgsteff [1 VAsat =
AbulkVdsat ] 2(Vgsteff + 2vt )
2 / 1 + RDSsatCoxWeffAbulk
(3.5.4)
VACLM =
AbulkEsatLeff + Vgsteff (Vds Vdsat ) PCLMAbulkEsat litl
3-11
Single Current Expression for All Operating Regimes of Vgs and Vds
(3.5.5) VADIBLC = (Vgsteff + 2 vt ) AbulkVdsat 1 AbulkVdsat + Vgsteff + 2vt rout (1 + PDIBLCBVbseff ) (3.5.6)
Leff Leff rout = PDIBLC1 exp( DROUT ) + 2 exp( DROUT ) + PDIBLC 2 2 lt 0 lt 0
(3.5.7)
1 VASCBE
Pscbe1 litl Pscbe 2 exp Vds Vdsat Leff
3.6 Single Current Expression for All Operating Regimes of Vgs and Vds
The Vgsteff function introduced in Chapter 2 gave a unified expression for the linear drain current from subthreshold to strong inversion as well as for the saturation drain current from subthreshold to strong inversion, separately. In order to link the continuous linear current with that of the continuous saturation current, a smooth function for Vds is introduced. In the past, several smoothing functions have been proposed for MOSFET modeling [22-24]. The smoothing function used in BSIM3 is similar to that proposed in [24]. The final current equation for both linear and saturation current now becomes (3.6.1)
Idso ( Vdseff ) Vds Vdseff Vds Vdseff Ids = 1 + 1 + RdsIdso( Vdseff ) VA VASCBE 1+ Vdseff
Most of the previous equations which contain Vds and Vdsat dependencies are now substituted with the Vdseff function. For example, Eq. (3.5.4) now becomes
3-12
(3.6.2)
VACLM =
AbulkEsatLeff + Vgsteff (Vds Vdseff ) PCLMAbulkEsat litl
Similarly, Eq. (3.5.7) now becomes (3.6.3)
1 VASCBE
Pscbe2 Pscbe1 litl exp Vds Vdseff Leff
The Vdseff expression is written as
Vdseff = Vdsat
1 Vdsat Vds + (Vdsat Vds )2 + 4Vdsat 2
(3.6.4)
The expression for Vdsat is that given under Section 3.4. The parameter in the unit of volts can be extracted. The dependence of Vdseff on Vds is given in Figure 33. The Vdseff function follows Vds in the linear region and tends to Vdsat in the saturation region. Figure 3-4 shows the effect of on the transition region between linear and saturation regimes.
3-13
1.4
Vdseff=Vdsat
1.2
Vdseff=Vds
1.0
Vdseff (V)
0.8
0.6
Vgs=1V Vgs=3V Vgs=5V
0.4
0.2
0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Vds (V)
Figure 3-3. Vdseff vs. Vds for =0.01 and different Vgs.
Vdseff=Vdsat
2.0
Vdseff=Vds
1.5
=0.05 =0.01
Vdseff (V)
1.0
=0.001
0.5
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Vds (V)
Figure 3-4. Vdseff vs. Vds for Vgs=3V and different values.
3-14
Substrate Current
3.7 Substrate Current

The substrate current in BSIM3v3.2.1 is modeled by (3.7.1)
I sub =
0 + 1 Leff
Leff
(V
ds
0 Vdseff )exp V V dseff ds
I ds 0 R I 1 + ds ds 0 Vdseff
Vds Vdseff 1 + VA
where parameters 0 and 0 are impact ionization coefficients; parameter 1 improves the Isub scalability.
3.8 A Note on Vbs

All Vbs terms have been substituted with a Vbseff expression as shown in Eq. (3.8.1). This is done in order to set an upper bound for the body bias value during simulations. Unreasonable values can occur if this expression is not introduced. (3.8.1)
Vbseff = Vbc + 0.5[Vbs Vbc 1 + (Vbs Vbc 1)2 4 1Vbc ]
where 1=0.001V. Parameter Vbc is the maximum allowable Vbs value and is obtained based on the condition of dVth/dVbs = 0 for the Vth expression of 2.1.4.
3-15
A Note on Vbs
3-16
CHAPTER 4: Capacitance Modeling
Accurate modeling of MOSFET capacitance plays equally important role as that of the DC model. This chapter describes the methodology and device physics considered in both intrinsic and extrinsic capacitance modeling in BSIM3v3.2.2. Detailed model equations are given in Appendix B. One of the important features of BSIM3v3.2 is introduction of a new intrinsic capacitance model (capMod=3 as the default model), considering the finite charge thickness determined by quantum effect, which becomes more important for thinner Tox CMOS technologies. This model is smooth, continuous and accurate throughout all operating regions.
4.1 General Description of Capacitance Modeling

BSIM3v3.2.2 models capacitance with the following general features:
Separate effective channel length and width are used for capacitance models. The intrinsic capacitance models, capMod=0 and 1, use piece-wise equations. capMod=2 and 3 are smooth and single equation models; therefore both charge and capacitance are continous and smooth over all regions. Threshold voltage is consistent with DC part except for capMod=0, where a longchannel Vth is used. Therefore, those effects such as body bias, short/narrow channel and DIBL effects are explicitly considered in capMod=1, 2, and 3. Overlap capacitance comprises two parts: (1) a bias-independent component which models the effective overlap capacitance between the gate and the heavily doped source/drain; (2) a gate-bias dependent component between the gate and the lightly doped source/drain region.
4-1
Geometry Definition for C-V Modeling
Bias-independent fringing capacitances are added between the gate and source as well as the gate and drain.
Name capMod vfbcv acde moin cgso cgdo CGS1 CGD1 CKAPPA CF CLC CLE DWC DLC
Function Flag for capacitance models the flat-band voltage for capMod = 0 Exponential coefficient for XDC for accumulation and depletion regions Coefficient for the surface potential Non-LDD region G/S overlap C per channel length Non-LDD region G/D overlap C per channel length Lightly-doped source to gate overlap capacitance Lightly-doped drain to gate overlap capacitance Coefficient for lightly-doped overlap capacitance Fringing field capacitance Constant term for short channel model Exponential term for short channel model Long channel gate capacitance width offset Long channel gate capacitance length offset
Default 3 -1.0 1 15 Calculated Calculated 0 0 0.6 equation (4.5.1) 0.1 0.6 Wint Lint
Unit (True) (V) (m/V) (V0.5) F/m F/m (F/m) (F/m)
(F/m) m
m m
Table 4-1. Model parameters in capacitance models.
4.2 Geometry Definition for C-V Modeling

For capacitance modeling, MOSFETs can be divided into two regions: intrinsic and extrinsic. The intrinsic capacitance is associated with the region between the metallurgical source and drain junction, which is defined by the effective length
4-2
Geometry Definition for C-V Modeling
(Lactive) and width (Wactive) when the gate to S/D region is at flat band voltage. Lactiveand Wactive are defined by Eqs. (4.2.1) through (4.2.4). (4.2.1)
Lactive = Ldrawn 2Leff

(4.2.2)
Wactive = Wdrawn 2Weff

(4.2.3)
Leff = DLC+
Llc Lwc Lwlc + Lwn + L ln Lwn L ln L W L W

(4.2.4)
Weff = DWC +
Wlc Wwc Wwlc + Wwn + W ln Wwn W ln L W L W
The meanings of DWC and DLC are different from those of Wint and Lint in the IV model. Lactive and Wactive are the effective length and width of the intrinsic device for capacitance calculations. Unlike the case with I-V, we assumed that these dimensions have no voltage bias dependence. The parameter Leff is equal to the source/drain to gate overlap length plus the difference between drawn and actual POLY CD due to processing (gate printing, etching and oxidation) on one side. Overall, a distinction should be made between the effective channel length extracted from the capacitance measurement and from the I-V measurement. Traditionally, the Leff extracted during I-V model characterization is used to gauge a technology. However this Leff does not necessarily carry a physical meaning. It is just a parameter used in the I-V formulation. This Leff is therefore very sensitive to the I-V equations used and also to the conduction characteristics of the LDD
4-3
Methodology for Intrinsic Capacitance Modeling
region relative to the channel region. A device with a large Leff and a small parasitic resistance can have a similar current drive as another with a smaller Leff but larger Rds. In some cases Leff can be larger than the polysilicon gate length giving Leff a dubious physical meaning. The Lactive parameter extracted from the capacitance method is a closer representation of the metallurgical junction length (physical length). Due to the graded source/ drain junction profile the source to drain length can have a very strong bias dependence. We therefore define Lactive to be that measured at gate to source/drain flat band voltage. If DWC, DLC and the newly-introduced length/ width dependence parameters (Llc, Lwc, Lwlc, Wlc, Wwc and Wwlc) are not specified in technology files, BSIM3v3.2.2 assumes that the DC bias-independent Leff and Weff (Eqs. (2.8.1) - (2.8.4)) will be used for C-V modeling, and DWC, DLC,Llc, Lwc, Lwlc, Wlc, Wwc and Wwlc will be set equal to the values of their DC counterparts (default values).
4.3 Methodology for Intrinsic Capacitance Modeling

4.3.1 Basic Formulation
To ensure charge conservation, terminal charges instead of the terminal voltages are used as state variables. The terminal charges Qg, Qb, Qs, and Qd are the charges associated with the gate, bulk, source, and drain termianls, respectively. The gate charge is comprised of mirror charges from these components: the channel inversion charge (Qinv), accumulation charge (Qacc) and the substrate depletion charge (Qsub).
4-4
The accumulation charge and the substrate charge are associated with the substrate while the channel charge comes from the source and drain terminals (4.3.1) Qg = (Qsub + Qinv + Qacc ) Qb = Qacc + Qsub Q = Q + Q s d inv The substrate charge can be divided into two components - the substrate charge at zero source-drain bias (Qsub0), which is a function of gate to substrate bias, and the additional non-uniform substrate charge in the presence of a drain bias (Qsub). Qg now becomes
Q g = (Qinv + Qacc + Qsub0 + Qsub )
(4.3.2)
The total charge is computed by integrating the charge along the channel. The threshold voltage along the channel is modified due to the nonuniform substrate charge by (4.3.3)
Vth ( y) = Vth (0) + (Abulk 1)Vy
(4.3.4)
Qc = Wactive qc dy = WactiveCox (Vgt AbulkVy )dy 0 0 Lactive Lactive Qg = Wactive qg dy = WactiveCox (Vgt + Vth VFB s Vy )dy 0 0 Lactive Lactive Qb = Wactive qbdy = WactiveCox Vth VFB s + Abulk 1 Vy dy 0 0
Lactive Lactive
) )
4-5
Substituting the following
dy =
dV y
and (4.3.5)
I ds =
Wactiveeff Cox A Vgt bulk Vds Vds = Wactiveeff Cox (Vgt AbulkVy )Ey Lactive 2
into Eq. (4.3.4), we have the following upon integration (4.3.6) 2 2 Abulk V ds Q c = W active L active C ox V gt Abulk V ds + Abulk 2 12 V gt V ds 2 2 V ds Abulk V ds + Q g = Q sub 0 + W active L active C ox V gt A 2 12 V gt bulk V ds 2 Q b = Q g Q c = Q sub + Q sub 0 + Q acc where
4-6
(4.3.7)
Q sub 0 = W active L active 2 si qN sub (2 B V bs ) 2 V ds 1 Abulk V + Abulk ( Abulk 1) Q sub = W active L active C ox ds A 2 12 V gt bulk V ds 2
The inversion charges are supplied from the source and drain electrodes such that Qinv = Qs + Qd. The ratio of Qd and Qs is the charge partitioning ratio. Existing charge partitioning schemes are 0/100, 50/50 and 40/60 (XPART = 0, 0.5 and 1) which are the ratios of Qd to Qs in the saturation region. We will revisit charge partitioning in Section 4.3.4. All capacitances are derived from the charges to ensure charge conservation. Since there are four terminals, there are altogether 16 components. For each component (4.3.8)
Cij =
Qi V j
where i and j denote the transistor terminals. In addition
C
i
ij
C
j
ij
=0
4.3.2 Short Channel Model

In deriving the long channel charge model, mobility is assumed to be constant with no velocity saturation. Therefore in saturation region (VdsVdsat), the carrier density at the drain end is zero. Since no channel length modulation is assumed, the channel charge will remain a constant throughout the saturation region. In essence, the channel charge in the
4-7
saturation region is assumed to be zero. This is a good approximation for long channel devices but fails when Leff < 2 m. If we define a drain bias, Vdsat,cv, in which the channel charge becomes a constant, we will find that Vdsat,cv in general is larger than Vdsat but smaller than the long channel Vdsat, given by Vgt/Abulk. However, in old long channel charge models, Vdsat,cv is set to Vgt/Abulk independent of channel length. Consequently, Cij/Leff has no channel length dependence (Eqs. (4.3.6), (4.37)). A pseudo short channel modification from the long channel has been used in the past. It involved the parameter Abulk in the capacitance model which was redefined to be equal to Vgt/Vdsat, thereby equating Vdsat,cv and Vdsat. This overestimated the effect of velocity saturation and resulted in a smaller channel capacitance. The difficulty in developing a short channel model lies in calculating the charge in the saturation region. Although current continuity stipulates that the charge density in the saturation region is almost constant, it is difficult to calculate accurately the length of the saturation region. Moreover, due to the exponentially increasing lateral electric field, most of the charge in the saturation region are not controlled by the gate electrode. However, one would expect that the total charge in the channel will exponentially decrease with drain bias. Experimentally, (4.3.9)
Vdsat ,iv < Vdsat ,cv < Vdsat ,iv
Lactive
V gsteff ,cv Abulk
and Vdsat,cv is modeled by the following
4-8
(4.3.10a)
V dsat,cv cdsat ,cv = V gsteff ,cv
CLE CLC Abulk 1 + L active
(4.3.10b)
Vgs Vth voffcv + Vgsteff,cv = noff nvt ln 1 exp noff nv t
Parameters noff and voffcv are introduced to better fit measured data above subthreshold regions. The parameter Abulk is substituted Abulk0 in the long channel equation by (4.3.11)
CLC CLE Abulk ' = Abulk 0 1 + L active

(4.3.11a)
K1ox Abulk = 1 + 2 V s bseff A0 Leff B0 1 + L +2 X X Weff '+B1 1 + KetaV bseff J dep eff
In (4.3.11), parameters CLC and CLE are introduced to consider channellength modulation.
4-9
4.3.3 Single Equation Formulation

Traditional MOSFET SPICE capacitance models use piece-wise equations. This can result in discontinuities and non-smoothness at transition regions. The following describes single-equation formulation for charge, capacitance and voltage modeling in capMod=2 and 3. (a) Transition from depletion to inversion region The biggest discontinuity is the inversion capacitance at threshold voltage. Conventional models use step functions and the inversion capacitance changes abruptly from 0 to Cox. Concurrently, since the substrate charge is a constant, the substrate capacitance drops abruptly to 0 at threshold voltage. Both of these effects can cause oscillation during circuit simulation. Experimentally, capacitance starts to increase almost quadratically at ~0.2V below threshold voltage and levels off at ~0.3V above threshold voltage. For analog and low power circuits, an accurate capacitance model around the threshold voltage is very important. The non-abrupt channel inversion capacitance and substrate capacitance model is developed from the I-V model which uses a single equation to formulate the subthreshold, transition and inversion regions. The new channel inversion charge model can be modified to any charge model by substituting Vgt with Vgsteff,cv as in the following
Q(Vgt ) = Q(Vgsteff,CV )
Capacitance now becomes
(4.3.12)
4-10
(4.3.13)
C(Vgt ) = C(Vgsteff,CV ) Vgsteff,CV Vgs,ds,bs
The inversion charge is always non-zero, even in the accumulation region. However, it decreases exponentially with gate bias in the subthreshold region. (b) Transition from accumulation to depletion region An effective flatband voltage VFBeff is used to smooth out the transition between accumulation and depletion regions. It affects the accumulation and depletion charges (4.3.14)
+ Vbseff 3 ; 3 = 0.02V
VFBeff = vfb 0.5 V3 + V3 + 4 3vfb

2
} where V = vfb V
3
gs
(4.3.15)
vfb= Vth s K1ox s Vbseff
In BSIM3v3.2.2, a bias-independent Vth is used to calculate vfb for capMod = 1, 2 and 3. For capMod = 0, Vfbcv is used instead (refer to the appendices).
Qacc = Wactive Lactive Cox VFBeff vfb

2 1ox
(4.3.16)
(4.3.17) K 1+ 1+ 4 Vgs VFBeff Vgsteff,CV Vbseff Qsub0 = WactiveLactive Cox 2 2 K1ox
4-11
(c) Transition from linear to saturation region An effective Vds, Vcveff, is used to smooth out the transition between linear and saturation regions. It affects the inversion charge. (4.3.18)
Vcveff = Vdsat,cv 0.5 V4 + V4 + 4 4Vdsat,cv

2
} whereV = V
4
dsat,cv
Vds 4; 4 = 0.02V
(4.3.19)
2 2 Abulk ' Vcveff Abulk ' Qinv = Wactive LactiveCox Vgsteff,cv Vcveff + Abulk ' 2 Vcveff 12Vgsteff ,cv 2
(4.3.20)
Qsub
2 ' ' A A V 1 ( ) 1 Abulk ' bulk bulk cveff = Wactive Lactive Cox Vcveff 2 ' A bulk Vcveff 12Vgsteff ,cv 2
Below is a list of all the three partitioning schemes for the inversion charge: (i) The 50/50 charge partition This is the simplest of all partitioning schemes in which the inversion charges are assumed to be contributed equally from the source and drain nodes.
4-12
(4.3.21)
2 Abulk ' 2 Vcveff Wactive Lactive Cox Abulk ' Qs = Qd = 0.5Qinv = Vgsteff,cv Vcveff + Abulk ' 2 2 Vcveff 12Vgsteff,cv 2
(ii) The 40/60 channel-charge partition This is the most physical model of the three partitioning schemes in which the channel charges are allocated to the source and drain terminals by assuming a linear dependence on the position y. (4.3.22)
y dy Q s = Wactive q c 1 L active 0 Lactive y Q = W dy d active q c L active 0
Lactive
(4.3.23)
Qs = 4 2 2 3 2 2 3 VgsteffCV VgsteffCV Abulk'Vcveff + VgsteffCV(Abulk'Vcveff ) (Abulk'Vcveff ) 3 3 15 A ' 2VgsteffCV bulk Vcveff 2 WactiveLactiveCox
2
(4.3.24)
Qd =
2 1 3 W 2 3 5 active L activeC ox Abulk' Vcveff gsteffcv V gsteff cv A bulk ' V cveff +V gsteff cv A bulk ' V cveff 2 V 3 5 Abulk' Vcveff 2Vgsteffcv 2
) (
(iii) The 0/100 Charge Partition In fast transient simulations, the use of a quasi-static model may result in a large unrealistic drain current spike. This partitioning scheme is developed to artificially suppress the drain current spike by assigning all inversion
4-13
Charge-Thickness Capacitance Model
charges in the saturation region to the source electrode. Notice that this charge partitioning scheme will still give drain current spikes in the linear region and aggravate the source current spike problem.
(4.3.25)
2 V Abulk ' Vcveff Abulk ' Vcveff gstefcvf gsteff,c + Qs = Wactive Lactive Cox Abulk ' 2 4 24 Vgsteff,c Vcveff gsteffcv 2
(4.3.26)
2 V Abulk ' Vcveff 3 Abulk ' Vcveff gsteffcv gsteff,c + Qd = Wactive Lactive Cox Abulk ' 2 4 V V 8 gsteffcv cveff gsteff,c 2
(d) Bias-dependent threshold voltage effects on capacitance Consistent Vth between DC and CV is important for acurate circuit simulation. capMod=1, 2 and 3 use the same Vth as in the DC model. Therefore, those effects, such as body bias, DIBL and short-channel effects are all explicitly considered in capacitance modeling. In deriving the capacitances additional differentiations are needed to account for the dependence of threshold voltage on drain and substrate biases.
4.4 Charge-Thickness Capacitance Model

Current MOSFET models in SPICE generally overestimate the intrinsic capacitance and usually are not smooth at Vfb and Vth. The discrepancy is more
4-14
pronounced in thinner Tox devices due to the assumption of inversion and accumulation charge being located at the interface. The charge sheet model or the band-gap(Eg)-reduction model of quantum effect [31] improves the
B
and thus
the Vth modeling but is inadequate for CV because they assume zero charge thickness. Numerical quantum simulation results in Figure 4-1 indicate the significant charge thickness in all regions of the CV curves [32]. This section describes the concepts used in the charge-thichness model (CTM). Appendix B lists all charge equations. A full report and anaylsis of the CTM model can be found in [32].
N orm alized C harge D istribution
F /c m ) Cgg (
0.15
E
2
1 .0 0 .8 0 .6 0 .4 0 .2 -4 -3 -2 -1 0 V g s (V ) 1
E A B D C
2 3
0.10
C A
T ox=30A N sub=5e17cm
-3
0.05 B 0.00 0 20 40
60
D epth (A )
Figure 4-1. Charge distribution from numerical quantum simulations show significant charge thickness at various bias conditions shown in the inset.
CTM is a charge-based model and therefore starts with the DC charge thicknss, XDC. The charge thicknss introduces a capacitance in series with Cox as illustrated in Figure 4-2, resulting in an effective Cox, Coxeff. Based on numerical selfconsistent solution of Shrodinger, Poisson and Fermi-Dirac equations, universal and analytical XDC models have been developed. Coxeff can be expressed as
4-15
(4.4.1)
C oxeff = C ox Ccen Cox + C cen
where
Ccen =
si
X DC
Vgs Vgse Poly depl.
Cox
Cacc
Cdep
Cinv
Figure 4-2. Charge-thickness capacitance concept in CTM. Vgse accounts for the poly depletion effect.
(i) XDC for accumulation and depletion The DC charge thickness in the accumulation and depletion regions can be expressed by [32] (4.4.2)
1 N X DC = Ldebye expacde sub16 3 2 10
0.25
Vgs Vbs V fb Tox
4-16
where XDC is in the unit of cm and (Vgs - Vbs - vfb) / Tox has a unit of MV/cm. The model parameter acde is introduced for better fitting with a default value of 1. For numerical statbility, (4.4.2) is replaced by (4.4.3) (4.4.3)
X DC = X max 1 X0 + 2
X 02 + 4 x X max
where
X 0 = X max X DC x
and Xmax=Ldebye/3;
x =10-3Tox.
(ii) XDC of inversion charge The inversion charge layer thichness [32] can be formulated as (4.4.4)
XDC = Vgsteff + 4(Vth vfb 2B ) 1+ 2Tox 1.9 10
7 0.7
[cm ]
Through vfb in (4.3.30), this equation is found to be applicable to N+ or P+ poly-Si gates as well as other future gate materials. Figure 4-3 illustrates the universality of (4.3.30) as verified by the numerical quantum simulations, where the x-axe
4-17
represents the boundary conditions (the average of the electric fields at the top and the bottom of the charge layers) of the Schrodinger and the Poisson equations.
Inversion C harge Thickness (A )
70 60 50 40 30 20 10 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Tox=20A Tox=70A
So lid - Nsub=2e16cm O pen - Nsub=2e17cm +
-3 -3 -3
Tox=50A Tox=90A
- Nsub=2e18cm
M odel
(V gsteff+4(V th-V fb-2 f))/Tox (M V /cm )
Figure 4-3. For all Tox and Nsub, modeled inversion charge thickness agrees with numerical quantum simulations.
(iii) Body charge thichness in inversion In inversion region, the body charge thickness effect is accurately modeled by including the deviation of the surface potential
s
from 2 B [32] (4.4.5)
Vgsteff,cv Vgsteff,cv + 2K1ox 2B 1 = s 2B = t ln + 2 moin K 1ox t
where the model parameter moin (defaulting to 15) is introduced for better fit to different technologies. The inversion channel charge density is therefore derived as
qinv = Coxeff (Vgsteff,cv )
(4.4.6)
4-18
Extrinsic Capacitance
Figure 4-4 illustrates the universality of CTM model by compariing Cgg of a SiON/ Ta2O5/TiN gate stack structure with an equivalent Tox of 1.8nm between data, numerical quantum simulation and modeling [32].
10.0
Measured Q.M. simulation CTM
7.5
18A equivalent SiO2 thickness
Cgg (pF)
5.0
TiN 60A Ta2O5
2.5
8A SiON p-Si
0.0 -2 -1 0 1 2 3
Vgs (V)
Figure 4-4. Universality of CTM is demonstrated by modeling the Cgg of 1.8nm equivalent Tox NMOSFET with SiON/Ta2O5/TiN gate stack.
4.5 Extrinsic Capacitance

4.5.1 Fringing Capacitance
The fringing capacitance consists of a bias independent outer fringing capacitance and a bias dependent inner fringing capacitance. Only the bias independent outer fringing capacitance is implemented. Experimentally, it is virtually impossible to separate this capacitance with the overlap capacitance. Nonetheless, the outer fringing capacitance can be theoretically calculated by (4.5.1)
CF = 2 ox t poly ln 1 + T ox
4-19
where tpoly is equal to 4 10 7 m. CF is a model parameter.
4.5.2 Overlap Capacitance

An accurate model for the overlap capacitance is essential. This is especially true for the drain side where the effect of the capacitance is amplified by the transistor gain. In old capacitance models this capacitance is assumed to be bias independent. However, experimental data show that the overlap capacitance changes with gate to source and gate to drain biases. In a single drain structure or the heavily doped S/D to gate overlap region in a LDD structure the bias dependence is the result of depleting the surface of the source and drain regions. Since the modulation is expected to be very small, we can model this region with a constant capacitance. However in LDD MOSFETs a substantial portion of the LDD region can be depleted, both in the vertical and lateral directions. This can lead to a large reduction of overlap capacitance. This LDD region can be in accumulation or depletion. We use a single equation for both regions by using such smoothing parameters as Vgs,overlap and Vgd,overlap for the source and drain side, respectively. Unlike the case with the intrinsic capacitance, the overlap capacitances are reciprocal. In other words, Cgs,overlap = Csg,overlap and Cgd,overlap = Cdg,overlap. (i) Source Overlap Charge (4.5.2)
Qoverlap, s Wactive 4V CKAPPA 1 + 1 gs,overlap = CGS0 Vgs + CGS1Vgs Vgs,overlap 2 CKAPPA
4-20
(4.5.3)
1 2 Vgs,overlap = Vgs + 1 (Vgs + 1 ) + 41 , = 0.02V 1 2

where CKAPPA is a model parameter. CKAPPA is related to the average doping of LDD region by
CKAPPA = 2 si qN LDD 2 Cox
17
The typical value for NLDD is (ii) Drain Overlap Charge
5 10
cm-3.
(4.5.4)
Qoverlap, d W active 4V CKAPPA 1 + 1 gd , overlap = CGD 0 V gd + CGD1V gd V gd , overlap CKAPPA 2
(4.5.5)
V gd , overlap = 1 V gd + 1 2
(V
gd
2 , = 0.02V + 1 ) + 4 1 1
(iii) Gate Overlap Charge (4.5.6)

Qoverlap , g = (Qoverlap , d + Qoverlap , s + (CGB 0 Lactive ) V gb )
In the above expressions, if CGS0 and CGD0 (the overlap capacitances between the gate and the heavily doped source/drain regions, respectively) are not given, they are calculated according to the following CGS0 = (DLC*Cox) - CGS1 (if DLC is given and DLC > 0)
4-21
CGS0 = 0 (if the previously calculated CGS0 is less than 0) CGS0 = 0.6 Xj*Cox (otherwise) CGD0 = (DLC*Cox) - CGD1 (if DLC is given and DLC > CGD1/Cox) CGD0 = 0 (if previously calculated CDG0 is less than 0) CGD0 = 0.6 Xj*Cox (otherwise). CGB0 in Eqn. (4.5.6) is a model parameter, which represents the gate-tobody overlap capacitance per unit channel length.
4-22
CHAPTER 5: Non-Quasi Static Model
5.1 Background Information

As MOSFETs become more performance-driven, the need for accurate prediction of circuit performance near cut-off frequency or under very rapid transient operation becomes more essential. However, most SPICE MOSFET models are based on Quasi-Static (QS) assumptions. In other words, the finite charging time for the inversion layer is ignored. When these models are used with 40/60 charge partitioning, unrealistically drain current spikes frequently occur [33]. In addition, the inability of these models to accurately simulate channel charge re-distribution causes problems in fast switched-capacitor type circuits. Many Non-Quasi-Static (NQS) models have been published, but these models (1) assume, unrealistically, no velocity saturation and (2) are complex in their formulations with considerable simulation time.
5.2 The NQS Model

The NQS model has been re-implemented in BSIM3v3.2 to improve the simulation performance and accuracy. This model is based on the channel charge relaxation time approach. A new charge partitioning scheme is used, which is physically consistent with quasi-static CV model.
5-1
Model Formulation
5.3 Model Formulation

The channel of a MOSFET is analogous to a bias dependent RC distributed transmission line (Figure 5-1a). In the Quasi-Static (QS) approach, the gate capacitor node is lumped with both the external source and drain nodes (Figure 51b). This ignores the finite time for the channel charge to build-up. One NonQuasi-Static (NQS) solution is to represent the channel as n transistors in series (Figure 5-1c). This model, although accurate, comes at the expense of simulation time. The NQS model in BSIM3v3.2.2 was based on the circuit of Figure 5-1d. This Elmore equivalent circuit models channel charge build-up accurately because it retains the lowest frequency pole of the original RC network (Figure 5-1a). The NQS model has two parameters as follows. The model flag, nqsMod, is now only an element (instance) parameter, no longer a model parameter. To turn on the NQS model, set nqsMod=1 in the instance statement. nqsMod defaults to zero with this model off.
Name
nqsMod elm
Function
Instance flag for the NQS model Elmore constant
Default
0 5
Unit
none none
Table 5-1. NQS model and instance parameters.
5-2
Model Formulation
Figure 5-1. Quasi-Static and Non-Quasi-Static models for SPICE analysis.
5.3.1 SPICE sub-circuit for NQS model

Figure 5-2 gives the RC-subcircuit of NQS model for SPICE implementation. An additional node, Qdef(t), is created to keep track of the amount of deficit/surplus channel charge necessary to reach the equilibrium based on the relaxation time approach. The bias-dependent resistance R (1/R=Gtau) can be determined from the RC time constant ( ). The current source icheq(t) results from the equilibrium channel charge, Qcheq(t). The capacitor C is multiplied by a scaling factor Cfact (with a typical value of
1 10
9
) to improve simulation accuracy. Qdef now becomes (5.3.1)
Qdef (t ) =Vdef (1 Cfact)
5-3
Model Formulation
Qdef
icheq(t)
Vdef C=1Cfact
Figure 5-2. NQS sub-circuit for SPICE implementation.
5.3.2 Relaxation time

The relaxation time
is modeled as two components:
drift
and
diff .
In
strong inversion region,
is determined by
drift ,
which, in turn, is
diff
determined by the Elmore resistance Relm; in subthreshold region, dominates.
is expressed by (5.3.2)
1 1 1 = + diff drift
Relm in strong inversoin is calculated from the channel resistance as (5.3.3)
Relm =
Leff
elm 0Qch
Leff
elm 0Qcheq
5-4
Model Formulation
where elm is the Elmore constant of the RC channel network with a theorectical value of 5. The quasi-static (or equilibrium) channel charge Qcheq(t), equal to Qinv of capMod=0, 1, 2 and 3, is used to approximate the actual channel charge Qch(t).
drift
is formulated as (5.3.4)
drift Relm CoxWeff Leff

diff
CoxWeff Leff
elm 0Qcheq
has the form of (5.3.5)
diff =
qLeff
16 0 kT
5.3.3 Terminal charging current and charge partitioning

Considering both the transport and charging component, the total current related to the terminals D, G and S can be written as (5.3.6)
iD,G,S (t ) = I D,G, S (DC) + Qd , g ,s (t ) t
Based on the relaxation time approach, the terminal charge and corresponding charging current can be formulated by
5-5
Model Formulation
(5.3.7)
Qdef (t ) = Qcheq (t ) Qch (t )
and (5.3.8a)
Qdef (t ) Qcheq (t ) Qdef (t ) = t t
(5.3.8b)
Qd , g , s (t ) t = D, G, S xpart Qdef (t )
where D,G,Sxpart are the NQS channel charge partitioning number for terminals D, G and S, respectively; Dxpart + Sxpart = 1 and Gxpart = -1. It is important for Dxpart and Sxpart to be consistent with the quasi-static charge partitioning number XPART and to be equal (Dxpart = Sxpart) at Vds=0 (which is not the case in the previous version), where the transistor operation mode changes (between forward and reverse modes). Based on this consideration, Dxpart is now formulated as (5.3.9)
D xpart = Qd Q = d Q d + Q s Qcheq
which is now bias dependent. For example, the derivities of Dxpart can be easily obtained based on the quasi-static results: (5.3.10)
dD xpart dV i
1 (Sxpart Cdi Dxpart Csi ) Qcheq
5-6
Model Formulation
where i represents the four terminals and Cdi and Csi are the intrinsic capacitances calculated from the quasi-static analysis. The corresponding values for Sxpart can be derived from the fact that Dxpart + Sxpart = 1. In the accumulation and depletion regions, Eq. (5.3.9) is simplified as If XPART < 0.5, Dxpart = 0.4; Else if XPART > 0.5, Dxpart = 0.0; Else Dxpart = 0.5;
5.3.4 Derivation of nodal conductances

This section gives some examples of how to derive the nodal conductances related to NQS for transient analysis. By noting that = RC, Gtau can be derived as (5.3.11)
Gtau =
C fact
is given by Eq. (5.3.2). Based on Eq. (5.3.8b), the self-conductance due
to NQS at the transistor node D can be derived as (5.3.12)
dDxpart dVd
(Gtau Vdef ) + Dxpart Vdef
dGtau dVd
The trans-conductance due to NQS on the node D relative to the node of Qdef can be derived as (5.3.13)
Dxpart Gtau
5-7
Model Formulation
Other conductances can also be obtained in a similar way.
5-8
CHAPTER 6: Parameter Extraction
Parameter extraction is an important part of model development. Many different extraction methods have been developed [23, 24]. The appropriate methodology depends on the model and on the way the model is used. A combination of a local optimization and the group device extraction strategy is adopted for parameter extraction.
6.1 Optimization strategy

There are two main, different optimization strategies: global optimization and local optimization. Global optimization relies on the explicit use of a computer to find one set of model parameters which will best fit the available experimental (measured) data. This methodology may give the minimum average error between measured and simulated (calculated) data points, but it also treats each parameter as a "fitting" parameter. Physical parameters extracted in such a manner might yield values that are not consistent with their physical intent. In local optimization, many parameters are extracted independently of one another. Parameters are extracted from device bias conditions which correspond to dominant physical mechanisms. Parameters which are extracted in this manner might not fit experimental data in all the bias conditions. Nonetheless, these extraction methodologies are developed specifically with respect to a given parameters physical meaning. If properly executed, it should, overall, predict
6-1
Extraction Strategies
device performance quite well. Values extracted in this manner will now have some physical relevance.
6.2 Extraction Strategies

Two different strategies are available for extracting parameters: the single device extraction strategy and group device extraction strategy. In single device extraction strategy, experimental data from a single device is used to extract a complete set of model parameters. This strategy will fit one device very well but will not fit other devices with different geometries. Furthermore, single device extraction strategy can not guarantee that the extracted parameters are physical. If only one set of channel length and width is used, parameters related to channel length and channel width dependencies can not be determined. BSIM3v3 uses group device extraction strategy. This requires measured data from devices with different geometries. All devices are measured under the same bias conditions. The resulting fit might not be absolutely perfect for any single device but will be better for the group of devices under consideration.
6.3 Extraction Procedure

6.3.1 Parameter Extraction Requirements
One large size device and two sets of smaller-sized devices are needed to extract parameters, as shown in Figure 6-1.
6-2
Extraction Procedure
Large W and L Orthogonal Set of W and L
Wmin L Lmin
Figure 6-1. Device geometries used for parameter extraction
The large-sized device (W 10m, L 10m) is used to extract parameters which are independent of short/narrow channel effects and parasitic resistance. Specifically, these are: mobility, the large-sized device threshold voltage VTideal, and the body effect coefficients K1 and K2 which depend on the vertical doping concentration distribution. The set of devices with a fixed large channel width but different channel lengths are used to extract parameters which are related to the short channel effects. Similarly, the set of devices with a fixed, long channel length but different channel widths are used to extract parameters which are related to narrow width
6-3
effects. Regardless of device geometry, each device will have to be measured under four, distinct bias conditions. (1) Ids vs. Vgs @ Vds = 0.05V with different Vbs. (2) Ids vs. Vds @ Vbs = 0V with different Vgs. (3) Ids vs. Vgs @ Vds = Vdd with different Vbs. (Vdd is the maximum drain voltage). (4) Ids vs. Vds @ Vbs = Vbb with different Vgs. (|Vbb| is the maximum body bias).
6.3.2 Optimization
The optimization process recommended is a combination of NewtonRaphson's iteration and linear-squares fit of either one, two, or three variables. This methodology was discussed by M. C. Jeng [18]. A flow chart of this optimization process is shown in Figure 6-2. The model equation is first arranged in a form suitable for Newton-Raphson's iteration as shown in Eq. (6.3.1): (6.3.1)
( m) (m) ( m) fexp(P 10, P 20, P 30 ) fsim( P 1 ,P 2 ,P 3 )=
fsim m fsim m fsim m P P P 1 + 2 + 3 P P P 1 2 3
The variable fsim() is the objective function to be optimized. The variable fexp() stands for the experimental data. P10, P20, a n d P30 represent the desired extracted parameter values. P1(m), P2(m) and P3(m) represent
parameter values after the mth iteration.
6-4
Initial Guess of Parameters P
Model Equations
Measured Data
Linear Least Squsre Fit Routine P
Pi
(m+1)
=P
(m) + i
P i
P P
i (m) i
<
no
yes STOP
Figure 6-2. Optimization flow.
To change Eq. (6.3.1) into a form that a linear least-squares fit routine can be used (i.e. in a form of y = a + bx1 + cx2), both sides of the Eq. (6.3.1) are divided by fsim / P1. This gives the change in P1, P1(m) , for the next iteration such that:
6-5
(6.3.2)
Pi( m +1) = Pi( m ) + Pi( m )

where i=1, 2, 3 for this example. The (m+1) parameter values for P2 and P3 are obtained in an identical fashion. This process is repeated until the incremental parameter change in parameter values Pi(m) are smaller than a pre-determined value. At this point, the parameters P1, P2, and P3 have been extracted.
6.3.3 Extraction Routine

Before any model parameters can be extracted, some process parameters have to be provided. They are listed below in Table 6-1: Input Parameters Names Tox Nch T Ldrawn Wdrawn Xj Physical Meaning Gate oxide thickness Doping concentration in the channel Temperature at which the data is taken Mask level channel length Mask level channel width Junction depth
Table 6-1. Prerequisite input parameters prior to extraction process.
The parameters are extracted in the following procedure. These procedures are based on a physical understanding of the model and based on local
6-6
optimization. (Note: Fitting Target Data refers to measurement data used for model extraction.) Step 1 Extracted Parameters & Fitting Target Data Vth0, K1, K2 Fitting Target Exp. Data: Vth(Vbs) Device & Experimental Data Large Size Device (Large W & L). Ids vs. Vgs @ Vds = 0.05V at Different Vbs Extracted Experimental Data Vth(Vbs)
Step 2 Extracted Parameters & Fitting Target Data 0,

U a, Ub, Uc
Devices & Experimental Data Large Size Device (Large W & L). Ids vs. Vgs @ Vds = 0.05V at Different Vbs
Fitting Target Exp. Data: Strong Inversion region Ids(Vgs, Vbs)
Step 3 Extracted Parameters & Fitting Target Data Lint, Rds(Rdsw , W, Vbs) Fitting Target Exp. Data: Strong Inversion region Ids(Vgs, Vbs) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vgs @ Vds = 0.05V at Different Vbs
6-7
Step 4 Extracted Parameters & Fitting Target Data Wint, Rds(Rdsw , W, Vbs) Fitting Target Exp. Data: Strong Inversion region Ids(Vgs, Vbs) Devices & Experimental Data One Set of Devices (Large and Fixed L & Different W). Ids vs. Vgs @ Vds = 0.05V at Different Vbs
Step 5 Extracted Parameters & Fitting Target Data Rdsw ,Prwb, Wr Fitting Target Exp. Data: Rds(Rdsw , W, Vbs) Devices & Experimental Data Rds(Rdsw , W, Vbs)
Step 6 Extracted Parameters & Fitting Target Data Dvt0, Dvt1, Dvt2, Nlx Fitting Target Exp. Data: Vth(Vbs, L, W) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Vth(Vbs, L, W)
6-8
Step 7 Extracted Parameters & Fitting Target Data Dvt0w, D vt1w, D vt2w Fitting Target Exp. Data: Vth(Vbs, L, W) Devices & Experimental Data One Set of Devices (Large and Fixed L & Different W). Vth(Vbs, L, W)
Step 8 Extracted Parameters & Fitting Target Data K3, K3b, W0 Fitting Target Exp. Data: Vth(Vbs, L, W) Devices & Experimental Data One Set of Devices (Large and Fixed L & Different W). Vth(Vbs, L, W)
Step 9 Extracted Parameters & Fitting Target Data Voff, Nfactor, Cdsc, Cdscb Fitting Target Exp. Data: Subthreshold region Ids(Vgs, Vbs) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vgs @ Vds = 0.05V at Different Vbs
Step 10 Extracted Parameters & Fitting Target Data Devices & Experimental Data
6-9
Cdscd Fitting Target Exp. Data: Subthreshold region Ids(Vgs, Vbs)
One Set of Devices (Large and Fixed W & Different L). Ids vs. Vgs @ Vbs = Vbb at Different Vds
Step 11 Extracted Parameters & Fitting Target Data dWb Fitting Target Exp. Data: Strong Inversion region Ids(Vgs, Vbs) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vgs @ Vds = 0.05V at Different Vbs
Step 12 Extracted Parameters & Fitting Target Data vsat, A0, Ags Fitting Target Exp. Data: Isat(Vgs, Vbs)/W A1, A2 (PMOS Only) Fitting Target Exp. Data Vasat(Vgs) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vds @ Vbs = 0V at Different Vgs
6-10
B0, B1 Fitting Target Exp. Data: Isat(Vgs, Vbs)/W
One Set of Devices (Large and Fixed L & Different W). Ids vs. Vds @ Vbs = 0V at Different Vgs
Step 14 Extracted Parameters & Fitting Target Data dWg Fitting Target Exp. Data: Isat(Vgs, Vbs)/W Devices & Experimental Data One Set of Devices (Large and Fixed L & Different W). Ids vs. Vds @ Vbs = 0V at Different Vgs
Step 15 Extracted Parameters & Fitting Target Data Pscbe1, Pscbe2 Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vds @ Vbs = 0V at Different Vgs
Fitting Target Exp. Data: Rout(Vgs, Vds)
Step 16 Extracted Parameters & Fitting Target Data Pclm, (Drout, Pdiblc1, Pdiblc2, L), Pavg Fitting Target Exp. Data: Rout(Vgs, Vds) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vds @ Vbs = 0V at Different Vgs
6-11
Step 17 Extracted Parameters & Fitting Target Data Drout, Pdibl1c, Pdiblc2 Fitting Target Exp. Data: (Drout, Pdiblc1, Pdiblc2, L) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). (Drout, Pdiblc1, Pdiblc2, L)
Step 18 Extracted Parameters & Fitting Target Data Pdibl1cb Fitting Target Exp. Data: (Drout, Pdiblc1, Pdiblc2, L, Vbs) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vgs @ fixed Vgs at Different Vbs
Step 19 Extracted Parameters & Fitting Target Data Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vgs @ Vds = Vdd at Different Vbs
dibl(Eta0, Etab, Dsub, L)

Fitting Target Exp. Data: Subthreshold region Ids(Vgs, Vbs)
6-12
Step 20 Extracted Parameters & Fitting Target Data Eta0, Etab, Dsub Fitting Target Exp. Data: dibl(Eta0, Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vgs @ Vds = Vdd at Different Vbs
Etab, L)
Step 21 Extracted Parameters & Fitting Target Data Keta Fitting Target Exp. Data: Isat(Vgs, Vbs)/W Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vds @ Vbs = Vbb at Different Vgs
Step 22 Extracted Parameters & Fitting Target Data 0, 1, 0 Fitting Target Exp. Data: Isub(Vgs, Vbs)/ W Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vds @ Vbs = Vbb at Different Vds
6-13
Notes on Parameter Extraction
6.4 Notes on Parameter Extraction

6.4.1 Parameters with Special Notes
Below is a list of model parameters which have special notes for parameter extraction.
Symbols used in SPICE Vth0 K1 K2 Vbm Nch gamma1 gamma2 Vbx Cgso Cgdo CF Description Threshold voltage for large W and L device @ Vbs=0V First order body effect coefficient Second order body effect coefficient Maximum applied body bias Channel doping concentration Body-effect coefficient near interface Body-effect coefficient in the bulk Vbs at which the depletion width equals xt Non-LDD source-gate overlap capacitance per channel length Non-Ldd drain-gate overlap capacitance per channel length Fringing field capacitance Default Value 0.7 (NMOS) -0.7 (PMOS) 0.5 0 -3 1.7E17 calculated calculated calculated calculated calculated calculated Unit V V1/2 none V 1/cm3 V1/2 V1/2 V F/m F/m F/m Notes nI-1 nI-2 nI-2 nI-2 nI-3 nI-4 nI-5 nI-6 nC-1 nC-2 nC-3
Table 6-2. Parameters with notes for extraction.
6-14
6.4.2 Explanation of Notes

nI-1. If Vth0 is not specified, it is calculated by
Vth 0 = VFB + s + K1 s
where the model parameter VFB=-1.0. If Vth0 is specified, VFB defaults to
VFB = Vth0 s K1 s
nI-2. If K1 and K2 are not given, they are calculated based on
K1 = 2 2 K 2 s Vbm
K2 =
2 s s Vbm s + Vbm
(1 2 )(
s Vbx s
where
s is
calculated by
Nch s = 2Vtm0 ln n i
Vtm 0 =
k BTnom q
6-15
Eg 0 T 21.5565981 ni = 1.45 10 nom exp 2Vtm 0 300 .15

1. 5 10
Eg 0
7.02 104 Tnom = 1.16 Tnom + 1108
where Eg0 is the energy bandgap at temperature Tnom. nI-3. If Nch is not given and 1 is given, Nch is calculated from
N ch =
1 2 C ox 2 2 q si
If both 1 and Nch are not given, Nch defaults to 1.7e23 m-3 and 1 is calculated from Nch. nI-4. If 1 is not given, it is calculated by
1 =
2q si Nch Cox
nI-5. If 2 is not given, it is calculated by
2 =
2q si N sub Cox
nI-6. If Vbx is not given, it is calculated by
6-16
nC-1. If Cgso is not given, it is calculated by if (dlc is given and is greater 0), Cgso = dlc * Cox - Cgs1 if (Cgso < 0) Cgso = 0 else Cgso = 0.6 Xj * Cox nC-2. If Cgdo is not given, it is calculated by if (dlc is given and is greater than 0), Cgdo = dlc * Cox - Cgd1 if (Cgdo < 0) Cgdo = 0 else Cgdo = 0.6 Xj * Cox
nC-3. If CF is not given then it is calculated usin by
2 ox 4 10 7 CF = ln 1 + Tox
6-17
6-18
CHAPTER 6: Parameter Extraction
Parameter extraction is an important part of model development. Many different extraction methods have been developed [23, 24]. The appropriate methodology depends on the model and on the way the model is used. A combination of a local optimization and the group device extraction strategy is adopted for parameter extraction.
6.1 Optimization strategy

There are two main, different optimization strategies: global optimization and local optimization. Global optimization relies on the explicit use of a computer to find one set of model parameters which will best fit the available experimental (measured) data. This methodology may give the minimum average error between measured and simulated (calculated) data points, but it also treats each parameter as a "fitting" parameter. Physical parameters extracted in such a manner might yield values that are not consistent with their physical intent. In local optimization, many parameters are extracted independently of one another. Parameters are extracted from device bias conditions which correspond to dominant physical mechanisms. Parameters which are extracted in this manner might not fit experimental data in all the bias conditions. Nonetheless, these extraction methodologies are developed specifically with respect to a given parameters physical meaning. If properly executed, it should, overall, predict
6-1
Extraction Strategies
device performance quite well. Values extracted in this manner will now have some physical relevance.
6.2 Extraction Strategies

Two different strategies are available for extracting parameters: the single device extraction strategy and group device extraction strategy. In single device extraction strategy, experimental data from a single device is used to extract a complete set of model parameters. This strategy will fit one device very well but will not fit other devices with different geometries. Furthermore, single device extraction strategy can not guarantee that the extracted parameters are physical. If only one set of channel length and width is used, parameters related to channel length and channel width dependencies can not be determined. BSIM3v3 uses group device extraction strategy. This requires measured data from devices with different geometries. All devices are measured under the same bias conditions. The resulting fit might not be absolutely perfect for any single device but will be better for the group of devices under consideration.
6.3 Extraction Procedure

6.3.1 Parameter Extraction Requirements
One large size device and two sets of smaller-sized devices are needed to extract parameters, as shown in Figure 6-1.
6-2
Large W and L Orthogonal Set of W and L
Wmin L Lmin
Figure 6-1. Device geometries used for parameter extraction
The large-sized device (W 10m, L 10m) is used to extract parameters which are independent of short/narrow channel effects and parasitic resistance. Specifically, these are: mobility, the large-sized device threshold voltage VTideal, and the body effect coefficients K1 and K2 which depend on the vertical doping concentration distribution. The set of devices with a fixed large channel width but different channel lengths are used to extract parameters which are related to the short channel effects. Similarly, the set of devices with a fixed, long channel length but different channel widths are used to extract parameters which are related to narrow width
6-3
effects. Regardless of device geometry, each device will have to be measured under four, distinct bias conditions. (1) Ids vs. Vgs @ Vds = 0.05V with different Vbs. (2) Ids vs. Vds @ Vbs = 0V with different Vgs. (3) Ids vs. Vgs @ Vds = Vdd with different Vbs. (Vdd is the maximum drain voltage). (4) Ids vs. Vds @ Vbs = Vbb with different Vgs. (|Vbb| is the maximum body bias).
6.3.2 Optimization
The optimization process recommended is a combination of NewtonRaphson's iteration and linear-squares fit of either one, two, or three variables. This methodology was discussed by M. C. Jeng [18]. A flow chart of this optimization process is shown in Figure 6-2. The model equation is first arranged in a form suitable for Newton-Raphson's iteration as shown in Eq. (6.3.1): (6.3.1)
( m) (m) ( m) fexp(P 10, P 20, P 30 ) fsim( P 1 ,P 2 ,P 3 )=
fsim m fsim m fsim m P P P 1 + 2 + 3 P P P 1 2 3
The variable fsim() is the objective function to be optimized. The variable fexp() stands for the experimental data. P10, P20, a n d P30 represent the desired extracted parameter values. P1(m), P2(m) and P3(m) represent
parameter values after the mth iteration.
6-4
Initial Guess of Parameters P
Model Equations
Measured Data
Linear Least Squsre Fit Routine P
Pi
(m+1)
=P
(m) + i
P i
P P
i (m) i
<
no
yes STOP
Figure 6-2. Optimization flow.
To change Eq. (6.3.1) into a form that a linear least-squares fit routine can be used (i.e. in a form of y = a + bx1 + cx2), both sides of the Eq. (6.3.1) are divided by fsim / P1. This gives the change in P1, P1(m) , for the next iteration such that:
6-5
(6.3.2)
Pi( m +1) = Pi( m ) + Pi( m )

where i=1, 2, 3 for this example. The (m+1) parameter values for P2 and P3 are obtained in an identical fashion. This process is repeated until the incremental parameter change in parameter values Pi(m) are smaller than a pre-determined value. At this point, the parameters P1, P2, and P3 have been extracted.
6.3.3 Extraction Routine

Before any model parameters can be extracted, some process parameters have to be provided. They are listed below in Table 6-1: Input Parameters Names Tox Nch T Ldrawn Wdrawn Xj Physical Meaning Gate oxide thickness Doping concentration in the channel Temperature at which the data is taken Mask level channel length Mask level channel width Junction depth
Table 6-1. Prerequisite input parameters prior to extraction process.
The parameters are extracted in the following procedure. These procedures are based on a physical understanding of the model and based on local
6-6
optimization. (Note: Fitting Target Data refers to measurement data used for model extraction.) Step 1 Extracted Parameters & Fitting Target Data Vth0, K1, K2 Fitting Target Exp. Data: Vth(Vbs) Device & Experimental Data Large Size Device (Large W & L). Ids vs. Vgs @ Vds = 0.05V at Different Vbs Extracted Experimental Data Vth(Vbs)
Step 2 Extracted Parameters & Fitting Target Data 0,

U a, Ub, Uc
Devices & Experimental Data Large Size Device (Large W & L). Ids vs. Vgs @ Vds = 0.05V at Different Vbs
Fitting Target Exp. Data: Strong Inversion region Ids(Vgs, Vbs)
Step 3 Extracted Parameters & Fitting Target Data Lint, Rds(Rdsw , W, Vbs) Fitting Target Exp. Data: Strong Inversion region Ids(Vgs, Vbs) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vgs @ Vds = 0.05V at Different Vbs
6-7
Step 4 Extracted Parameters & Fitting Target Data Wint, Rds(Rdsw , W, Vbs) Fitting Target Exp. Data: Strong Inversion region Ids(Vgs, Vbs) Devices & Experimental Data One Set of Devices (Large and Fixed L & Different W). Ids vs. Vgs @ Vds = 0.05V at Different Vbs
Step 5 Extracted Parameters & Fitting Target Data Rdsw ,Prwb, Wr Fitting Target Exp. Data: Rds(Rdsw , W, Vbs) Devices & Experimental Data Rds(Rdsw , W, Vbs)
Step 6 Extracted Parameters & Fitting Target Data Dvt0, Dvt1, Dvt2, Nlx Fitting Target Exp. Data: Vth(Vbs, L, W) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Vth(Vbs, L, W)
6-8
Step 7 Extracted Parameters & Fitting Target Data Dvt0w, D vt1w, D vt2w Fitting Target Exp. Data: Vth(Vbs, L, W) Devices & Experimental Data One Set of Devices (Large and Fixed L & Different W). Vth(Vbs, L, W)
Step 8 Extracted Parameters & Fitting Target Data K3, K3b, W0 Fitting Target Exp. Data: Vth(Vbs, L, W) Devices & Experimental Data One Set of Devices (Large and Fixed L & Different W). Vth(Vbs, L, W)
Step 9 Extracted Parameters & Fitting Target Data Voff, Nfactor, Cdsc, Cdscb Fitting Target Exp. Data: Subthreshold region Ids(Vgs, Vbs) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vgs @ Vds = 0.05V at Different Vbs
6-9
Cdscd Fitting Target Exp. Data: Subthreshold region Ids(Vgs, Vbs)
One Set of Devices (Large and Fixed W & Different L). Ids vs. Vgs @ Vbs = Vbb at Different Vds
Step 11 Extracted Parameters & Fitting Target Data dWb Fitting Target Exp. Data: Strong Inversion region Ids(Vgs, Vbs) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vgs @ Vds = 0.05V at Different Vbs
Step 12 Extracted Parameters & Fitting Target Data vsat, A0, Ags Fitting Target Exp. Data: Isat(Vgs, Vbs)/W A1, A2 (PMOS Only) Fitting Target Exp. Data Vasat(Vgs) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vds @ Vbs = 0V at Different Vgs
6-10
B0, B1 Fitting Target Exp. Data: Isat(Vgs, Vbs)/W
One Set of Devices (Large and Fixed L & Different W). Ids vs. Vds @ Vbs = 0V at Different Vgs
Step 14 Extracted Parameters & Fitting Target Data dWg Fitting Target Exp. Data: Isat(Vgs, Vbs)/W Devices & Experimental Data One Set of Devices (Large and Fixed L & Different W). Ids vs. Vds @ Vbs = 0V at Different Vgs
Step 15 Extracted Parameters & Fitting Target Data Pscbe1, Pscbe2 Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vds @ Vbs = 0V at Different Vgs
Fitting Target Exp. Data: Rout(Vgs, Vds)
Step 16 Extracted Parameters & Fitting Target Data Pclm, (Drout, Pdiblc1, Pdiblc2, L), Pavg Fitting Target Exp. Data: Rout(Vgs, Vds) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vds @ Vbs = 0V at Different Vgs
6-11
Step 17 Extracted Parameters & Fitting Target Data Drout, Pdibl1c, Pdiblc2 Fitting Target Exp. Data: (Drout, Pdiblc1, Pdiblc2, L) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). (Drout, Pdiblc1, Pdiblc2, L)
Step 18 Extracted Parameters & Fitting Target Data Pdibl1cb Fitting Target Exp. Data: (Drout, Pdiblc1, Pdiblc2, L, Vbs) Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vgs @ fixed Vgs at Different Vbs
Step 19 Extracted Parameters & Fitting Target Data Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vgs @ Vds = Vdd at Different Vbs
dibl(Eta0, Etab, Dsub, L)

Fitting Target Exp. Data: Subthreshold region Ids(Vgs, Vbs)
6-12
Step 20 Extracted Parameters & Fitting Target Data Eta0, Etab, Dsub Fitting Target Exp. Data: dibl(Eta0, Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vgs @ Vds = Vdd at Different Vbs
Etab, L)
Step 21 Extracted Parameters & Fitting Target Data Keta Fitting Target Exp. Data: Isat(Vgs, Vbs)/W Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vds @ Vbs = Vbb at Different Vgs
Step 22 Extracted Parameters & Fitting Target Data 0, 1, 0 Fitting Target Exp. Data: Isub(Vgs, Vbs)/ W Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). Ids vs. Vds @ Vbs = Vbb at Different Vds
6-13
6.4 Notes on Parameter Extraction

6.4.1 Parameters with Special Notes
Below is a list of model parameters which have special notes for parameter extraction.
Symbols used in SPICE Vth0 K1 K2 Vbm Nch gamma1 gamma2 Vbx Cgso Cgdo CF Description Threshold voltage for large W and L device @ Vbs=0V First order body effect coefficient Second order body effect coefficient Maximum applied body bias Channel doping concentration Body-effect coefficient near interface Body-effect coefficient in the bulk Vbs at which the depletion width equals xt Non-LDD source-gate overlap capacitance per channel length Non-Ldd drain-gate overlap capacitance per channel length Fringing field capacitance Default Value 0.7 (NMOS) -0.7 (PMOS) 0.5 0 -3 1.7E17 calculated calculated calculated calculated calculated calculated Unit V V1/2 none V 1/cm3 V1/2 V1/2 V F/m F/m F/m Notes nI-1 nI-2 nI-2 nI-2 nI-3 nI-4 nI-5 nI-6 nC-1 nC-2 nC-3
Table 6-2. Parameters with notes for extraction.
6-14
6.4.2 Explanation of Notes

VFB = Vth0 s K1 s
K1 = 2 2 K 2 s Vbm
K2 =
2 s s Vbm s + Vbm
(1 2 )(
s Vbx s
where
s is
calculated by
Vtm 0 =
k BTnom q
6-15
Eg 0 T 21.5565981 ni = 1.45 10 nom exp 2Vtm 0 300 .15

1. 5 10
Eg 0
7.02 104 Tnom = 1.16 Tnom + 1108
where Eg0 is the energy bandgap at temperature Tnom. nI-3. If Nch is not given and 1 is given, Nch is calculated from
N ch =
1 2 C ox 2 2 q si
1 =
2q si Nch Cox
2 =
2q si N sub Cox
6-16
nC-1. If Cgso is not given, it is calculated by if (dlc is given and is greater 0), Cgso = dlc * Cox - Cgs1 if (Cgso < 0) Cgso = 0 else Cgso = 0.6 Xj * Cox nC-2. If Cgdo is not given, it is calculated by if (dlc is given and is greater than 0), Cgdo = dlc * Cox - Cgd1 if (Cgdo < 0) Cgdo = 0 else Cgdo = 0.6 Xj * Cox
2 ox 4 10 7 CF = ln 1 + Tox
6-17
6-18
CHAPTER 7: Benchmark Test Results
A series of benchmark tests [26] have been performed to check the model robustness, accuracy and performance. Although not all the benchmark test results are included in this chapter, the most important ones are demonstrated.
7.1 Benchmark Test Types

Table 7-1 lists the various benchmark test conditions and associated figure number included in this section. Notice that for each plot, smooth transitions are apparent for current, transconductance, and source to drain resistance for all transition regions regardless of bias conditions.
Device Size W/L=20/5 W/L=20/5 W/L=20/0.5 W/L=20/0.5 W/L=20/5 W/L=20/5 W/L=20/0.5 W/L=20/0.5 W/L=20/5
Bias Conditions Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V; W/ L=20/5 Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V Gm/Ids vs. Vgs @ Vds=0.05V, 3-3V; Vbs=0V
Notes Log scale Linear scale Log scale Linear scale Log scale Linear scale Log scale Linear scale Linear scale
Figure Number 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9
7-1
Device Size W/L=20/0.5 W/L=20/5 W/L=20/0.5 W/L=20/0.5 W/L=20/5 W/L=20/0.5 W/L=20/0.5
Bias Conditions Gm/Ids vs. Vgs @ Vds=0.05V, 3-3V; Vbs=0V Gm/Ids vs. Vgs @ Vds=0.05V; Vbs=0V to 3.3V Gm/Ids vs. Vgs @ Vds=0.05V; Vbs=0V to 3.3V Ids vs. Vds @Vbs=0V; Vgs=0.5V, 0.55V, 0.6V Ids vs. Vds @Vbs=0V; Vgs=1.15V to 3.3V Ids vs. Vds @Vbs=0V; Vgs=1.084V to 3.3V Rout vs. Vds @ Vbs=0V; Vgs=1.084V to 3.3V
Notes Linear scale Linear scale Linear scale Linear scale Linear scale Linear scale Linear scale
Figure Number 7-10 7-11 7-12 7-13 7-14 7-15 7-16
Table 7-1. Benchmark test information.
7.2 Benchmark Test Results

All of the figures listed in Table 7-1 are shown below. Unless otherwise indicated, symbols represent measurement data and lines represent the results of the model. All of these plots serve to demonstrate the robustness and continuous behavior of the unified model expression for not only Ids but Gm, Gm/Ids, and Rout as well.
7-2
1.E-02 1.E-03 1.E-04 1.E-05 1.E-06 1.E-07 1.E-08 1.E-09 1.E-10 1.E-11 1.E-12 0.0 1.0 2.0 Vgs (V) 3.0 4.0 Solid lines: Model results Symbols: Exp.data W/L=20/5 Tox=9 nm Vbs=0V Vds=3.3V Vds=0.05V
Figure 7-1. Continuity from subthreshold to strong inversion (log scale).
Ids (A)
1.8E-03 1.6E-03 1.4E-03 1.2E-03

Ids (A)
1.0E-03 8.0E-04 6.0E-04 4.0E-04 2.0E-04 0.0E+00
Solid lines: Model result Symbols: Exp.data W/L=20/5 Tox=9 nm Vbs=0V
Vds=3.3V Vds=0.05V
0.0
1.0
2.0 Vgs (V)
3.0
4.0
Figure 7-2. Continuity from subthreshold to strong inversion (linear scale).
7-3
1.0E+00 1.0E-01 1.0E-02 1.0E-03 1.0E-04 1.0E-05 1.0E-06 1.0E-07 1.0E-08 1.0E-09 1.0E-10 1.0E-11 1.0E-12 0.0
Vds=3.3V
Ids (A)
Vds=0.05V
Solid lines: Model results Symbols: Exp. data W/L=20/0.5 Tox=9 nm Vbs=0V 1.0 2.0 Vgs (V) 3.0 4.0
Figure 7-3. Same as Figure 7-1 but for a short channel device.
1.0E-02 9.0E-03 8.0E-03 7.0E-03 6.0E-03 5.0E-03 4.0E-03 3.0E-03 2.0E-03 1.0E-03 0.0E+00
Ids (A)
Solid lines: Model results Symbols: Exp. data W/L=20/0.5 Tox=9 nm Vbs=0V
Vds=3.3V
Vds=0.05V 0.0 1.0 2.0 Vgs (V) 3.0 4.0
7-4
1.E-03 1.E-04 1.E-05 1.E-06

Ids (A)
Vbs=0V
Vbs=-3.3V
1.E-07 1.E-08 1.E-09 1.E-10 1.E-11 1.E-12 0.0 1.0 2.0 Vgs (V) 3.0 4.0 Solid lines: Model results Symbols: Exp. data W/L=20/5 Tox=9 nm Vds=0.05V
Figure 7-5. Subthreshold to strong inversion continuity as a function of Vbs.

7.E-05 Solid lines: Model results 6.E-05 Symbols: Exp. data W/L=20/5 5.E-05 Tox=9 nm Vds=0.05V 4.E-05 3.E-05 Vbs=0V 2.E-05 1.E-05 0.E+00 0.0 1.0 2.0 Vgs (V) 3.0 4.0 Vbs=-3.3V
Figure 7-6. Subthreshold to strong inversion continuity as a function of Vbs.
Ids (A)
7-5
1.E-03 1.E-04 1.E-05 1.E-06 Vbs=-3.3V Vbs=0V
Ids (A)
1.E-07 1.E-08 1.E-09 1.E-10 1.E-11 1.E-12 0.0 1.0 2.0 Vgs (V) 3.0 4.0 Solid lines: Model results Symbols: Exp. data W/L=20/0.5 Tox=9 nm Vds=0.05V
5.E-04 5.E-04 4.E-04 4.E-04 3.E-04 3.E-04 2.E-04 2.E-04 1.E-04 5.E-05 0.E+00 0.0 1.0 2.0 Vgs (V) 3.0 4.0 W/L=20/0.5 Tox=9 nm Vds=0.05V Vbs=0V Vbs=-3.3V
Ids (A)
7-6
30 Vds=3.3V 25 Solid lines: Model results Symbols: Exp. data W/L=20/5 Tox=9 nm Vbs=0V
gm/Ids (mho/A)
20 15 10 5 Vds=0.05V 0 0.0 1.0
2.0 Vgs (V)
3.0
4.0
Figure 7-9. Gm/Ids continuity from subthreshold to strong inversion regions.

30 25 W/L=20/0.5 Tox=9 nm Vbs=0V
gm/Ids (mho/A)
20 15 10 5 0 0.0 1.0 Vds=3.3V
Vds=0.05V
2.0 Vgs (V)
3.0
4.0
7-7
35 30 Solid lines: Model results Symbols: Exp. data W/L=20/5 Tox=9 nm Vds=0.05V
gm/Ids (mho/A)
25 20 15 10 5 Vbs=0V 0 0.0 1.0
Vbs=-3.3V
2.0 Vgs(V)
3.0
4.0
Figure 7-11. Gm/Ids continuity as a function of Vbs.
35 30 25
Gm/Id
20 15 10 5 0 0.0 1.0 Vbs=0V
Solid lines: Model results Symbols: Exp. data W/L=20/0.5 Tox=9 nm Vds=0.05V
Vbs=-1.98V
2.0 Vgs (V)
3.0
4.0
7-8
8.E-05 7.E-05 6.E-05 Solid lines: BSIM3v3 Dotted lines: BSIM3v2 W/L=20/0.5 Vgs =0.6V
Ids (A)
5.E-05 4.E-05 3.E-05 2.E-05 1.E-05
Vgs=0.55V Vgs=0.5V
0.E+00 0.0 0.2 0.4 Vds (V) 0.6 0.8
Figure 7-13. Comparison of Gds with BSIM3v2.

1.6E-03 1.4E-03 1.2E-03
Ids (A)
W/L=20/5 Tox=9 nm Vbs=0V
Vgs=3.3V
1.0E-03 8.0E-04 6.0E-04 4.0E-04 2.0E-04 Vgs=1.15V 0.0 0.5 1.0 1.5 2.0 Vds (V) 2.5 3.0 3.5
0.0E+00
Figure 7-14. Smooth transitions from linear to saturation regimes.
7-9
9.E-03 8.E-03 7.E-03 6.E-03
W/L=20/0.5 Tox=9nm Vbs=0V
Vgs=3.3V
Ids (A)
5.E-03 4.E-03 3.E-03 2.E-03 1.E-03 0.E+00 0.0 0.5 1.0 1.5 2.0 Vds (V) 2.5 3.0 3.5 Vgs=1.084V
2.0E+05 1.8E+05 1.6E+05 1.4E+05 1.2E+05 1.0E+05 8.0E+04 6.0E+04 4.0E+04 2.0E+04 0.0E+00 0.0
W/L=20/0.5 Tox=9 nm Vbs=0V
Vgs=1.084V
Rout (Ohm)
Vgs=3.3V
1.0
2.0 Vds (V)
3.0
4.0
Figure 7-16. Continuous and non-negative Rout behavior.
7-10
CHAPTER 8: Noise Modeling
8.1 Flicker Noise

8.1.1 Parameters
There exist two models for flicker noise modeling. One is called SPICE2 flicker noise model; the other is BSIM3 flicker noise model [35-36]. The flicker noise model parameters are listed in Table 8-1.
Symbols used in equation Noia Noib Noic Em Af Ef Kf Symbols used in SPICE noia noib noic em af ef kf Description Noise parameter A Noise parameter B Noise parameter C Saturation field Flick noise exponent Flicker noise frequency exponent Flicker noise coefficient Default (NMOS) 1e20 (PMOS) 9.9e18 (NMOS) 5e4 (PMOS) 2.4e3 (NMOS) -1.4e-12 (PMOS) 1.4e-12 4.1e7 1 1 0 Unit none none none V/m none none none
Table 8-1. Flicker noise model parameters.
8-1
Flicker Noise
8.1.2 Formulations
1.
For SPICE2 model (8.1)
Noise density =
K f I ds
2
af
Cox Leff f ef
where f is the frequency. For BSIM3 model If Vgs > Vth + 0.1
2.
(8.2)
Noise density = + q 2 kTeff I ds Cox Leff f
2 2 ef 14 Noia log N0 + 2 10 + Noib (N0 Nl ) + Noic N0 2 Nl 2 14 8 2 10 Nl + 2 10
Vtm I ds Lclm Weff Leff f ef 108
Noia + Noib Nl + Noic Nl
(N
+ 2 1014
where Vtm is the thermal voltage, eff is the effective mobiity at the given bias condition, and Leff and Weff are the effective channel length and width, respectively. The parameter N0 is the charge density at the source side given by (8.3)
N0 = Cox (Vgs Vth ) q
The parameter Nl is the charge density at the drain end given by
8-2
Flicker Noise
(8.4)
Nl =
Cox (Vgs Vth min(Vds ,Vdsat )) q
Lclm is the channel length reduction due to channel length modulation and
given by (8.5)
Vds Vdsat + Em (forVds > Vdsat) Litl log Litl Lclm = Esat ) 0 (otherwise Esat = 2 vsat eff
where
Litl = 3 X jTox
Otherwise (8.6)
Noise density=
Slimit Swi Slimit + Swi
Where, Slimit is the flicker noise calculated at Vgs = Vth + 0.1 and Swi is given by
8-3
Channel Thermal Noise
(8.7)
Noia Vtm Ids Swi = Weff Leff f ef 4 1036

2
8.2 Channel Thermal Noise

There also exist two models for channel thermal noise modeling. One is called SPICE2 thermal noise model. The other is BSIM3v3 thermal noise model. Each of these can be toggled through the model flag, noiMod.
1.
For SPICE2 thermal noise model (8.8)
8kBT (Gm + Gmbs + Gds ) 3

where Gm, Gmbs and Gds are the transconductances.
2.
For BSIM3v3 thermal noise model [37] (8.9)
4 k B T eff Leff
2
Q inv
Qinv is the inversion channel charge computed from the capacitance models (capMod = 0, 1, 2 or 3).
8-4
Noise Model Flag
8.3 Noise Model Flag

A model flag, noiMod, is used to select different combination of flicker and thermal noise models discussed above with possible optoins described in Table 82.
noimod flag 1 2 3 4 Thermal noise model SPICE2 BSIM3v3 SPICE2 BSIM3v3
Flicker noise model SPICE2 BSIM3v3 BSIM3v3 SPICE2
Table 8-2. noiMod flag for differnet noise models.
8-5
Noise Model Flag
8-6
CHAPTER 9: MOS Diode Modeling
9.1 Diode IV Model

The diode IV modeling now supports a resistance-free diode model and a currentlimiting feature by introducing a new model parameter ijth (defaulting to 0.1A). If ijth is explicitly specified to be zero, a resistance-free diode model will be triggered; otherwise two critical junction votages Vjsm for S/B diode and Vjdm for D/B diode will be computed from the value of ijth.
9.1.1 Modeling the S/B Diode

If the S/B saturation current Isbs is larger than zero, the following equations is used to calculate the S/B diode current Ibs. Case 1 - ijth is equal to zero: A resistance-free diode. (9.1)
Vbs + Ibs = Isbs exp NV 1 GminVbs tm

where
NV tm = NJ KbT q ;
NJ is a model parameter, known as the junction
emission coefficient. Case 2 - ijth is non-zero: Current limiting feature.
9-1
Diode IV Model
If Vbs < Vjsm (9.2)
Vbs Ibs = Isbs exp NV 1 + GminVbs tm

otherwise (9.3)
Ibs = ijth+
ijth+ Isbs (Vbs Vjsm) + GminVbs NV tm
with Vjsm computed by

ijth Vjsm = NVtm ln I + 1 sbs
The saturation current Isbs is given by (9.4)
I sbs = As J s + Ps J ssw
where Js is the junction saturation current density, AS is the source junction area, Jssw is the sidewall junction saturation current density, Ps is the perimeter of the source junction. Js and Jssw are functions of temperature and can be written as (9.5) Eg 0 Eg T + XTI ln T Vtm0 Vtm nom J s = J s 0 exp NJ
9-2
Diode IV Model
(9.6)
Eg 0 Eg T + XTI ln T Vtm0 Vtm nom J ssw = J s 0 sw exp NJ
The energy band-gap Eg0 and Eg at the nominal and operating temperatures are expressed by (9.7a) and (9.7b), repectively: (9.7a)
E g 0 = 1.16 7.02 10 4 Tnom Tnom + 1108
2
(9.7b)
E g = 1 .16 7 .02 10 T T + 1108
4 2
In the above derivatoins, Js0 is the saturation current density at Tnom. If Js0 is not given,
J s 0 = 1 10
4
A/m2. Js0sw is the sidewall saturation current density
at Tnom, with a default value of zero. If Isbs is not positive, Ibs is calculated by (9.8) I bs = Gmin Vbs
9.1.2 Modeling the D/B Diode

If the D/B saturation current Isbd is larger than zero, the following equations is used to calculate the D/B diode current Ibd. Case 1 - ijth is equal to zero: A resistance-free diode.
9-3
Diode IV Model
(9.9) Vbd + Ibd = I sbd exp NV 1 GminVbd tm Case 2 - ijth is non-zero: Current limiting feature. If Vbd < Vjdm
(9.10)
Vbd Ibd = I sbd exp NV 1 + GminVbd tm
otherwise (9.11)
I bd = ijth + ijth + I sbd (Vbd Vjdm) + GminVbd NVtm
with Vjdm computed by

ijth Vjdm = NVtm ln I + 1 sbd
The saturation current Isbd is given by (9.12)
I sbd = Ad J s + Pd J ssw
where Ad is the drain junction area and Pd is the perimeter of the drain junction. If Isbd is not positive, Ibd is calculated by (9.13) I bd = Gmin Vbd
9-4
MOS Diode Capacitance Model
9.1.3 Model Parameter Lists

The diode DC model parameters are listed in Table 9-1.
Symbols used in equation Symbols used in SPICE Description Default Unit
Js0 Js0sw NJ XTI ijth
js jssw nj xti ijth
Saturation current density Side wall saturation current density Emission coefficient Junction current temperature exponent coefficient Limiting current
1e-4 0 1 3.0 0.1
A/m2 A/m none none A
Table 9-1. MOS diode model parameters.
9.2 MOS Diode Capacitance Model

Source and drain junction capacitance can be divided into two components: the junction bottom area capacitance Cjb and the junction periphery capacitance Cjp. The formula for both the capacitances is similar, but with different model parameters. The equation of Cjb includes the parameters such as Cj, Mj, and Pb. The equation of Cjp includes the parameters such as Cjsw, Mjsw, Pbsw, Cjswg, Mjswg, and Pbswg.
9.2.1 S/B Junction Capacitance

The S/B junction capacitance can be calculated by If Ps > Weff (9.14)
Capbs = As C jbs + (Ps Weff )C jbssw + Weff C jbsswg
9-5
Otherwise (9.15)
Capbs = As C jbs + Ps C jbsswg
where Cjbs is the unit bottom area capacitance of the S/B junction, Cjbssw is the periphery capacitance of the S/B junction along the field oxide side, and Cjbsswg is the periphery capacitance of the S/B junction along the gate oxide side. If Cj is larger than zero, Cjbs is calculated by if Vbs < 0 (9.16)
Vbs C jbs = C j 1 P b
M j
otherwise
(9.17)
Vbs C jbs = C j 1 + M j P b
If Cjsw is large than zero, Cjbssw is calculated by if Vbs < 0
9-6
(9.18)
Vbs C jbssw = C jsw 1 P bsw
M jsw
otherwise (9.19)
Vbs C jbssw = C jsw 1 + M jsw P bsw
If Cjswg is larger than zero, Cjbsswg is calculated by if Vbs < 0

(9.20)
V C jbsswg = C jswg1 bs P bswg

otherwise
M jswg
(9.21)
V C jbsswg = C jswg1 + M jswg bs P bswg
9.2.2 D/B Junction Capacitance

The D/B junction capacitance can be calculated by
9-7
If Pd > Weff (9.22)

Capbd = Ad C jbd + (Pd Weff )C jbdsw + Weff C jbdswg
Otherwise (9.23)
Capbd = Ad C jbd + Pd C jbdswg
where Cjbd is the unit bottom area capacitance of the D/B junction, Cjbdsw is the periphery capacitance of the D/B junction along the field oxide side, and Cjbdswg is the periphery capacitance of the D/B junction along the gate oxide side. If Cj is larger than zero, Cjbd is calculated by if Vbd < 0 (9.24)
C jbd Vbd = Cj 1 P b
M j
otherwise
(9.25)
Vbd C jbd = C j 1 + M j P b
If Cjsw is large than zero, Cjbdsw is calculated by if Vbd < 0
9-8
(9.26)
Vbd C jbdsw = C jsw 1 P bsw otherwise
M jsw
(9.27)
Vbd C jbdsw = C jsw 1 + M jsw P bsw
If Cjswg is larger than zero, Cjbdswg is calculated by if Vbd < 0

(9.28)
V Cjbdswg = Cjswg1 bd P bswg

otherwise
M jswg
(9.29)
V C jbdswg = C jswg 1 + M jswg bd P bswg
9-9
9.2.3 Temperature Dependence of Junction Capacitance

The temperature dependence of the junction capacitance is modeled. Both zero-bias unit-area junction capacitance (Cj, Cjsw and Cjswg) and built-in potential of the junction (Pb, Pbsw and Pbswg) are temperature dependent and modeled in the following. For zero-bias junction capacitance: (9.30a)
C j (T ) = C j (Tnom ) (1 + tcj T )
(9.30b) C jsw (T ) = C jsw (Tnom ) (1 + tcjsw T ) (9.30c)

C jswg (T ) = C jswg (Tnom ) (1 + tcjswg T )
For the built-in potential: (9.31a) Pb (T ) = Pb (Tnom ) tpb T (9.31b)
P bsw(T ) = P bsw(Tnom ) tpbsw T

(9.31c)
P bswg (T ) = P bswg (Tnom ) tpbswg T

In Eqs. (9.30) and (9.31), the temperature difference is defined as
9-10
(9.32)
T = T Tnom
The six new model parameters in the above equations are described in Table 9-2.
9.2.4 Junction Capacitance Parameters

The following table give a full description of those model parameters used in the diode junction capacitance modeling.
Symbols used in equation Cj Mj Pb Cjsw
Symbols used in SPICE cj mj pb cjsw
Description Bottom junction capacitance per unit area at zero bias Bottom junction capacitance grading coefficient Bottom junction built-in potential Source/drain sidewall junction capacitance per unit length at zero bias Source/drain sidewall junction capacitance grading coefficient Source/drain side wall junction built-in potential Source/drain gate side wall junction capacitance per unit length at zero bias Source/drain gate side wall junction capacitance grading coefficient Source/drain gate side wall junction built-in potential Temperature coefficient of Pb Temperature coefficient of Pbsw
Default 5e-4 0.5 1.0 5e-10
Unit F/m2 none V F/m
Mjsw Pbsw Cjswg
mjsw pbsw cjswg
0.33 1.0 Cjsw
none V F/m
Mjswg
mjswg
Mjsw
none
Pbswg tpb tpbsw
pbswg tpb tpbsw
Pbsw 0.0 0.0
V V/K V/K
9-11
Symbols used in equation tpbswg tcj tcjsw tcjswg
Symbols used in SPICE tpbswg tcj tcjsw tcjswg
Description Temperature coefficient of Pbswg Temperature coefficient of Cj Temperature coefficient of Cjsw Temperature coefficient of Cjswg
Default 0.0 0.0 0.0 0.0
Unit V/K 1/K 1/K 1/K
Table 9-2. MOS Junction Capacitance Model Parameters.
9-12
APPENDIX A: Parameter List
A.1 Model Control Parameters

Symbols used in equation None None None None mobMod capMod nqsModa noiMod Symbols used in SPICE level version binUnit paramChk mobMod capMod nqsMod noiMod Description The model selector Model version selector Bining unit selector Parameter value check Mobility model selector Flag for capacitance models Flag for NQS model Flag for noise models Default 8 3.2 1 False 1 3 0 1 Unit none none none none none none none none Note
a. nqsMod is now an element (instance) parameter, no longer a model parameter.
A.2 DC Parameters
A-1
DC Parameters
Symbols used in equation Vth0
Symbols used in SPICE vth0
Description Threshold voltage @Vbs=0 for Large L.
Default 0.7 (NMOS) -0.7 (PMOS)
Unit V
Note nI-1
VFB K1 K2 K3 K3b W0 Nlx Vbm Dvt0 Dvt1 Dvt2 Dvt0w
vfb k1 k2 k3 k3b w0 nlx vbm dvt0 dvt1 dvt2 dvt0w
Flat-band voltage First order body effect coefficient Second order body effect coefficient Narrow width coefficient Body effect coefficient of k3 Narrow width parameter Lateral non-uniform doping parameter Maximum applied body bias in Vth calculation first coefficient of short-channel effect on Vth Second coefficient of shortchannel effect on Vth Body-bias coefficient of shortchannel effect on Vth First coefficient of narrow width effect on Vth for small channel length Second coefficient of narrow width effect on Vth for small channel length
Calculated 0.5 0.0 80.0 0.0 2.5e-6 1.74e-7 -3.0 2.2 0.53 -0.032 0
V V1/2 none none 1/V m m V none none 1/V 1/m
nI-1 nI-2 nI-2
Dvt1w
dvtw1
5.3e6
1/m
A-2
DC Parameters
Symbols used in equation Dvt2w
Symbols used in SPICE dvt2w
Description Body-bias coefficient of narrow width effect for small channel length Mobility at Temp = Tnom NMOSFET PMOSFET First-order mobility degradation coefficient Second-order mobility degradation coefficient Body-effect of mobility degradation coefficient
Default -0.032
Unit 1/V
Note
u0
670.0 250.0 2.25E-9 5.87E-19 mobMod =1, 2: -4.65e-11 mobMod =3: -0.046 8.0E4 1.0 0.0 0.0 0.0 -0.047 0.0 1.0
cm2/Vs m/V (m/V)2 m/V2
Ua Ub Uc
ua ub uc
1/V m/sec none 1/V m m 1/V 1/V none
sat A0 Ags B0 B1 Keta A1 A2
vsat a0 ags b0 b1 keta a1 a2
Saturation velocity at Temp = Tnom Bulk charge effect coefficient for channel length gate bias coefficient of Abulk Bulk charge effect coefficient for channel width Bulk charge effect width offset Body-bias coefficient of bulk charge effect First non-saturation effect parameter Second non-saturation factor
A-3
DC Parameters
Symbols used in equation Rdsw Prwb Prwg Wr Wint Lint dWg dWb Voff Nfactor Eta0 Etab Dsub Cit Cdsc
Symbols used in SPICE rdsw prwb prwg wr wint lint dwg dwb voff nfactor eta0 etab dsub cit cdsc
Description Parasitic resistance per unit width Body effect coefficient of Rdsw Gate bias effect coefficient of Rdsw Width Offset from Weff for Rds calculation Width offset fitting parameter from I-V without bias Length offset fitting parameter from I-V without bias Coefficient of Weffs gate dependence Coefficient of Weffs substrate body bias dependence Offset voltage in the subthreshold region at large W and L Subthreshold swing factor DIBL coefficient in subthreshold region Body-bias coefficient for the subthreshold DIBL effect DIBL coefficient exponent in subthreshold region Interface trap capacitance Drain/Source to channel coupling capacitance
Default 0.0 0 0 1.0 0.0 0.0 0.0 0.0 -0.08 1.0 0.08 -0.07 drout 0.0 2.4E-4
Unit -mWr V-1/2 1/V none m m m/V m/V1/2 V none none 1/V none F/m2 F/m2
Note
A-4
DC Parameters
Symbols used in equation Cdscb Cdscd Pclm Pdiblc1 Pdiblc2 Pdiblcb Drout
Symbols used in SPICE cdscb cdscd pclm pdiblc1 pdiblc2 pdiblcb drout
Description Body-bias sensitivity of Cdsc Drain-bias sensitivity of Cdsc Channel length modulation parameter First output resistance DIBL effect correction parameter Second output resistance DIBL effect correction parameter Body effect coefficient of DIBL correction parameters L dependence coefficient of the DIBL correction parameter in Rout First substrate current bodyeffect parameter Second substrate current bodyeffect parameter Gate dependence of Early voltage Effective Vds parameter poly gate doping concentration The first parameter of impact ionization current Isub parameter for length scaling The second parameter of impact ionization current
Default 0.0 0.0 1.3 0.39 0.0086 0 0.56
Unit F/Vm2 F/Vm2 none none none 1/V none
Note
Pscbe1 Pscbe2 Pvag Ngate 0 1 0
pscbe1 pscbe2 pvag delta ngate alpha0 alpha1 beta0
4.24E8 1.0E-5 0.0 0.01 0 0 0.0 30
V/m m/V none V cm-3 m/V 1/V V nI-3
A-5
C-V Model Parameters
Symbols used in equation Rsh Js0sw Js0 ijth
Symbols used in SPICE rsh jssw js ijth
Description Source drain sheet resistance in ohm per square Side wall saturation current density Source drain junction saturation current per unit area Diode limiting current
Default 0.0 0.0 1.0E-4 0.1
Unit / square A/m A/m2 A
Note
nI-3
A.3 C-V Model Parameters
Symbols used in equation Xpart CGS0
Symbols used in SPICE xpart cgso
Description Charge partitioning flag Non LDD region source-gate overlap capacitance per channel length Non LDD region drain-gate overlap capacitance per channel length Gate bulk overlap capacitance per unit channel length Bottom junction capacitance per unit area at zero bias Default 0.0 calculated Unit none F/m Note nC-1
CGD0
cgdo
calculated
F/m
nC-2
CGB0 Cj
cgbo cj
0.0 5.0e-4
F/m F/m2
A-6
C-V Model Parameters
Symbols used in equation Mj Mjsw
Symbols used in SPICE mj mjsw
Description Default Bottom junction capacitance grating coefficient Source/Drain side wall junction capacitance grading coefficient Source/Drain side wall junction capacitance per unit area Source/drain gate side wall junction capacitance grading coefficient Source/drain gate side wall junction capacitance grading coefficient Source/drain side wall junction built-in potential Bottom built-in potential Source/Drain gate side wall junction built-in potential Light doped source-gate region overlap capacitance Light doped drain-gate region overlap capacitance Coefficient for lightly doped region overlap capacitance Fringing field capacitance fringing field capacitance Constant term for the short channel model Exponential term for the short channel model 0.5 0.33 none Unit Note
Cjsw Cjswg
cjsw cjswg
5.E-10 Cjsw
F/m F/m
Mjswg
mjswg
Mjsw
none
Pbsw Pb Pbswg CGS1 CGD1 CKAPPA
pbsw pb pbswg cgs1 cgd1 ckappa
1.0 1.0 Pbsw 0.0 0.0 0.6
V V V F/m F/m V
Cf CLC CLE
cf clc cle
calculated 0.1E-6 0.6
F/m m none
nC-3
A-7
NQS Parameters
Symbols used in equation DLC DWC Vfbcv noff voffcv acde
Symbols used in SPICE dlc dwc vfbcv noff voffcv acde
Description Default Length offset fitting parameter from C-V Width offset fitting parameter from C-V Flat-band voltage parameter (for capMod=0 only) CV parameter in Vgsteff,CV for weak to strong inversion CV parameter in Vgsteff,CV for week to strong inversion Exponential coefficient for charge thickness in capMod=3 for accumulation and depletion regions Coefficient for the gate-bias dependent surface potential lint wint -1 1.0 0.0 1.0 Unit m m V none V m/V nC-4 nC-4 nC-4 Note
moin
moin
15.0
none
nC-4
A.4 NQS Parameters
Symbols Symbols used in used in Description equation SPICE Elm elm Elmore constant of the channel
Default 5
Unit none
Note
A-8
dW and dL Parameters
A.5 dW and dL Parameters
Symbols used in equation Wl Wln Ww Wwn Wwl Ll Lln Lw Lwn Lwl Llc
Symbols used in SPICE wl wln ww wwn wwl ll lln lw lwn lwl Llc
Description Coefficient of length dependence for width offset Power of length dependence of width offset Coefficient of width dependence for width offset Power of width dependence of width offset Coefficient of length and width cross term for width offset Coefficient of length dependence for length offset Power of length dependence for length offset Coefficient of width dependence for length offset Power of width dependence for length offset Coefficient of length and width cross term for length offset Coefficient of length dependence for CV channel length offset
Default 0.0 1.0 0.0 1.0 0.0 0.0 1.0 0.0 1.0 0.0 Ll
Unit mWln none mWwn none mWwn+Wln mLln none mLwn none mLwn+Lln mLln
Note
A-9
Temperature Parameters
Symbols used in equation Lwc
Symbols used in SPICE Lwc
Description Coefficient of width dependence for CV channel length offset Coefficient of length and widthdependence for CV channel length offset Coefficient of length dependence for CV channel width offset Coefficient of widthdependence for CV channel width offset Coefficient of length and widthdependence for CV channel width offset
Default Lw
Unit mLwn
Note
Lwlc
Lwlc
Lwl
mLwn+Lln
Wlc
Wlc
Wl
mWln
Wwc Wwlc
Wwc Wwlc
Ww Wwl
mWwn mWln+Wwn
A.6 Temperature Parameters
Symbols used in equation Tnom te
Symbols used in SPICE tnom
Description Temperature at which parameters are extracted Mobility temperature exponent
Default 27
Unit oC
Note
ute
-1.5
none
A-10
Symbols used in equation Kt1 Kt1l
Symbols used in SPICE kt1 kt1l
Description Temperature coefficient for threshold voltage Channel length dependence of the temperature coefficient for threshold voltage Body-bias coefficient of Vth temperature effect Temperature coefficient for Ua Temperature coefficient for Ub Temperature coefficient for Uc
Default -0.11 0.0
Unit V Vm
Note
Kt2 Ua1 Ub1 Uc1
kt2 ua1 ub1 uc1
0.022 4.31E-9 -7.61E18 mobMod=1, 2: -5.6E-11 mobMod=3: -0.056
none m/V (m/V)2 m/V2
1/V
At Prt At nj XTI
at prt at nj xti
Temperature coefficient for saturation velocity Temperature coefficient for Rdsw Temperature coefficient for saturation velocity Emission coefficient of junction Junction current temperature exponent coefficient
3.3E4 0.0 3.3E4 1.0 3.0
m/sec -m m/sec none none
A-11
Flicker Noise Model Parameters
Symbols used in equation tpb tpbsw tpbswg tcj tcjsw tcjswg
Symbols used in SPICE tpb tpbsw tpbswg tcj tcjsw tcjswg
Description Temperature coefficient of Pb Temperature coefficient of Pbsw Temperature coefficient of Pbswg Temperature coefficient of Cj Temperature coefficient of Cjsw Temperature coefficient of Cjswg
Default 0.0 0.0 0.0 0.0 0.0 0.0
Unit V/K V/K V/K 1/K 1/K 1/K
Note
A.7 Flicker Noise Model Parameters
Symbols used in equation Noia Noib Noic
Symbols used in SPICE noia noib noic
Description Noise parameter A Noise parameter B Noise parameter C
Default (NMOS) 1e20 (PMOS) 9.9e18 (NMOS) 5e4 (PMOS) 2.4e3 (NMOS) -1.4e12 (PMOS) 1.4e-12 4.1e7
Unit none none none
Note
Em
em
Saturation field
V/m
A-12
Process Parameters
Symbols used in equation Af Ef Kf
Symbols used in SPICE af ef kf
Description Flicker noise exponent Flicker noise frequency exponent Flicker noise coefficient
Default 1 1 0
Unit none none none
Note
A.8 Process Parameters
Symbols used in equation Tox Toxm Xj 1 2 Nch Nsub Vbx Xt
Symbols used in SPICE tox toxm xj gamma1 gamma2 nch nsub vbx xt
Description Gate oxide thickness Tox at which parameters are extracted Junction Depth Body-effect coefficient near the surface Body-effect coefficient in the bulk Channel doping concentration Substrate doping concentration Vbs at which the depletion region width equals xt Doping depth
Default 1.5e-8 Tox 1.5e-7 calculated calculated 1.7e17 6e16 calculated 1.55e-7
Unit m m m V1/2 V1/2 1/cm3 1/cm3 V m
Note
nI-3
nI-5 nI-6 nI-4
nI-7
A-13
Geometry Range Parameters
A.9 Geometry Range Parameters
Symbols used in equation Lmin Lmax Wmin Wmax binUnit
Symbols used in SPICE lmin lmax wmin wmax binunit
Description Minimum channel length Maximum channel length Minimum channel width Maximum channel width Bin unit scale selector
Default 0.0 1.0 0.0 1.0 1.0
Unit m m m m none
Note
A.10Model Parameter Notes

VFB = Vth0 s K1 s
K1 = 2 2 K 2 s Vbm
A-14
Model Parameter Notes
K2 =
2 s s Vbm s + Vbm
(1 2 )(
s Vbx s
where s is calculated by
Vtm 0 =
k BTnom q
1. 5 Eg 0 Tnom 21 . 5565981 ni = 1.45 10 exp 300 . 15 2 V tm 0 10
Eg 0 = 1.16
7.02 104 Tnom Tnom + 1108
where Eg0 is the energy bandgap at temperature Tnom. nI-3. If pscbe2 <= 0.0, a warning message will be given. If ijth < 0.0, a fatal error message will occur. If Toxm < = 0.0, a fatal error message will occur.
A-15
nI-4. If Nch is not given and 1 is given, Nch is calculated from

N ch =
1 C ox 2 q si
2
1 =
2q si Nch Cox
2 =
2q si N sub Cox
nC-1. If Cgso is not given, it is calculated by if (dlc is given and is greater 0), Cgso = dlc * Cox - Cgs1 if (Cgso < 0) Cgso = 0 else Cgso = 0.6 Xj * Cox nC-2. If Cgdo is not given, it is calculated by if (dlc is given and is greater than 0),
A-16
Cgdo = dlc * Cox - Cgd1 if (Cgdo < 0) Cgdo = 0 else Cgdo = 0.6 Xj * Cox

CF = 2 ox 4 10 7 ln 1 + Tox
nC-4. If (acde < 0.4) or (acde > 1.6), a warning message will be given. If (moin < 5.0) or (moin > 25.0), a warning message will be given. If (noff < 0.1) or (noff > 4.0), a warning message will be given. If (voffcv < -0.5) or (voffcv > 0.5), a warning message will be given.
A-17
A-18
APPENDIX B: Equation List
B.1 I-V Model

B.1.1 Threshold Voltage
Vth = Vth 0 ox + K1ox s Vbseff K 2 oxVbseff Tox Nlx + K1ox 1 + 1 s + (K 3 + K 3bVbseff ) s Weff '+W0 Leff Weff ' Leff Weff ' Leff DVT 0 w + exp 2 exp D D 1 1 VT w VT w 2ltw ltw
(Vbi s )
Leff Leff (Vbi s ) DVT 0 + exp 2 exp D D 1 1 VT VT 2lt lt Leff Leff + exp 2 exp D D Vds sub sub (Etao + EtabVbseff ) 2 l l to to
Vth0ox = Vth0 K1 s
K 1ox = K 1
Tox Toxm
K2ox = K2
Tox Toxm
B-1
I-V Model
lt =
siX dep / C ox (1 + D VT 2 V bseff )
ltw =
siX dep / C ox (1 + D VT 2 w V bseff )
lto = siX dep 0 / Cox

Xdep = 2si( s Vbseff ) qNch 2sis qNch
Xdep 0 =
(1=0.001)
Vbseff = Vbc + 0.5[Vbs Vbc 1 + (Vbs Vbc 1)2 41Vbc ]

2 K1 Vbc = 0.9 s 2 4K 2
Vbi = vt ln(
NchNDS ) ni 2
B.1.2 Effective (Vgs-Vth)
Vgsteff
Vgs Vth ) 2 n vt ln 1 + exp( 2 n vt = 2s Vgs Vth 2Voff exp( ) 1 + 2 n COX 2 n vt qsiNch
B-2
I-V Model
n = 1 + Nfactor
Cd + Cox
Leff Leff (Cdsc + CdscdVds + Cdscb Vbseff ) exp(DVT1 ) + 2 exp(DVT1 ) 2lt lt Cox
Cit Cox
Cd =
si Xdep
B.1.3 Mobility
For mobMod=1
eff =
o Vgsteff + 2Vth 2 Vgsteff + 2Vth 1 + (Ua + Uc Vbseff )( ) + Ub ( ) TOX TOX
For mobMod=2
eff =
o Vgsteff 2 Vgsteff 1 + (Ua + UcVbseff )( ) + Ub ( ) TOX TOX
For mobMod=3
eff =
o Vgsteff + 2Vth 2 Vgsteff + 2Vth 1 + [Ua ( ) + Ub ( ) ](1 + UcVbseff ) TOX TOX
B-3
I-V Model
B.1.4 Drain Saturation Voltage

For Rds > 0 or 1:
Vdsat
b b 2 4ac = 2a
a = A bulk 2WeffsatCoxR DS + (
1 1) A bulk
2 b = (Vgsteff + 2 vt )( 1) + A bulkE satL eff + 3 A bulk (Vgsteff + 2 vt )WeffsatCoxR DS
c = (Vgsteff + 2vt ) E satLeff + 2 (Vgsteff + 2vt ) 2 WeffsatCoxR DS

= A1Vgsteff + A2
For Rds = 0 and = 1:
Vdsat =
Esat Leff ( Vgsteff + 2 vt ) Abulk Esat Leff + (Vgsteff + 2 vt )
2 Leff A0Leff B0 K1ox 1 + Abulk = 1+ 1 AgsVgsteff Weff '+B1 1+ KetaV bseff 2 s Vbseff Leff + 2 XJ Xdep Leff + 2 XJ Xdep
B-4
I-V Model
Esat =
2sat eff
B.1.5 Effective Vds
Vdseff = Vdsat
1 Vdsat Vds + (Vdsat Vds )2 + 4Vdsat 2
B.1.6 Drain Current Expression
Ids =
Vds Vdseff Vds Vdseff Idso ( Vdseff ) 1 + 1 + RdsIdso( Vdseff ) V V A ASCBE 1+ Vdseff
WeffeffCoxVgsteff (1 Abulk Idso = Leff [1 + Vdseff
Vdseff )Vdseff 2(Vgsteff + 2vt ) / ( EsatLeff )]
VA = VAsat + (1 +
1 1 PvagVgsteff + )( ) 1 E satLeff VACLM VADIBLC
VACLM =
AbulkEsatLeff + Vgsteff (Vds Vdseff ) PCLMAbulkEsat litl
B-5
I-V Model
VADIBLC =
(Vgsteff + 2 vt ) AbulkVdsat 1 rout (1 + PDIBLCBVbseff ) AbulkVdsat + Vgsteff + 2vt
Leff Leff rout = PDIBLC1 exp( DROUT ) + 2 exp( DROUT ) + PDIBLC 2 2 lt 0 lt 0
1 VASCBE
Pscbe 2 Pscbe1 litl exp Vds Vdseff Leff
EsatLeff + Vdsat + 2 RDSsatCoxWeffVgsteff [1 VAsat =
AbulkVdsat ] 2(Vgsteff + 2vt )
2 / 1 + RDSsatCoxWeffAbulk
si Tox X j ox
litl =
B.1.7 Substrate Current
I sub =
0 + 1 Leff
Leff
(V
ds
0 V dseff )exp V V ds dseff
I ds 0 1 + R ds I ds 0 V dseff
V ds V dseff 1 + VA
B-6
I-V Model
B.1.8 Polysilicon Depletion Effect
2 Ngate qN poly X poly 1 poly = X poly E poly = 2 2 si
ox Eox = si E poly = 2q si Ngate polyV poly
Vgs VFB s = V poly + Vox
a( V gs VFB s V poly ) V poly = 0

2
a=
ox 2
2q si N gateTox
2
Vgs_ eff
2 2 2ox (Vgs VFB s ) q si NgateTox = VFB + s + 1 1+ 2 ox2 q si NgateTox
B.1.9 Effective Channel Length and Width

Leff = Ldrawn 2 dL
Weff = Wdrawn 2 dW
B-7
I-V Model
Weff ' = Wdrawn 2 dW '
dW = dW '+dWgVgsteff + dWb s Vbseff s dW ' = Wint + Wl Ww W + Wwn + W ln wl Wwn W ln L W L W
dL = Lint +
Ll L Lw + Lwn + L ln wl Lwn L ln W L L W
B.1.10Source/Drain Resistance
Rds =
Rdsw 1 + PrwgVgsteff + Prwb s Vbseff s
(10 W ')
6 eff
))
Wr
B.1.11Temperature Effects
Vth(T ) = Vth(Tnorm) + (KT1 + Kt1l / Leff + KT2Vbseff )(T / Tnorm 1)
o(T ) = o(Tnorm)(
T te ) Tnorm
vsat(T ) = vsat (Tnorm) AT(T / Tnorm 1)
B-8
Capacitance Model Equations
Rdsw ( T ) = Rdsw ( Tnorm ) + Pr t (
T Tnorm
1)
Ua ( T ) = Ua ( Tnorm) + Ua1( T / Tnorm 1)
Ub ( T ) = Ub ( Tnorm) + Ub1( T / Tnorm 1)
Uc ( T ) = Uc ( Tnorm ) + Uc1( T / Tnorm 1)
B.2 Capacitance Model Equations

B.2.1 Dimension Dependence
L active = L drawn 2L eff
Wactive = Wdrawn 2Weff
Leff = DLC +
Llc Lwc Lwlc + Lwn + L ln Lwn L ln L W L W
Weff = DWC+
Wlc Wwc Wwlc + Wwn + W ln Wwn W ln L W L W
B-9
B.2.2 Overlap Capacitance

B.2.2.1 Source Overlap Capacitance
(1) for capMod = 0
Qoverlap, s Wactive (2) for capMod = 1 If Vgs < 0

Q overlap , s W active = CGS 0 V gs +
= CGS0Vgs
4V gs CKAPPA CGS 1 1+ 1 2 CKAPPA
Else
Qoverlap, s Wactive
(3) for capMod = 2
= (CGS 0 + CKAPPA CGS1) V gs
Qoverlap,s Wactive
4V CKAPPA 1 + 1 gs,overlap = CGS0 Vgs + CGS 1Vgs Vgs,overlap 2 CKAPPA
1 2 , = 0.02 Vgs,overlap = Vgs + 1 (Vgs + 1 ) + 41 1 2
B-10
B.2.2.2 Drain Overlap Capacitance
(1) for capMod = 0
Qoverlap,d Wactive
= CGD0Vgd
(2) for capMod = 1 If Vgd < 0
Qoverlap,d Wactive
Else
= CGD0 Vgs +
CKAPPA CGD1 1 + 1 4Vgd 2 CKAPPA
Q overlap , d W active
(3) for capMod = 2
Qoverlap,d Wactive
= (CGD 0 + CKAPPA CGD1) V gd
CKAPPA 1+ 1 4Vgd,overlap = CGD 0 Vgd + CGD 1Vgd Vgd,overlap 2 CKAPPA
1 2 Vgd ,overlap = Vgd + 1 (Vgd + 1 ) + 4 1 , 1 = 0.02 2
B-11
B.2.2.3 Gate Overlap Charge
Qoverlap,g = Qoverlap,s + Qoverlap,d
B.2.3 Instrinsic Charges

(1) capMod = 0 a. Accumulation region (Vgs < Vfbcv + Vbs) Qg = Wactive LactiveCox (Vgs Vbs V fbcv )
Qsub = Qg
Qinv = 0 b. Subthreshold region (Vgs < Vth)
K Qsub0 = WactiveLactiveCox 1ox 2
4(V V V ) 1 + 1 + gs fbcv bs 2 K1ox
Qg = Qb
B-12
Qinv = 0 c. Strong inversion (Vgs > Vth)

Vdsat , cv = Vgs Vth Abulk '
CLC CLE Abulk ' = Abulk 0 1 + Leff
K1ox + Abulk0 = 1 2 V s bseff
A0 Leff B0 1 + L +2 X X Weff '+B1 1 + KetaV bseff J dep eff
Vth = V fbcv + s + K1ox s Vbseff (i) 50/50 Charge partition If Vds < Vdsat
2 Vds Abulk'Vds Qg = CoxWactiveLactive Vgs Vfbcv s + A 'V 2 12Vgs Vth bulk ds 2
B-13
Qinv = Wactive Lactive Cox [ Vgs Vth
Abulk ' Vds Abulk ' 2 Vds 2 + ] Abulk ' 2 12(Vgs Vth Vds ) 2
(1 Abulk ' )Vds (1 Abulk ' ) Abulk ' Vds 2 ] Qb = Wactive Lactive Cox [ Vfb Vth + s + Abulk ' 2 Vds ) 12(Vgs Vth 2
Abulk ' Vds Abulk ' 2 Vds 2 + Qs = Qd = 0.5Qinv = Wactive LactiveCox[Vgs Vth ] Abulk ' 2 12(Vgs Vth Vds) 2
otherwise
Qg = Wactive Lactive Cox (Vgs Vfb s
Vdsat ) 3
1 Qs = Qd = Wactive Lactive Cox (Vgs Vth ) 3
Qb = Wactive Lactive Cox (Vfb + s Vth +
(1 Abulk ' )Vdsat ) 3
(ii) 40/60 channel-charge Partition
B-14
if (Vds < Vdsat)
Qg = CoxWactive Lactive [ Vgs Vfb s
Vds + 2
Abulk ' Vds 2 ] Abulk ' Vds 12(Vgs Vth ) 2
Abulk ' Vds Abulk ' 2 Vds 2 + ] Abulk ' 2 12(Vgs Vth Vds ) 2
Qb = Wactive Lactive Cox [Vfb Vth + s +
(1 Abulk ' )Vds (1 Abulk ' ) Abulk ' Vds 2 ] Abulk ' 2 Vds ) 12(Vgs Vth 2
Qd = Wactive Lactive Cox (Vgs Vth )2 Abulk ' Vds(Vgs Vth ) ( Abulk ' Vds)2 + Abulk ' Vds [ Vgs Vth A ' 6 8 40 bulk Vds + A ' 2 2 (Vgs Vth bulk Vds)2 2
Qs = (Qg + Qb + Qd )
otherwise
Vdsat ) 3
B-15
Qd =
4 Wactive Lactive Cox (Vgs Vth ) 15
Qs = ( Qg + Qb + Q d )
(iii) 0/100 Channel-charge Partition if Vds < Vdsat
Qg = CoxWactive Lactive [ Vgs Vfb s
Vds + 2
Abulk ' Vds 2 ] Abulk ' Vds ) 12(Vgs Vth 2
Abulk ' Vds Abulk ' 2 Vds 2 + ] A ' 2 12(Vgs Vth bulk Vds ) 2
(1 Abulk ' )Vds (1 Abulk ' ) Abulk ' Vds 2 Qb = Wactive Lactive Cox [Vfb Vth + s + ] A ' 2 12(Vgs Vth bulk Vds) 2
B-16
Vgs Vth Abulk ' ( Abulk ' Vds ) 2 + Qd = Wactive Lactive Cox Vds A ' 2 4 24(Vgs Vth bulk Vds ) 2
Qs = (Qg + Qb + Qd ) otherwise
Vdsat ) 3
Qd = 0
Qs = (Q g + Qb )
(2) capMod = 1 The flat-band voltage Vfb is calculated from
V fb = Vth s K1ox s Vbseff
B-17
where the bias dependences of Vth given in Section B.1.1 are not considered in calculating Vfb for capMod = 1. if (Vgs < Vfb + Vbs+ Vgsteffcv)
Qg 1 = Wactive Lactive Cox Vgs Vfb Vbs Vgsteffcv else

Qg1 = WactiveLactiveCox
2 K1ox 1 + 1 + 4(Vgs V fb Vgsteff , CV Vbseff ) 2 2 K1ox
Qb 1 = Qg 1
Vdsat ,cv =
Vgsteffcv Abulk '
CLC CLE A bulk ' = A bulk 0 1 + L eff
K1ox + 1 Abulk0 = 2 V s bseff
A0 Leff B0 1 + L +2 X X Weff '+B1 1 + KetaV bseff J dep eff
B-18
V gs Vth voffcv + 1 exp V gsteff ,cv = noff nv t ln noff nv t
if (Vds <=Vdsat)
2 Abulk ' Vds Vds + Qg = Qg 1 + Wactive Lactive Cox Vgsteff cv Abulk ' 2 12 Vgsteff cv Vds 2
2 A A V 1 ' ' ( ) A 1 ' bulk bulk ds bulk Qb = Qb 1 + Wactive Lactive Cox Vds A ' 2 bulk Vds 12 Vgsteffcv 2 (i) 50/50 Channel-charge Partition
Qs = Qd =
W active L active C ox 2
2 2 A bulk ' V ds V gsteff cv A bulk ' V ds + A bulk ' 2 V ds 12 V gsteffcv 2
(ii) 40/60 Channel-charge partition
B-19
Qs =
Wactive Lactive Cox A ' 2 Vgsteff cv bulk Vds 2

2
4 2 2 2 3 Vgsteffcv 3 Vgstefcvf 2 ( Abulk ' Vds ) + Vgsteffcv ( Abulk ' Vds ) ( Abulk ' Vds ) 3 3 15
Qd = (Qg + Qb + Qs ) (iii) 0/100 Channel-charge Partition
2 V A V ' ( Abulk ' Vds gstefcv bulk ds ) + Qs = Wactive Lactive Cox Abulk ' 2 4 Vds 24 Vgsteffcv 2
Qd = (Qg + Qb + Qs ) if (Vds > Vdsat)
Vdsat Qg = Qg 1 + Wactive Lactive Cox Vgsteff cv 3
Qb = Qb 1 Wactive Lactive Cox
(V
gsteffcv
Vdsat
B-20
(i) 50/50 Channel-charge Partition
Qs = Qd =
Wactive Lactive Cox Vgsteff cv 3
(ii) 40/60 Channel-charge Partition
Qs =
2Wactive Lactive Cox Vgsteffcv 5
Qd = (Qg + Qb + Qs ) (iii) 0/100 Channel-charge Partition
Qs = Wactive Lactive Cox
2Vgstefcv 3
Qd = (Qg + Qb + Qs ) (3) capMod = 2 The flat-band voltage Vfb is calculated from
vfb = Vth s K1ox s Vbseff
B-21
where the bias dependences of Vth given in Section B.1.1 are not considered in calculating Vfb for capMod = 2.
Q g = (Q inv + Q acc + Q sub 0 + Q sub )
Q b = Q acc + Q sub 0 + Q sub
Q inv = Q s + Q d
VFBeff = vfb 0.5 V3 + V3 2 + 4 3vfb
where V3 = vfb Vgb 3 ; 3 = 0.02
Qacc = Wactive Lactive Cox VFBeff vfb
Q sub0
2 V gs V FBeff V gsteff ,CV Vbseff ) K 1ox 1 + 1 + 4( = Wactive LactiveC ox 2 2 K 1ox
V dsat , cv =
Vgsteff,cv gstefcvf A bulk '
CLC CLE Abulk ' = Abulk 0 1 + L active
B-22
K1ox 1+ Abulk0 = 2 V s bseff
A0 Leff B0 1 + 1 + KetaV L +2 X X ' + W B 1 eff bseff J dep eff
Vgs Vth voffcv 1 exp + Vgsteff ,cv = noff nvt ln noff nv t
Vcveff = Vdsat,cv 0.5 V4 + V42 + 4 4Vdsat, cv
where V4 = Vdsat,cv Vds 4 ; 4 = 0.02
2 2 Abulk ' Vcveff Abulk ' Qinv = Wactive Lactive Cox Vgsteff cv Vcveff + Abulk ' 2 12 Vgsteff cv Vcveff 2
Qsub
2 1 A ' (1 Abulk ' )Abulk ' Vcveff bulk = Wactive Lactive Cox Vcveff A ' 2 12 Vgsteffcv bulk Vcveff 2
B-23
B.2.3.1 50/50 Charge partition

2 2 Abulk ' Vcveff Wactive Lactive Cox Abulk ' . Qinv = Qs = Qd = 05 V cv Vcveff + gsteff Abulk 2 2 12Vgsteffcv Vcveff 2
B.2.3.2 40/60 Channel-charge Partition

2 3 W 4 2 2 2 active LactiveC ox Abulk' Vcveff gsteffcv3 V gstefcvf A bulk ' V cveff + V gsteff A bulk ' V cveff gsteffc 2 V 3 3 15 Abulk ' 2Vgsteff cv Vcveff 2
Qs =
Qd =
2 3 Wactive LactiveCox 5 1 2 Abulk ' Vcveff Vgsteffcv3 V gsteff cv A bulk ' V cveff + V gsteff cv A bulk ' V cveff gsteffc 2 3 5 Abulk ' 2Vgsteffcv Vcveff 2
B.2.3.3 0/100 Charge Partition 2 V ' A V ' A V gsteffcv bulk cveff gstefcvf bulk cveff + Qs = Wactive Lactive Cox Abulk ' 4 2 24 Vgsteffcv Vcveff 2
2 V ' A V 3 ' A V bulk cveff gsteffcv bulk cveff + Qd = Wactive Lactive Cox Abulk ' 4 2 8 Vgsteffcv Vcveff 2
B-24
(3) capMod = 3 (Charge-Thickness Model) capMod = 3 also uses the bias-independent Vth to calculate Vfb as in capMod = 1 and 2.
vfb = Vth s K1ox s Vbseff
For the finite charge thickness (XDC) formulations, refer to Chapter 4.
Q acc = WLC oxeff V gbacc
V gbacc =
1 V0 + V02 + 4 3V fb 2
V0 = V fb + Vbseff Vgs 3
VFBeff = vfb 0.5 V3 + V3 2 + 4 3vfb
where V3 = vfb Vgb 3 ; 3 = 0.02
Coxeff =
Cox Ccen Cox + Ccen
C cen =
si
X DC
B-25
V gsteffCV (V gsteffCV + 2 K 1ox 2 B = s 2 B = t ln 2 moin K 1ox t
Qsub0 = WLC oxeff
K1ox 2
4(Vgs VFBeff Vbseffs Vgsteff,cv ) -1 + 1 + 2 K 1 ox
Vcveff = Vdsat
1 V1 + V12 + 4 3Vdsat 2
V1 = Vdsat Vds 3
V dsat =
V gsteff , cv Abulk '
2 2 Abulk ' Vcveff 1 Qinv = WLCoxeff Vgsteff,cv Abulk 'Vcveff + Abulk 'Vcveff 2 12 Vgsteff,cv 2
B-26
Qsub = WLC oxeff
2 1 A ' (1 Abulk ') Abulk 'Vcveff bulk Vcveff Abulk 'Vcveff 2 12 V gsteff ,cv 2
(i) 50/50 Charge Partition
2 2 ' WLC A V 1 oxeff bulk cveff Vgsteff,cv 1 Abulk'Vcveff + QS = QD = Qinv = Abulk'Vcveff 2 2 2 12 Vgsteff,cv 2
(ii) 40/60 Charge Partition
QS =
(Vgsteff,cv )3 4(Vgsteff,cv )2 Abulk'Vcveff + 2(Vgsteff,cv )(Abulk'Vcveff)2 2 (Abulk'Vcveff)3 3 3 15 Abulk'Vcveff 2Vgsteff ,cv 2 WLC oxeff
2
QD =
3 5 2 2 1 3 'Vcveff+(Vgsteff 'Vcveff) (A 'Vcveff) Vgsteff ,cv ,cv ,cv bulk bulk bulk ) ( ) A )(A (Vgsteff 3 5 'Vcveff A bulk 2Vgsteff ,cv 2 WLC oxeff
2
(iii) 0/100 Charge Partition
QS =
WLC oxeff 2
2 2 Abulk ' Vcveff 1 Vgsteff,cv + Abulk 'Vcveff Abulk 'Vcveff 2 12 Vgsteff,cv 2
B-27
QD =
WLCoxeff 2
2 Abulk ' 2 Vcveff 3 Vgsteff ,cv Abulk 'Vcveff + A 'V 2 4 Vgsteff ,cv bulk dveff 2
B-28
APPENDIX C: References
[1] G.S. Gildenblat, VLSI Electronics: Microstructure Science, p.11, vol. 18, 1989. [2] Muller and Kamins, Devices Electronics for Integrated Circuits, Second Edition. [3] J. H. Huang, Z. H. Liu, M. C. Jeng, K. Hui, M. Chan, P. K. Ko and C. Hu., BSIM3 Version 2.0 Users Manual, March 1994. [4] J.A. Greenfield and R.W. Dutton, "Nonplanar VLSI Device Analysis Using the Solution of Poisson's Equation," IEEE Trans. Electron Devices, vol. ED-27, p.1520, 1980. [5] H.S. Lee. "An Analysis of the Threshold Voltage for Short-Channel IGFET's," SolidState Electronics, vol.16, p.1407, 1973. [6] G.W. Taylor, "Subthreshold Conduction in MOSFET's," IEEE Trans. Electron Devices, vol. ED-25, p.337, 1978. [7] T. Toyabe and S. Asai, "Analytical Models of Threshold Voltage and Breakdown Voltage of Short-Channel MOSFET's Derived from Two-Dimensional Analysis," IEEE J. Solid-State Circuits, vol. SC-14, p.375, 1979. [8] D.R. Poole and D.L. Kwong, "Two-Dimensional Analysis Modeling of Threshold Voltage of Short-Channel MOSFET's," IEEE Electron Device Letter, vol. ED-5, p.443, 1984.
C-1
[9] J.D. Kendall and A.R. Boothroyd, "A Two-Dimensional Analytical Threshold Voltage Model for MOSFET's with Arbitrarily Doped Substrate," IEEE Electron Device Letter, vol. EDL-7, p.407, 1986. [10] Z.H. Liu, C. Hu, J.H. Huang, T.Y. Chan, M.C. Jeng, P.K. Ko, and Y.C. Cheng, "Threshold Voltage Model For Deep-Submicrometer MOSFETs," Electron Devices, vol. 40, pp. 86-95, Jan., 1993. [11] Y.C. Cheng and E.A. Sullivan, "Effect of Coulombic Scattering on Silicon Surface Mobility," J. Appl. Phys. 45, 187 (1974). [12] Y.C. Cheng and E.A. Sullivan, Surf. Sci. 34, 717 (1973). [13] A.G. Sabnis and J.T. Clemens, "Characterization of Electron Velocity in the Inverted <100> Si Surface," Tech. Dig.- Int. Electron Devices Meet., pp. 18-21 (1979). [14] G.S. Gildenblat, VLSI Electronics: Microstructure Science, p. 11, vol. 18, 1989. [15] M.S. Liang, J.Y. Choi, P.K. Ko, and C. Hu, "Inversion-Layer Capacitance and Mobility of Very Thin Gate-Oxide MOSFET's," IEEE Trans. Electron Devices, ED33, 409, 1986. [16] F. Fang and X. Fowler, "Hot-electron Effects and Saturation velocity in Silicon Inversion Layer," J. Appl. Phys., 41, 1825, 1969. [17] E. A. Talkhan, I. R. Manour and A. I. Barboor, "Investigation of the Effect of DriftField-Dependent Mobility on MOSFET Characteristics," Parts I and II. IEEE Trans. on Electron Devices, ED-19(8), 899-916, 1972. IEEE Tran.
C-2
[18] M.C. Jeng, "Design and Modeling of Deep-Submicrometer MOSFETs," Ph. D. Dissertation, University of California. [19] K.Y. Toh, P.K. Ko and R.G. Meyer, "An Engineering Model for Short-channel MOS Devices," IEEE Jour. of Solid-State Circuits, vol. 23, No. 4, Aug. 1988. [20] C. Hu, S. Tam, F.C. Hsu, P.K. Ko, T.Y. Chan and K.W. Kyle, "Hot-Electron Induced MOSFET Degradation - Model, Monitor, Improvement," IEEE Tran. on Electron Devices, Vol. 32, pp. 375-385, Feb. 1985. [21] F.C. Hsu, P.K. Ko, S. Tam, C. Hu and R.S. Muller, "An Analytical Breakdown Model for Short-Channel MOSFET's," IEEE Trans. on Electron Devices, Vol.ED29, pp. 1735, Nov. 1982 [22] H. J. Parke, P. K. Ko, and C. Hu, A Measurement-based Charge Sheet Capacitance Model of Short-Channel MOSFETs for SPICE, in IEEE IEDM 86, Tech. Dig., pp. 485-488, Dec. 1986. [23] M. Shur, T.A. Fjeldly, T. Ytterdal, and K. Lee, A Unified MOSFET Model, SolidState Electron., 35, pp. 1795-1802, 1992. [24] MOS9 Documentation. [25] C. F. Machala, P. C. Pattnaik and P. Yang, "An Efficient Algorithms for the Extraction of Parameters with High Confidence from Nonlinear Models," IEEE Electron Device Letters, Vol. EDL-7, no. 4, pp. 214-218, 1986. [26] Y. Tsividis and K. Suyama, MOSFET Modeling for Analog Circuit CAD: Problems and Prospects, Tech. Dig. vol. CICC-93, pp. 14.1.1-14.1.6, 1993.
C-3
[27] C. L. Huang and G. Sh. Gildenblat, "Measurements and Modeling of the n-channel MOSFET Inversion Layer Mobility and Device Characteristics in the Temperature Range 60-300 K," IEEE Tran. on Electron Devices, vol. ED-37, no.5, pp. 12891300, 1990. [28] D. S. Jeon, et al, IEEE Tran. on Electron Devices, vol. ED-36, no. 8, pp1456-1463, 1989. [29] S. M. Sze, Physics of Semiconductor Devices, 2nd Edition. [30] P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition. [31] R. Rios, N. D. Arora, C.-L. Huang, N. Khalil, J. Faricelli, and L. Gruber, A physical compact MOSFET model, including quantum mechanical effects, for statistical circuit design applications, IEDM Tech. Dig., pp. 937-940, 1995. [32] Weidong Liu, Xiaodong Jin, Ya-Chin King, and Chenming Hu, An efficient and accurate compact model for thin-oxide-MOSFET intrinsic capacitance considering the finite charge layer thickness, IEEE Trans. on Electron Devices, vol. ED-46, May, 1999. [33] Mansun Chan, et al, "A Relaxation time Approach to Model the Non-Quasi-Static Transient Effects in MOSFETs," IEDM, 1994 Technical Digest, pp. 169-172, Dec. 1994. [34] P. K. Ko, Hot-electron Effects in MOSFETs, Ph. D Dissertation, University of California, Berkeley, 1982
C-4
[35] K.K. Hung et al, A Physics-Based MOSFET Noise Model for Circuit Simulators, IEEE Transactions on Electron Devices, vol. 37, no. 5, May 1990. [36] K.K. Hung et al, A Unified Model for the Flicker Noise in Metal-Oxide Semiconductor Field-Effect Transistors, IEEE Transactions on Electron Devices, vol. 37, no. 3, March 1990. [37] T.P. Tsividis, Operation and Modeling of the MOS Transistor, McGraw-Hill, New York, 1987.
C-5
C-6
APPENDIX D: Model Parameter Binning
Below is the information on parameter binning regarding which model parameters can or cannot be binned. All those parameters which can be binned follow this implementation:
P=P 0 + PL P PP + W + Leff Weff Leff Weff
For example, for the parameter k1: P0 = k1, PL = lk1, PW = wk1, PP = pk1. binUnit is a bining unit selector. If binUnit = 1, the units of Leff and Weff used in the binning equation above have the units of microns; therwise in meters. For example, for a device with Leff = 0.5m and Weff = 10m. If binUnit = 1, the parameter values for vsat are 1e5, 1e4, 2e4, and 3e4 for vsat, lvsat, wvsat, and pvsat, respectively. Therefore, the effective value of vsat for this device is vsat = 1e5 + 1e4/0.5 + 2e4/10 + 3e4/(0.5*10) = 1.28e5 To get the same effective value of vsat for binUnit = 0, the values of vsat, lvsat, wvsat, and pvsat would be 1e5, 1e-2, 2e-2, 3e-8, respectively. Thus, vsat = 1e5 + 1e-2/0.5e6 + 2e-2/10e-6 + 3e-8/(0.5e-6 * 10e-6) = 1.28e5
D-1
Model Control Parameters
D.1 Model Control Parameters
Symbols used in equation None None None None mobMod capMod nqsMod noiMod
Symbols used in SPICE level version binUnit paramChk mobMod capMod nqsMod noiMod
Description The model selector Model version selector Bining unit selector Parameter value check Mobility model selector Flag for the short channel capacitance model Flag for NQS model Flag for Noise model
Can Be Binned? NO NO NO NO NO NO NO NO
D.2 DC Parameters
Symbols used in equation Vth0 VFB K1 K2
Symbols used in SPICE vth0 vfb k1 k2
Description Threshold voltage @Vbs=0 for Large L. Flat band voltage First order body effect coefficient Second order body effect coefficient
Can Be Binned? YES YES YES YES
D-2
DC Parameters
Symbols used in equation K3 K3b W0 Nlx Dvt0 Dvt1 Dvt2 Dvt0w
Symbols used in SPICE k3 k3b w0 nlx dvt0 dvt1 dvt2 dvt0w
Description Narrow width coefficient Body effect coefficient of k3 Narrow width parameter Lateral non-uniform doping parameter first coefficient of short-channel effect on Vth Second coefficient of shortchannel effect on Vth Body-bias coefficient of shortchannel effect on Vth First coefficient of narrow width effect on Vth for small channel length Second coefficient of narrow width effect on Vth for small channel length Body-bias coefficient of narrow width effect for small channel length Mobility at Temp = Tnom NMOSFET PMOSFET First-order mobility degradation coefficient Second-order mobility degradation coefficient
Can Be Binned? YES YES YES YES YES YES YES YES
Dvt1w
dvtw1
YES
Dvt2w
dvt2w
YES
u0
YES YES YES
Ua Ub
ua ub
D-3
DC Parameters
Symbols used in equation Uc sat A0 Ags B0 B1 Keta A1 A2 Rdsw Prwb Prwg Wr Wint Lint
Symbols used in SPICE uc vsat a0 ags b0 b1 keta a1 a2 rdsw prwb prwg wr wint lint
Description Body-effect of mobility degradation coefficient Saturation velocity at Temp = Tnom Bulk charge effect coefficient for channel length gate bias coefficient of Abulk Bulk charge effect coefficient for channel width Bulk charge effect width offset Body-bias coefficient of bulk charge effect First non0saturation effect parameter Second non-saturation factor Parasitic resistance per unit width Body effect coefficient of Rdsw Gate bias effect coefficient of Rdsw Width Offset from Weff for Rds calculation Width offset fitting parameter from I-V without bias Length offset fitting parameter from I-V without bias
Can Be Binned? YES YES YES YES YES YES YES YES YES YES YES YES YES NO NO
D-4
DC Parameters
Symbols used in equation dWg dWb Voff Nfactor Eta0 Etab Dsub Cit Cdsc Cdscb Cdscd Pclm Pdiblc1 Pdiblc2 Pdiblcb
Symbols used in SPICE dwg dwb voff nfactor eta0 etab dsub cit cdsc cdscb cdscd pclm pdiblc1 pdiblc2 pdiblcb
Description Coefficient of Weffs gate dependence Coefficient of Weffs substrate body bias dependence Offset voltage in the subthreshold region for large W and L Subthreshold swing factor DIBL coefficient in subthreshold region Body-bias coefficient for the subthreshold DIBL effect DIBL coefficient exponent in subthreshold region Interface trap capacitance Drain/Source to channel coupling capacitance Body-bias sensitivity of Cdsc Drain-bias sensitivity of Cdsc Channel length modulation parameter First output resistance DIBL effect correction parameter Second output resistance DIBL effect correction parameter Body effect coefficient of DIBL correction parameters
Can Be Binned? YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES
D-5
DC Parameters
Symbols used in equation Drout
Symbols used in SPICE drout
Description L dependence coefficient of the DIBL correction parameter in Rout First substrate current bodyeffect parameter Second substrate current bodyeffect parameter Gate dependence of Early voltage Effective Vds parameter poly gate doping concentration The first parameter of impact ionization current Isub parameter for length scaling The second parameter of impact ionization current Source drain sheet resistance in ohm per square Source drain junction saturation current per unit area Diode limiting current
Can Be Binned? YES
Pscbe1 Pscbe2 Pvag Ngate 0 1 0 Rsh Js0 ijth
pscbe1 pscbe2 pvag delta ngate alpha0 alpha1 beta0 rsh js ijth
YES YES YES YES YES YES YES YES NO NO NO
D-6
AC and Capacitance Parameters
D.3 AC and Capacitance Parameters
Symbols used in equation Xpart CGS0
Symbols used in SPICE xpart cgso
Description Charge partitioning rate flag Non LDD region source-gate overlap capacitance per channel length Non LDD region drain-gate overlap capacitance per channel length Gate bulk overlap capacitance per unit channel length Bottom junction per unit area Bottom junction capacitance grating coefficient Source/Drain side junction capacitance grading coefficient Source/Drain side junction capacitance per unit area Bottom built-in potential Source/Drain side junction built-in potential Light doped source-gate region overlap capacitance Light doped drain-gate region overlap capacitance
Can Be Binned? NO NO
CGD0
cgdo
NO
CGB0 Cj Mj Mjsw
cgbo cj mj mjsw
NO NO NO NO
Cjsw Pb Pbsw CGS1 CGD1
cjsw pb pbsw cgs1 cgd1
NO NO NO YES YES
D-7
AC and Capacitance Parameters
Symbols used in equation CKAPPA
Symbols used in SPICE ckappa
Description Coefficient for lightly doped region overlap capacitance Fringing field capacitance fringing field capacitance Constant term for the short channel model Exponential term for the short channel model Length offset fitting parameter from C-V Width offset fitting parameter from C-V Flat-band voltage parameter (for capMod = 0 only) CV parameter in Vgsteff,CV for weak to strong inversion CV parameter in Vgsteff,CV for weak to strong inversion Exponential coefficient for charge thickness in capMod=3 for accumulation and depletion regions Coefficient for the gate-bias dependent surface potential
Can Be Binned? YES
Cf CLC CLE DLC DWC Vfbcv noff voffcv acde
cf clc cle dlc dwc vfbcv noff voffcv acde
YES YES YES YES YES YES YES YES YES
moin
moin
YES
D-8
NQS Parameters
D.4 NQS Parameters
Symbols Symbols used in used in Description equation SPICE Elm elm Elmore constant of the channel
Can Be Binned? YES
D.5 dW and dL Parameters
Symbols used in equation Wl Wln Ww Wwn Wwl Ll Lln
Symbols used in SPICE wl wln ww wwn wwl ll lln
Description Coefficient of length dependence for width offset Power of length dependence of width offset Coefficient of width dependence for width offset Power of width dependence of width offset Coefficient of length and width cross term for width offset Coefficient of length dependence for length offset Power of length dependence for length offset
Can Be Binned? NO NO NO NO NO NO NO
D-9
dW and dL Parameters
Symbols used in equation Lw Lwn Lwl Llc
Symbols used in SPICE lw lwn lwl Llc
Description Coefficient of width dependence for length offset Power of width dependence for length offset Coefficient of length and width cross term for length offset Coefficient of length dependence for CV channel length offset Coefficient of width dependence for CV channel length offset Coefficient of length and widthdependence for CV channel length offset Coefficient of length dependence for CV channel width offset Coefficient of widthdependence for CV channel width offset Coefficient of length and widthdependence for CV channel width offset
Can Be Binned? NO NO NO NO
Lwc
Lwc
NO
Lwlc
Lwlc
NO
Wlc
Wlc
NO
Wwc Wwlc
Wwc Wwlc
NO NO
D-10
D.6 Temperature Parameters
Symbols used in equation Tnom te Kt1 Kt1l
Symbols used in SPICE tnom
Description Temperature at which parameters are extracted Mobility temperature exponent Temperature coefficient for threshold voltage Channel length dependence of the temperature coefficient for threshold voltage Body-bias coefficient of Vth temperature effect Temperature coefficient for Ua Temperature coefficient for Ub Temperature coefficient for Uc Temperature coefficient for saturation velocity Temperature coefficient for Rdsw Emission coefficient Junction current temperature exponent coefficient
Can Be Binned? NO
ute kt1 kt1l
YES YES YES
Kt2 Ua1 Ub1 Uc1 At Prt nj XTI
kt2 ua1 ub1 uc1 at prt nj xti
YES YES YES YES YES YES YES YES
D-11
Flicker Noise Model Parameters
Symbols used in equation tpb tpbsw tpbswg tcj tcjsw tcjswg
Symbols used in SPICE tpb tpbsw tpbswg tcj tcjsw tcjswg
Description Temperature coefficient of Pb Temperature coefficient of Pbsw Temperature coefficient of Pbswg Temperature coefficient of Cj Temperature coefficient of Cjsw Temperature coefficient of Cjswg
Can Be Binned? NO NO NO NO NO NO
D.7 Flicker Noise Model Parameters
Symbols used in equation Noia Noib Noic Em Af
Symbols used in SPICE noia noib noic em af
Description Noise parameter A Noise parameter B Noise parameter C Saturation field Flicker noise exponent
Can Be Binned? NO NO NO NO NO
D-12
Process Parameters
Symbols used in equation Ef Kf
Symbols used in SPICE ef kf
Description Flicker noise frequency exponent Flicker noise parameter
Can Be Binned? NO NO
D.8 Process Parameters
Symbols used in equation Tox Toxm Xj 1 2 Nch Nsub Vbx Vbm Xt
Symbols used in SPICE tox toxm xj gamma1 gamma2 nch nsub vbx vbm xt
Description Gate oxide thickness Tox at which parameters are extracted Junction Depth Body-effect coefficient near the surface Body-effect coefficient in the bulk Channel doping concentration Substrate doping concentration Vbs at which the depletion region width equals xt Maximum applied body bias in Vth calculation Doping depth
Can Be Binned? NO NO YES YES YES YES YES YES YES YES
D-13
Geometry Range Parameters
D.9 Geometry Range Parameters
Symbols used in equation Lmin Lmax Wmin Wmax binUnit
Symbols used in SPICE lmin lmax wmin wmax binUnit
Description Minimum channel length Maximum channel length Minimum channel width Maximum channel width Binning unit selector
Can Be Binned? NO NO NO NO NO
D-14

BSIM3v3.2.2 MOSFET Model: Users' Manual

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BSIM3v3.2.2 MOSFET Model: Users' Manual

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BSIM3v3.2.

Technical Support: Dr. Weidong Liu: liuwd@bsim.eecs.berkeley.edu

Physics-Based Derivation of I-V Model 2-1

Unified I-V Model

BSIM3v3.2.2 Manual Copyright 1999 UC Berkeley

Non-Quasi Static Model

5.1 Background Information

BSIM3v3.2.2 Manual Copyright 1999 UC Berkeley

Benchmark Test Results

MOS Diode Modeling 9-1

9.2 MOS Diode Capacitance Model 9-5

BSIM3v3.2.2 Manual Copyright 1999 UC Berkeley

Junction Capacitance Parameters 9-11

A.1 Model Control Parameters A.3 C-V Model Parameters A-8

BSIM3v3.2.2 Manual Copyright 1999 UC Berkeley

Model Parameter Binning

D.1 Model Control Parameters

BSIM3v3.2.2 Manual Copyright 1999 UC Berkeley

BSIM3v3.2.2 Manual Copyright 1999 UC Berkeley

1.1 General Information

1.2 Organization of This Manual

BSIM3v3.2.2 Manual Copyright 1999 UC Berkeley

Organization of This Manual

BSIM3v3.2.2 Manual Copyright 1999 UC Berkeley

CHAPTER 2: Physics-Based Derivation of I-V Model

2.1 Non-Uniform Doping and Small Channel Effects on Threshold Voltage

BSIM3v3.2.2 Manual Copyright 1999 UC Berkeley

Non-Uniform Doping and Small Channel Effects on Threshold Voltage

Vth =VFB + s + s Vbs =VTideal+ s Vbs s

BSIM3v3.2.2 Manual Copyright 1999 UC Berkeley

Non-Uniform Doping and Small Channel Effects on Threshold Voltage

2.1.1 Vertical Non-Uniform Doping Effect

Figure 2-1. Actual substrate doping distribution and its approximation.

BSIM3v3.2.2 Manual Copyright 1999 UC Berkeley

Non-Uniform Doping and Small Channel Effects on Threshold Voltage

Vth = VTideal + K1 s Vbs s K 2Vbs

BSIM3v3.2.2 Manual Copyright 1999 UC Berkeley

Non-Uniform Doping and Small Channel Effects on Threshold Voltage

2.1.2 Lateral Non-Uniform Doping Effect

BSIM3v3.2.2 Manual Copyright 1999 UC Berkeley

Non-Uniform Doping and Small Channel Effects on Threshold Voltage

Due to the lateral non-uniform doping effect, Eq. (2.1.4) becomes:

BSIM3v3.2.2 Manual Copyright 1999 UC Berkeley

Non-Uniform Doping and Small Channel Effects on Threshold Voltage

2.1.3 Short Channel Effect

Vth = Vth 0 + K 1 s Vbs s K 2Vbs Nlx + K1 1 + 1 s Vth Leff

Vth = th (L)(2(Vbi s ) + Vds )

BSIM3v3.2.2 Manual Copyright 1999 UC Berkeley

Non-Uniform Doping and Small Channel Effects on Threshold Voltage

(2.1.14) Vbi = KBT N N ln( ch 2 d ) q ni

where Nd in is the source/drain doping concentration with a typical value of around

cm-3. The expression th(L) is a short channel effect

lt is referred to as the characteristic length and is given by (2.1.16)

Xdep is the depletion width in the substrate and is given by (2.1.17)

BSIM3v3.2.2 Manual Copyright 1999 UC Berkeley

Non-Uniform Doping and Small Channel Effects on Threshold Voltage

th ( L ) = Dvt 0 [exp( Dvt 1 L / 2lt ) + 2 exp( Dvt 1 L / lt )]

dibl ( L ) = [exp( Dsub L / 2lt 0 ) + 2 exp( Dsub L / lt 0 )]

Vth(Vds) = dibl( L)(Eta0 + EtabVbs)Vds

BSIM3v3.2.2 Manual Copyright 1999 UC Berkeley

Non-Uniform Doping and Small Channel Effects on Threshold Voltage

VTideal + K1 s Vbs K 2Vbs

VTideal + K1 s Vbs K 2Vbs