library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.

ALL; -- for making mux as a component-entity mux is port ( a,b,sel : in bit; x: out bit); end entity ; architecture mux of mux is begin x <= a when sel ='0' else b; end architecture; ---- for flipflop------as a component-entity ff is port ( d,clk : in bit; q : out bit); end entity; architecture ff of ff is begin process (clk) begin if (clk'event and clk='1') then q <= d; end if; end process; end architecture; ---- starting of shift register-----main code-entity circularshift is port ( clk, load : in bit; d : in bit_vector (0 to 3); q : buffer bit_vector (0 to 3)); end entity; architecture structural of circularshift is signal i : bit_vector(0 to 3); component mux is port (a,b,sel: in bit; x: out bit); end component; component ff is port (d,clk,sel :in bit; q :out bit); end component; begin mux1 mux2 mux3 mux4 dff1 dff2 dff3 dff4 : : : : : : : : mux port map (q(3) ,d(0),load,i(0)); mux port map (q(0) ,d(1),load,i(1)); mux port map (q(1) ,d(2),load,i(2)); mux port map (q(2) ,d(3),load,i(3)); ff port map (i(0) ,clk, q(0)); ff port map (i(1) ,clk, q(1)); ff port map (i(2) ,clk, q(2)); ff port map (i(3) ,clk, q(3));

end architecture;