LOW POWER DESIGN METHODOLOGIES edited by Jan M. Rabaey University California and, Massoud Pedram MM. Rbyam University of Southern California KLUWER ACADEMIC PUBLISHERS Boston / Dordrecht / LondonDistributors for North America: Kluwer Academic Publishers 101 Philip Drive Assinippi Parke ‘Norwell, Massachusetts 02061 USA Distributors for all other countries: Kluwer Academic Publishers Group Distribution Centre Post Office Box 322 3300 AH Dordrecht, THE NETHERLANDS Consulting Editor: Jonathan Allen, Massachusetts Institute of Technology ACALP. Catalogue record for this book is available from the Library of Congress. Copyright © 1996 by Kluwer Academic Publishers All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photo-copying, recording, or otherwise, without the prior written permission of the publisher, Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massachusetts 02061 Printed on acid-free paper. Printed in the United States of America Table of Contents ‘Table of Contents v Preface ix Author Index xi 1. Introduction 1 Jan M.Rabaey, Massoud Pedram and Paul Landman LL. Motivation. 1 1.2, Sources of Dissipation in Digital Integrated Cirewts. 5 13. Degrees of Freedom .. 14, Recurring Themes in Low-Power... 15. Emerging Low Power Approaches — An Overview 16, Summary, 2 it 1S PART I Technology and Circuit Design Levels 2. Device and Technology Impact on Low Power Electronics 21 Chenming Bu 2.1, Introduetion 7 21 22, Dynamic Dissipation in CMOS... 21 23. Bifects of and on Speed. a 2 24, Constraints on Reduction .. 2s 25, Transistor Sizing and Optimal Gate Oxide Thickness 26 26. Impact of Technology Scaling. 28 2.7, Technology and Device Innovations 31 28. Summary. 33vi Low Power Design Methodologies 3. Low Power Circuit Techniques 37 Christer Svensson and Dake Lin 3.1. Introduction. 3.2, Power Consumption in Circuits 33. Flip-flops and Latches. 34, Lotic. 3.5. High Capacitance Nodes: 36, Summary. 4, Energy-Recovery CMOS 65 William C. Athas 4.1. A Simple Example. . 6 4.2. Alook at some practical details. 2 43, Rotratile Logic =a) 44, Reversible Pipelines 79 45. High-Performance Approsches... 84 46. Summary. 94 5. Low Power Clock Distribution 101 Joe G. Xi and Wayne W-M. Dai 5.1. Power Dissipation in Clock Distribution ot 5.2. Single Driver vs Distributed Buffers, 13 5.3. Buffer and Device Sizing under Process Variations 108 54, Zero Skew vs, Tolerable Skew. 4 533, Chip and Package Co-Design of Clock NetWork evn U9 56, Summary... 123 ‘Table of Contents PART II Logic and Module Design Levels 6. Logic Synthesis for Low Power Massoud Pedram 6.1, Introduetion. 62. Power Estimation Techniques. 63. Power Minimization Techniques... 64, Concluding Remarks 7. Low Power Arithmetic Components ‘Thomas K. Callaway and Earl E. Swartslander Tk. Introd tion nnn 72. Circuit Design Sue . 73. adders. 7.4, Mulhiptiers 75. Division 76, Summary 8. Low Power Memory Design Kiyoh tro 8.1, Inwedetion 82. Sources and Reductions of Power Dissipation in Memory Subsystem. 83, Sources of Power Dissipation in DRAM and SRAM 84, Low Power DRAM Cirsus. 85, Low Power SRAM Circuits 129 129 132 156 161 161 1682 170 1186. 194 198 201