ACKNOWLEDGEMENT

It is with the profound feelings of gratitude I would like to express my thanks to my institution SJB Institute of Technology for providing excellent infrastructure for the successful completion of our project. I would like to express my profound grateful to his holiness Padmabhushan Sri Sri Sri Dr Balagangadharanatha Mahaswamiji for providing an opportunity to complete my academics in this auspicious college and provided an opportunity to present this project. I would also like to express my profound grateful to his holiness Reverend Sri Sri Prakashnath Swamiji Managing director for providing an opportunity to complete my academics in this auspicious college. I like to take immense pleasure in thanking Dr. Puttaraju, principal, SJB Institute of Technology, for giving me the best facilities which helped me in satisfactory completion of project work. I extend my immense pleasure in thanking Dr. Nagaraj K R., Head of the Department, Electronics and Communication Engineering, for providing me invaluable guidance for the project. My hearty thanks are also due towards my guide Dr. Rekha K R., Professor, Whose timely support and guidance helped me immensely in the completion of the project. I wish to express my heartfelt thanks to the project coordinator Mr. Bhaskar B., Department of Electronics and Communication, SJB Institute of Technology, for their valuable suggestions and cheerful encouragement to carry out my technical project. Lastly, I take this opportunity to extend my full hearted thanks, gratitude and respect to my parents, lecturers, librarian and all my friends, for giving me valuable advices and support at all times in all possible ways.

Regards PRADEEP .S (1JB12LVS11)

ABSTRACT

Multiplications are most basic and frequently used operations in a CPU. These operations also form the basis for other complex operations. With ever increasing need for faster clock frequency it becomes imperative to have faster arithmetic unit. In this work a new system of Mathematics Vedic Mathematics is used to implement operations. Vedic Mathematics is based on 16 formulas with the purpose of simplification of lengthy and cumbersome mathematics. Vedic mathematics contains multiple algorithms for one operation. In the current work these algorithms are evaluated for their suitability in binary arithmetic. Suitable algorithms are implemented for Multiplication, Squaring and cubing in Verilog. Multiplication, Squaring and cubing are further used in design of Sine and Cosine function implementations.

CONTENTS

Details
CHAPTER 1: INTRODUCTION

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1

CHAPTER 2: LITERATURE REVIEW 2.1 Array Multiplier 2.2 Wallace Tree Multiplier 2.3 Booth Multiplier 2.4 Problem Formulation 2.5 Objective

2 4 5 6 7 7

CHAPTER 3: VEDIC SUTRAS 3.1 Implementation of Square Algorithms 3.2 Implementation of Cube Algorithms 3.3 Types of Multiplier

8 9 12 14

CHAPTER 4: EXPERIMENTAL RESULT 4.1 Simulation Result of Square Algorithms 4.2 Comparison Result between Wallace Tree and Array Multiplier 4.3 Simulation Result of Cube Algorithms

16 16 17 18

CHAPTER 5: CONCLUSION AND FUTURE WORK

19

REFERENCES APPENDIX 1

20 21

LIST OF FIGURES

Figures
2.1 4x4 Array Multiplier 2.2 4x4 Wallace Tree Multiplier 2.3 Booth Block Diagram 3.1 Block Diagram of Square Architecture 3.2 Block Diagram of Cube Architecture 4.1 Simulation Waveform of Square Algorithm using Wallace Tree Multiplier 4.2 Timing Constraints of Square Algorithm using Wallace Tree Multiplier 4.3 Simulation Waveform of Square Algorithm using Wallace Tree Multiplier 4.4 Timing Constraints of Square Algorithm using Wallace Tree Multiplier 4.5 Simulation Waveform of Square Algorithm using Wallace Tree Multiplier 4.6 Timing Constraints of Square Algorithm using Wallace Tree Multiplier

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5 6 7 11 13 16 16 17 17 18 18

APPENDIX 1
Source Code
Top level module for square algorithm module squaring(x,xsquare); output [15:0]xsquare; input [7:0] x; wire [7:0]asq; wire [7:0]bsq; wire [7:0]ab; wire [8:0]tab; wire [15:0]sasq; wire [12:0]stab; multiplier w1(x[7:4],x[7:4],asq); multiplier w2(x[7:4],x[3:0],ab); multiplier w3(x[3:0],x[3:0],bsq); assign tab = ab<<1; assign sasq = asq<<8; assign stab = tab<<4; assign xsquare = sasq+stab+bsq; endmodule Module for array multiplier module arraymultiplier (A,B,product); input [3:0]A; input [3:0]B; output [7:0]product; wire [3:0] p0,p1,p2,p3; partial_product pa(A,B,p0,p1,p2,p3); arrayadder par(p0,p1,p2,p3,product); endmodule Module for partial product adder using array structure module arrayadder(p0,p1,p2,p3,product); input [3:0] p0; input [3:0] p1; input [3:0] p2; input [3:0] p3; output [7:0] product; wire [11:0]s; wire [11:0]c; fulladder f0(c[0], s[0], p0[1], p1[0], 1'b0); fulladder f1(c[1], s[1], p2[0], p1[1], 1'b0); fulladder f2(c[2], s[2], p3[0], p2[1], 1'b0); fulladder f3(c[3], s[3], s[1], p0[2], c[0]); fulladder f4(c[4], s[4], s[2], p1[2], c[1]); fulladder f5(c[5], s[5], p3[1], p2[2], c[2]); fulladder f6(c[6], s[6], s[4], p0[3], c[3]);

fulladder f7(c[7], s[7], s[5], p1[3], c[4]); fulladder f8(c[8], s[8], p3[2], p2[3], c[5]); fulladder f9(c[9], s[9], s[7], 1'b0, c[6]); fulladder f10(c[10], s[10], s[8], c[9],c[7]); fulladder f11(c[11], s[11], p3[3], c[10],c[8]); assign product[0] = p0[0]; assign product[1] = s[0]; assign product[2] = s[3]; assign product[3] = s[6]; assign product[4] = s[9]; assign product[5] = s[10]; assign product[6] = s[11]; assign product[7] = c[11]; endmodule Module for Wallace tree multiplier module wallacetree (A,B,product); input [3:0]A; input [3:0]B; output [7:0]product; wire [3:0] p0,p1,p2,p3; partial_product pa(A,B,p0,p1,p2,p3); partialadder par(p0,p1,p2,p3,product); endmodule Module for partial product adder using Wallace tree structure module partialadder(p0,p1,p2,p3,product); input [3:0]p0; input [3:0]p1; input [3:0]p2; input [3:0]p3; output [7:0]product; wire [14:0]s; wire [14:0]c; halfadder h1(c[0], s[0], p0[1], p1[0]); fulladder f1(c[1], s[1], p0[2], p1[1], p2[0]); fulladder f2(c[2], s[2], p0[3], p1[2], p2[1]); fulladder f3(c[3], s[3], p1[3], p2[2], p3[1]); halfadder h2(c[4], s[4], p2[3], p3[2]); halfadder h3(c[5], s[5], s[1], c[0]); fulladder f4(c[6], s[6], p3[0], s[2], c[1]); halfadder h4(c[7], s[7], s[3], c[2]); halfadder h5(c[8], s[8], s[4], c[3]); halfadder h6(c[9], s[9], p3[3], c[4]); halfadder h7(c[10], s[10], s[6], c[5]); fulladder f5(c[11], s[11], s[7], c[6], c[10]); fulladder f6(c[12], s[12], s[8], c[7], c[11]); fulladder f7(c[13], s[13], s[9], c[8], c[12]); halfadder h8(c[14], s[14], c[9], c[13]); assign product[0] = p0[0];

assign product[1] = s[0]; assign product[2] = s[5]; assign product[3] = s[10]; assign product[4] = s[11]; assign product[5] = s[12]; assign product[6] = s[13]; assign product[7] = s[14]; endmodule Module for partial product generator module partial_product(A,B,p0,p1,p2,p3); input [3:0]A; input [3:0]B; output [3:0]p0; output [3:0]p1; output [3:0]p2; output [3:0]p3; and pp1(p0[0], A[0], B[0]); and pp2(p0[1], A[0], B[1]); and pp3(p0[2], A[0], B[2]); and pp4(p0[3], A[0], B[3]); and pp5 (p1[0], A[1], B[0]); and pp6(p1[1], A[1], B[1]); and pp7(p1[2], A[1], B[2]); and pp8(p1[3], A[1], B[3]); and pp9(p2[0], A[2], B[0]); and pp10(p2[1], A[2], B[1]); and pp11(p2[2], A[2], B[2]); and pp12(p2[3], A[2], B[3]); and pp13(p3[0], A[3], B[0]); and pp14(p3[1], A[3], B[1]); and pp15(p3[2], A[3], B[2]); and pp16(p3[3], A[3], B[3]); endmodule Module for full adder module fulladder(COUT,S,A,B,CIN); input A,B,CIN; output S,COUT; wire p,q,r; xor x2(p,A,B); xor x3(S,p,CIN); and a2(q,p,CIN); and a3(r,A,B); or o1(COUT,q,r); endmodule Module for half adder module halfadder(CO,S,A,B);

input A,B; output S,CO; xor x1(S,A,B); and a1(CO,A,B); endmodule

Top level module for cube algorithm module cubing (x,xcube); input [3:0]x; output [11:0]xcube; wire [3:0] asq, bsq; wire [5:0] acu,bcu,asqb,absq; wire [6:0] tasqb,tabsq; wire [8:0] stabsq; wire [10:0] stasqb; wire [10:0] sacu; wallacetree1 w1 (x[3:2],x[3:2],asq); wallacetree2 w2 (x[3:2],asq,acu); wallacetree1 w3 (x[1:0],x[1:0],bsq); wallacetree2 w4 (x[1:0],bsq,bcu); wallacetree2 w5 (x[1:0],asq,asqb); wallacetree2 w6 (x[3:2],bsq,absq); assign tasqb = (asqb<<1)+asqb; assign tabsq = (absq<<1)+absq; assign stabsq = tabsq<<2; assign stasqb = tasqb<<4; assign sacu = acu<<6; assign xcube = sacu+stasqb+stabsq+bcu; endmodule Module for 2X2 Wallace tree multiplier module wallacetree1 (A,B,p); input [1:0]A; input [1:0]B; output [3:0]p; wire [1:0] p0,p1,p2,p3; partial_product1 pa(A,B,p0,p1); partialadder1 par(p0,p1,p); endmodule Module for 4x2 Wallace tree multiplier module wallacetree2 (A,B,p); input [1:0]A; input [3:0]B; output [5:0]p; wire [3:0] p0,p1; partial_product2 pa(A,B,p0,p1);

partialadder2 par(p0,p1,p); endmodule Module for 2X2 partial product adder using Wallace tree structure module partialadder1 (p0,p1,p); input [1:0]p0; input [1:0]p1; output [3:0]p; wire [1:0] s; wire [1:0] c; halfadder h1(c[0], s[0], p0[1], p1[0]); halfadder h2(c[1], s[1],p1[1], c[0]); assign p[0] = p0[0]; assign p[1] = s[0]; assign p[2] = s[1]; assign p[3] = c[1]; endmodule

Module for 4X2 partial product adder using Wallace tree structure module partialadder2 (p0,p1,p); input [3:0]p0; input [3:0]p1; output [5:0]p; wire [3:0] s; wire [3:0] c; halfadder h1(c[0] ,s[0], p0[1], p1[0]); fulladder f1(c[1] ,s[1], p0[2], p1[1], c[0]); fulladder f2(c[2] ,s[2], p0[3], p1[2], c[1]); halfadder h2(c[3] ,s[3], p1[3], c[2]); assign p[0] = p0[0]; assign p[1] = s[0]; assign p[2] = s[1]; assign p[3] = s[2]; assign p[4] = s[3]; assign p[5] = c[3]; endmodule Module for 2x2 partial product generator module partial_product1(a,b,p0,p1); input [1:0] a; input [1:0]b; output [1:0]p0; output [1:0]p1; and pp0(p0[0],a[0],b[0]); and pp1(p0[1],a[0],b[1]); and pp2(p1[0],a[1],b[0]); and pp3(p1[1],a[1],b[1]); endmodule

Module for 4x2 partial product generator module partial_product2(a,b,p0,p1); input [1:0] a; input [3:0]b; output [3:0]p0; output [3:0]p1; and pp0(p0[0], a[0], b[0]); and pp1(p0[1], a[0], b[1]); and pp2(p0[2], a[0], b[2]); and pp3(p0[3], a[0], b[3]); and pp4(p1[0], a[1], b[0]); and pp5(p1[1], a[1], b[1]); and pp6(p1[2], a[1], b[2]); and pp7(p1[3], a[1], b[3]); endmodule Test bench for square algorithm module input_test; reg [7:0]x; wire [15:0]xsquare; squaring s(.x(x),.xsquare(xsquare)); initial begin x=8'b00000000; #20 x=8'b10011001; #40 x=8'b10101010; #60 x=8'b00000001; #80 x=8'b11111111; #10 $finish; end initial $monitor($time, "x=%b,xsquare=%b", x,xsquare); endmodule Test bench for cube algorithm module input_testc; reg [3:0]x; wire [11:0]xcube; cubing s(.x(x),.xcube(xcube)); initial begin x=4'b0000; #20 x=8'b1001; #40 x=8'b1010; #60 x=8'b0001; #80 x=8'b1111; #10 $finish; end initial $monitor($time, "x=%b,xsquare=%b", x,xsquare); endmodule