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KIN TRC MY TNH

ET4270
TS. Nguyn c Minh

[Adapted from Computer Organization and Design, 4th Edition, Patterson & Hennessy, 2008, MK] [Adapted from Computer Architecture lecture slides, Mary Jane Irwin, 2008, PennState University]

T chc lp
S tn ch Ging vin Vn phng Email 3 (3-1-1-6) TS. Nguyn c Minh C9-401 nguyenducminh@edabk.org

Website
Sch

http://ca.edabk.org
Computer Org and Design, 3rd Ed., Patterson &Hennessy, 2007

Digital Design and Computer Architecture, David Money Harris Th nghim


Bi tp

3 bi
Theo chng, bi xem trn trang web

Gii thiu

HUST-FET, 21/10/2012

im s iu kin thi
Bi thi gia k
Bi tp ln Tin trnh
Ti a: 100 im, Bt u: 50 im Tch ly, tr qua tr li cu hi trn lp v ng gp t chc lp

Lab, Bi tp chng
30%
20% (?) 10%

Bi thi cui k
Bi tp ln

70%
10% (1-2 im thng)

Gii thiu

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Lch hc
Thi gian, a im:
L thuyt: 11 bui x 135 pht / 1 bui Bi tp ln: 4 bui x 135 pht / 1 bui Thay i lch (ngh, hc b) s c thng bo trn website trc 2 ngy Th 2:

Gii thiu

HUST-FET, 21/10/2012

Outline

My tnh in t
Tc pht trin ng dng Phn loi

Mc tiu mn hc

Gii thiu

HUST-FET, 21/10/2012

Pht trin ca cng ngh thng tin

? Major Technology Generations

Bipolar
Vacuum Tubes Relays

CMOS nMOS pMOS

Electromechanical

[from Kurzweil]

Gii thiu

HUST-FET, 21/10/2012

Bt u

EDSAC, University of Cambridge, UK, 1949


Gii thiu 7

HUST-FET, 21/10/2012

Ngy nay

Cameras Media Players

Smart phones

Set-top boxes Robots

Sensor Nets

Routers

Laptops

Supercomputers

Servers Automobiles

My tnh c mt khp mi ni
8

Gii thiu

HUST-FET, 21/10/2012

ng dng
Phng tin giao thng
Khi my tnh tr nn r hn, nh hn v c hiu sut cao hn, n c s dng trong t, xe my tng hiu sut s dng nhiu liu, gim nhim, tng an ton.

in thoi di ng, thit b vin thng


Gip con ngi giao tip d bt k u.

Bn gen
My tnh tr nn r v mnh hn 10-100 ln so vi cch y 10 nm cho php trang b cc my tnh phn tch v nh x bn gen ngi.

WWW
Nh s ph bin ca my tnh, cc thit b mng, Internet tr thnh mi trng lm th gii trn ngp thng tin (th gii thng tin).

B tm kim
Google tr thnh 1 ng t v 1 ch.

Gii thiu

HUST-FET, 21/10/2012

Cc loi my tnh
My tnh bn (eng, Desktop computers)
Mt ngi dng; Chy nhiu ng dng khc nhau; i km mn hnh, bn phm v chut; Yu cu gi thnh r, hiu nng cao

My ch (eng, Servers)
Nhiu ngi dng ng thi; Chy cc ng dng ln; Truy cp qua mng, Yu cu n nh v an ton cao.

Siu my tnh (eng, Supercomputers)


Chy cc ng dng khoa hc v cng ngh cao cp; Gm hng trm/nghn b x l, b nh v b lu tr dung lng ln; Yu cu hiu nng cao v c gi thnh cao. My tnh nhng (eng, Embedded computers (processors))

My tnh nm bn trong mt thit b khc, chy 1 ng dng xc nh trc.

Gii thiu

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Tng trng doanh s in thoi di ng

Tng trng in thoi di ng >> Tng trng my tnh bn

Gii thiu

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c im ca my tnh nhng ng dng trong nhiu lnh vc khc nhau Yu cu hiu nng rt khc nhau Yu cu hiu nng ti thiu v va . V d? Yu cu kht khe v gi thnh. V d? Yu cu kht khe v nng lng tiu th. V d? t chp nhn hng hc. V d?

Gii thiu

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Mc tiu mn hc
Kin thc v h thng my tnh: Giao din gia phn mm v phn cng Qu trnh bin dch chng trnh phn mm Cu to v hot ng ca phn cng my tnh Phng php nh gi nh lng v hiu nng my tnh nh hng ca cc thnh phn ln hiu nng my tnh K s phn mm: tn dng u im ca phn cng v la chn phn cng ti u K s phn cng: nh hng ca phn cng ln phn mm

Gii thiu

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Mc tiu mn hc

SOPC Builder
Processor Library

Configure Processor Select & Configure Perigherals, IP


p Conect Block

Custom Instructions

Peripheral Library

IP Modules

Quartus II
User Design Other IP Block

Nios II IDE
HDL Source Files
Generate

C++ file
Custom Library Peripheral Driver

Synthesis& Fitter

Verifacation & Debug

Compiler,Linker,Debugger

Atera FPGA

Gii thiu

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KIN TRC MY TNH


Thnh phn c bn ca my tnh
[Adapted from Computer Organization and Design, 4 th Edition, Patterson & Hennessy, 2008, MK]
[Adapted from Computer Architecture lecture slides, Mary Jane Irwin, 2008, PennState University]

Chng 1 Thnh phn c bn ca my tnh

Outline

Cc loi phn mm Cc khi phn cng Kin trc tp lnh Ni dung mn hc nh gi hiu nng my tnh

Chng 1 Thnh phn c bn ca my tnh

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Phn mm
Phn mm ng dng Phn mm h thng Phn cng

Phn mm h thng
H iu hnh gim st, giao tip gia phn cng v phn mm ng dng (nh Linux, MacOS, Windows)
iu khin cc hot ng vo ra c bn Cp pht b nh Cung cp s chia s c bo v gia cc ng dng

B bin dch chuyn i cc chng trnh ngn ng bc cao (nh C, Java) thnh cc cu lnh phn cng c th thc hin

Chng 1 Thnh phn c bn ca my tnh

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Trnh bin dch


High-level language program (in C)
swap (int v[], int k) (int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; ) swap: sll add lw lw sw sw jr $2, $5, 2 $2, $4, $2 $15, 0($2) $16, 4($2) $16, 0($2) $15, 4($2) $31

one-to-many

C compiler

Assembly language program (for MIPS)

one-to-one

assembler

Machine (object, binary) code (for MIPS)


000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 , , ,

Chng 1 Thnh phn c bn ca my tnh

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u im ca ngn ng bc cao
Ngn ng bc cao

Chng trnh c vit ngn ng t nhin v ph hp vi tng ng dng (V d: Fotran, Lisp, Java) Tng nng sut lp trnh vin m chng trnh d hiu, d g li, d kim tra Tng kh nng bo tr chng trnh

Chng trnh c lp vi phn cng s thc hin chng trnh Chng trnh c ti u ha cho tng loi phn cng nh cc thut ton ti u trong trnh bin dch

t chng trnh cn c pht trin bng hp ng

Chng 1 Thnh phn c bn ca my tnh

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Phn cng
5 thnh phn ca h thng my tnh:
ng d liu (eng, datapath) Khi iu khin B nh Khi vo Khi ra
Phn mm ng dng

Phn cng

Phn mm h thng

CPU = ng d liu + khi iu khin

Chng 1 Thnh phn c bn ca my tnh

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Kin trc vonNeumann


Memory (ROM/RAM)
Bus d liu Bus iu khin

Central Processing Unit (CPU)


PCI PCIe SCSI USB

I/O Devices

Bus a ch

B nh Memory DRAM SRAM ROM EEPROM Flash

B x l trung tm CPU Intel 80X86 Motorola 680X PowerPC ASIP

Phi ghp vo/ra (I/O)

Thit b vo/ra Mn hnh My in Bn phm Con chut cng Sensor, Actor

Chng 1 Thnh phn c bn ca my tnh

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Kin trc Havard


Bus d liu Bus iu khin Bus a ch

B nh d liu

B x l trung tm CPU

Phi ghp vo/ra (I/O)

Thit b vo/ra

Bus a ch Bus iu khin Bus d liu

B nh lnh

Chng 1 Thnh phn c bn ca my tnh

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B x l a nhn AMDs Barcelona

2MB shared L3 Cache

Core 1

512KB L2

512KB L2

4 nhn, lnh khng theo th t


ng h: 1,9 GHz

Core 2

Northbridge 512KB L2
512KB L2

Cng ngh 65nm


3 mc b m (L1, L2, L3) Tch hp b iu khin cu bc

Core 3

Core 4

Chng 1 Thnh phn c bn ca my tnh

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Kin trc tp lnh (ISA)


Kin trc tp lnh (eng, Instruction Set Architecture - ISA), hay kin trc: l giao din tru tng gia phn cng v cc phn mm lp thp nht, bao gm tt c cc thng tin cn thit vit chng trnh ngn ng my nh: cc ch th my, thanh ghi, bn b nh, phng php vo ra, Giao din nh phn ng dng (eng, Application Binary Interface ABI) bao gm cc ch th my c bn ngi dng c th s dng v cc hm h thng cp thp do h iu hnh cung cp. Kt lun:
My tnh gm cc lp phn cp theo mc tru tng. Kin trc tp lnh l mt lp then cht trong h thng my tnh. Cc trin khai phn cng khc nhau tun theo cng chun v kin trc tp lnh c th thc hin cng mt phn mm ging nhau.

Chng 1 Thnh phn c bn ca my tnh

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Cu trc ni dung mn hc
Chng 2. Giao din gia phn mm v phn cng
Kin trc tp lnh Biu din d liu T chc v truy cp b nh Lnh vo ra

Chng 3. Cu trc b x l
Thit k b x l trung tm K thut ng ng

Chng 4. B nh
Phn cp v thit k b nh

Chng 5. Vo ra
Thit b, c ch vo ra Cu trc bus

Chng 1 Thnh phn c bn ca my tnh

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nh gi v so snh cc my tnh
Quyt nh mua my tnh
Trong s cc my tnh, my no c
hiu nng tt nht? gi thnh r nht? t l gi thnh/hiu nng tt nht?

La chn thit k my tnh


Trong cc la chn thit k, thit k no
cho ci tin tt nht v hiu nng? gi thnh thp nht? t l gi thnh/hiu nngtt nht?

Yu cu:
Cn c so snh Thng s nh gi

Mc tiu: nm r s nh hng ca cc nhn t trong kin trc my tnh ti hiu nng ton h thng; vai tr quan trng tng i v gi thnh ca cc nhn t ,
Chng 1 Thnh phn c bn ca my tnh 26

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Hiu nng (eng. Performance)


Thi gian p ng (thi gian thc thi) l khong thi gian gia thi im bt u thc hin v thi im hon thnh mt nhim v
Quan trng i vi 1 ngi s dng yu cu h thng thc hin 1 nhim v

Thng lng (di thng) l tng s nhim v c th c hon thnh trong 1 khong thi gian
Quan trng i vi ngi iu hnh trung tm d liu

Cn cc h o lng khc nhau cho hiu nng ca my tnh cng nh cn 1 tp hp cc ng dng khc nhau kim chun cc my tnh nhng, my tnh bn (thng ch trng n thi gian p ng) v cc my ch (thng ch trng n thng lng
Chng 1 Thnh phn c bn ca my tnh 27

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V d 1.1 Ci tin hiu nng


nh hng ca b x l ln thi gian p ng v thng lng Nu ta thay i cu trc my tnh nh sau th thi gian p ng v thng lng ca my tnh thay i th no?
Thay th b x l bng b x l nhanh hn B xung 1 b x l thc hin cc nhim v tch bit (nh trong h thng tm kim WWW)

Chng 1 Thnh phn c bn ca my tnh

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nh ngha hiu nng (tc )


Hiu nng (tc ) ca my tnh X:

1 Performance x Execution Time x


My tnh X nhanh hn my tnh Y, n ln:

Performance x ExecutionT ime y n Performance y ExecutionT ime x

ti a ha hiu nng, cn ti thiu ha thi gian thc hin

Gim thi gian p ng thng s tng thng lng


29

Chng 1 Thnh phn c bn ca my tnh

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V d 1.2 So snh hiu nng


Nu my tnh A thc hin 1 chng trnh mt 10s v my tnh B chy cng chng trnh mt 15s, my tnh A nhanh hn my tnh B bao nhiu ln?

Chng 1 Thnh phn c bn ca my tnh

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V d 1.2 So snh hiu nng


Nu my tnh A thc hin 1 chng trnh mt 10s v my tnh B chy cng chng trnh mt 15s, my tnh A nhanh hn my tnh B bao nhiu ln? T l so snh hiu nng ca A v B l:

Performance A ExecutionT ime B 15 1,5 Performance B ExecutionT ime A 10


A nhanh hn B 1,5 ln

Chng 1 Thnh phn c bn ca my tnh

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o hiu nng o thi gian thc hin


C 3 loi thi gian dng tnh hiu nng Thi gian p ng (thi gian ng h, thi gian tri qua):
Tng thi gian hon thnh 1 nhim v Bao gm: thi gian truy cp a, b nh, thi gian vo ra, thi gian cho h iu hnh

Thi gian b x l (CPU time)


Thi gian CPU ngi dng Thi gian CPU h thng

Chng 1 Thnh phn c bn ca my tnh

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Cc yu t tnh hiu nng


Thi gian CPU thi gian b x l dng thc hin 1 nhim v
Khng bao gm thi gian ch vo/ra hay thi gian thc hin cc chng trnh khc Thi gian CPU cho 1 chng trnh, Tcpu c tnh t s chu k ng h CPU thc hin chng trnh P v thi gian 1 chu k ng h:

Tcpu C Tc or Tcpu C / f c
Hiu nng c th ci thin bng cch gim s chu k 1 xung ng h hoc gim s chu k cn thit thc hin chng trnh

Chng 1 Thnh phn c bn ca my tnh

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Xung nhp ng h
CPU hot ng ng b theo ng h

1 chu k
ng h Tc

10 nsec clock cycle => 100 MHz clock rate 5 nsec clock cycle => 200 MHz clock rate
2 nsec clock cycle => 500 MHz clock rate 1 nsec (10-9) clock cycle => 1 GHz (109) clock rate

500 psec clock cycle => 2 GHz clock rate

Chng 1 Thnh phn c bn ca my tnh

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V d 1.3 Ci thin hiu nng My tnh A vi xung ng h 2GHz thc hin 1 chng trnh ht 10 giy. thc hin chng trnh trong 6 giy bng my tnh B, ta cn tng tc xung ng h ca my B. Tuy nhin, tng tc xung ng h cng lm tng s chu k cn thit ln 1,2 ln. Xc nh tc xung ng h my tnh B.

Chng 1 Thnh phn c bn ca my tnh

V d 1.3 Ci thin hiu nng


Cng thc tnh thi gian CPU, khi my tnh A thc hin chng trnh: C

Tcpu, A

f c, A

S chu k my tnh A dng thc hin chng trnh:

S chu k my tnh B dng thc hin chng trnh:

C A Tcpu, A f c, A 10 2 109 20 109 cycles

Tc ng h ca my tnh B:

CB 1,2 C A

f c,B

CB 1,2 20 109 4GHz Tcpu, B 6

Chng 1 Thnh phn c bn ca my tnh

S xung ng h
S xung ng h thc hin 1 chng trnh: Trong :

C I CPI

I l s ch th my cn thc hin trong chng trnh CPI (eng. Clock cycles per Instruction) l s xung ng h trung bnh cn thc thi 1 ch th my,

CPI c th dng so snh cc my tnh khc nhau cng trin khai 1 kin trc tp lnh. V d: c 3 loi lnh A, B, C khc nhau trong 1 kin trc tp lnh. Mi lnh trong tng loi c CPI tng ng:
CPI for this instruction class B 2
37

CPI

A 1

C 3

Chng 1 Thnh phn c bn ca my tnh

HUST-FET, 21/10/2012

V d 1.4 So snh da trn CPI My tnh A v B cng trin khai 1 kin trc tp lnh. My A c chu k ng h l 250ps, v CPI hiu dng cho 1 chng trnh P l 2,0. My B c chu k ng h l 500ps, v CPI hiu dng cho cng 1 chng trnh P l 1,2. My tnh no nhanh hn v nhanh hn bao nhiu?

Chng 1 Thnh phn c bn ca my tnh

V d 1.4 So snh da trn CPI


Khi 2 my tnh A, B cng thc hin 1 chng trnh, chng cng thc hin I ch th. Do :

Tcpu, A I CPI A Tc , A I 2,0 250 ps 500 I Tcpu, B I CPI B Tc , B I 1,2 500 ps 600 I
V vy, my A nhanh hn my B v:

Performance A Tcpu, B 600 I 1,2 Performance B Tcpu, B 500 I

Chng 1 Thnh phn c bn ca my tnh

CPI hiu dng (trung bnh)


CPI hiu dng c tnh bng cch xt tt c cc lp ch th c trong chng trnh v ly trung bnh vi trng s l t l xut hin ca lp ch th trong chng trnh

CPI (CPI i ICi )


Trong :
i 1

ICi l t l (%) s ch th thuc lp i c thc thi CPIi l s chu k (trung bnh) cn thc hin 1 ch th thuc thuc lp i N l s lp ch th

CPI hiu dng ph thuc vo t l ch th trong mt chng trnh (tn sut ng ca cc ch th trong 1 hoc nhiu chng trnh)
Chng 1 Thnh phn c bn ca my tnh

Cng thc hiu nng


Cng thc hiu nng c bn:

Tcpu I CPI Tc

Tcpu

I CPI fc

Cng thc trn phn tch 3 yu t nh hng n hiu nng my tnh Cho php o CPU c o bng cch chy chng trnh:
Tc ng h c cho trc S ch th I c o bng cch dng cng c profilers/m phng s thc hin chng trnh m khng cn trin khai phn cng CPI ph thuc vo loi ch th, trin khai phn cng chi tit

Cho php so snh 2 trin khai phn cng hoc nh gi la chn gia 2 thit k
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Cc yu t quyt nh hiu nng CPU


Tcpu I CPI Tc
I Algorithm Programming language Compiler ISA Core organization Technology CPI Tc

Chng 1 Thnh phn c bn ca my tnh

Cc yu t quyt nh hiu nng CPU


Tcpu I CPI Tc
I Algorithm Programming language Compiler ISA Core organization Technology CPI Tc

X X X X

X X X X X X X X

Chng 1 Thnh phn c bn ca my tnh

V d 1.5 So snh on m chng trnh


Ngi thit k mt my tnh trin khai kin trc tp lnh gm 3 loi ch th A, B, C c CPI nh sau:
A
CPI 1

B
2

C
3

Vi 1 cu lnh ngn ng bc cao, ngi vit trnh bin dch c th la chn 2 on ch th my gm c tn sut cc loi ch th nh sau:
on m
1 2

A
2 4

B
1 1

C
2 1

on m no gm nhiu ch th hn? on m no nhanh hn? Tnh CPI ca tng on m.

Chng 1 Thnh phn c bn ca my tnh

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V d 1.5 So snh on m chng trnh


on m
1

A
2

B
1

C
2

A CPI 1

B 2

C 3

on m 1 dng 5 ch th, on m 2 dng 6 ch th S xung ng h thc hin mi on m c tnh 3 nh sau:


C1 (CPI i I1,i ) (1 2 2 1 3 2) 10
i 1 3

C2 (CPI i I 2,i ) (1 4 2 1 3 1) 9
i 1

Trong I1,i, I2,i l s lng ch th loi i trong on m 1 v 2 tng ng

Nh vy on m 1 chm hn on m 2, mc d dng t ch th hn
Chng 1 Thnh phn c bn ca my tnh 45

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V d 1.6 Ci tin hiu nng


Cho mt my tnh thc hin 1 chng trnh gm 4 loi ch th my c cc thng s v tn sut v CPI nh sau:
Op

ALU Load Store Branch

Tn sut (ICi) 50% 20% 10% 20%

CPIi

ICi x CPIi

1 5 3 2 =

Nu ta c b m d liu lm gim thi gian np (Load) xung 2 chu k, my tnh s nhanh ln bao nhiu ln? Nu ta c khi d bo r nhnh cho php tit kim 1 chu k khi r nhnh, hiu nng s th no? Nu ta c 2 khi ALU thc hin 2 ch th ALU ng thi?
Chng 1 Thnh phn c bn ca my tnh

V d 1.6 Ci tin hiu nng


Op Tn sut (ICi) ALU 50% Load 20% Store 10% Branch 20% CPIi ICi x CPIi 0,5 1 1,0 5 0,3 3 0,4 2 = 2,2

0,5

0,5

0,25

0,4
0,3 0,4 1,6

1,0
0,3 0,2 2,0

1,0
0,3 0,4 1,95

Nu ta c b m d liu lm gim thi gian np (Load) xung 2 chu k, my tnh s nhanh ln bao nhiu ln?
Tcpu = 1,6 x I x Tc v vy 2,2/1,6 means 37,5% faster

Nu ta c khi d bo r nhnh cho php tit kim 1 chu k khi r nhnh, hiu nng s th no?
Tcpu = 2,0 x I x Tc v vy 2,2/2,0 means 10% faster

Nu ta c 2 khi ALU thc hin 2 ch th ALU ng thi?


Tcpu = 1,95 x I x Tc v vy 2,2/1,95 means 12,8% faster
Chng 1 Thnh phn c bn ca my tnh

Chng trnh o kim chun


Benchmarks l tp hp cc chng trnh to nn 1 workload c chn o hiu nng SPEC (System Performance Evaluation Cooperative) to ra 1 tp cc benchmark chun bt u t SPEC89. Chun mi nht l SPEC CPU2006 gm 12 chng trnh s nguyn (CINT2006) v 17 chng trnh s thc (CFP2006) www.spec.org Ngoi ra, cn c cc tp cc workload o kim nng lng (SPECpower_ssj2008), mail (SPECmail2008), hay a phng tin (mediabench),

Chng 1 Thnh phn c bn ca my tnh

Cc chng trnh o kim


Integer benchmarks
gzip compression wupwise

FP benchmarks
Quantum chromodynamics

vpr
gcc

FPGA place & route


GNU C compiler

swim
mgrid

Shallow water model


Multigrid solver in 3D fields

mcf
crafty

Combinatorial optimization
Chess program

applu
mesa

Parabolic/elliptic pde
3D graphics library

parser
eon perlbmk gap

Word processing program


Computer visualization perl application Group theory interpreter

galgel
art equake facerec

Computational fluid dynamics


Image recognition (NN) Seismic wave propagation simulation Facial image recognition

vortex
bzip2

Object oriented database


compression

ammp
lucas

Computational chemistry
Primality testing

twolf

Circuit place & route

fma3d
sixtrack

Crash simulation fem


Nuclear physics accel

apsi

Pollutant distribution

Chng 1 Thnh phn c bn ca my tnh

SPEC CINT2006 on Barcelona (Tc = 0,4 x 10-9)


Name
perl bzip2 gcc

Ix109
2 118 2 389 1 050

CPI
0,75 0,85 1,72

ExTime
637 817 724

RefTime
9 770 9 650 8 050

SPEC ratio
15,3 11,8 11,1

mcf
go hmmer sjeng

336
1 658 2 783 2 176

10,00
1,09 0,80 0,96

1 345
721 890 837

9 120
10 490 9 330 12 100

6,8
14,6 10,5 14,5

libquantum
h264avc omnetpp astar xalancbmk

1 623
3 102 587 1 082 1 058

1,61
0,80 2,94 1,79 2,70

1 047
993 690 773 1 143

20 720
22 130 6 250 7 020 6 900

19,8
22,3 9,1 9,1 6,0

Geometric Mean
Chng 1 Thnh phn c bn ca my tnh

11,7

So snh v tng kt hiu nng Tng kt hiu nng cho 1 tp tiu chun thnh mt s duy nht:
Thi gian thc hin c chun ha thnh SPECRatio (t s ln c ngha l nhanh hn) Ly trung bnh nhn ca cc SPECRatio:

GM n

SPEC ratio
i 1

Chng 1 Thnh phn c bn ca my tnh

Cc thng s hiu nng khc

Nng lng tiu th l mt thng s quan trng, c bit vi th trng h nhng (thi lng pin l quan trng vi h thng)

Chng 1 Thnh phn c bn ca my tnh

Lut Amdahl
Khi thc hin ci tin mt c im ca h thng, tc dng ca vic ci tin b gii hn bi c im c ci tin
Tcpu sau khi ci tin =

Tcpu nh hng bi s ci tin


T l ci tin

+ Tcpu khng nh hng

Lut c bn tnh ton nh lng s ci tin Khi ci tin, cn ch trng n cc trng hp thng dng t ra gii hn s lng b x l hot ng song song

Chng 1 Thnh phn c bn ca my tnh

53

HUST-FET, 21/10/2012

V d 1.7 - Lut Amdahl


1 chng trnh thc hin bi 1 my tnh trong 100 giy. Trong , 80 giy c dng thc hin php nhn. Vy cn phi tng tc php nhn ln my ln c th tng tc thc hin chng trnh ln 5 ln?
Tcpu sau khi ci tin =
Tcpu nh hng bi s ci tin T l ci tin 80 giy 20 giy = n + (100-80)

+ Tcpu khng nh hng

Khng th ci tin tng tc c 5 ln

Chng 1 Thnh phn c bn ca my tnh

54

HUST-FET, 21/10/2012

Kt lun chng
H thng my tnh c xy dng t phn cp cc lp tru tng. Cc chi tit trin khai lp di b che khut khi lp trn. Kin trc tp lnh lp giao tip gia phn cng v phn mm mc thp l lp tru tng quan trng trong h thng my tnh. Phn cng my tnh gm 5 thnh phn: ng d liu, khi iu khin, b nh, khi vo, v khi ra. 5 thnh phn kt ni vi nhau bng h thng bus theo m hnh vonNeumann hoc m hnh Havard. Phng php nh gi hiu nng mt h thng my tnh l dng thi gian thc hin 1 chng trnh. Thi gian thc hin chng trnh c tnh bng cng thc:

Tcpu I CPI Tc
Chng 1 Thnh phn c bn ca my tnh 55

HUST-FET, 21/10/2012

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