2 Semaforo 2.1 semaforo.vhd Library ieee; Use ieee.std_logic_1164. all; use ieee.std_logic_unsigned.

all; entity semaforo is port (clk : in s t d _ l o g i c; clr : in s t d _ l o g i c; luces: out s t d _ l o g i c _ v e c t o r (5 downto 0)); end semaforo; architecture semaforo_arq of semaforo is type estado_tipo is (S0,S1,S2,S3,S4,S5); signal estado: estado_tipo; signal cont: s t d _ l o g i c _ v e c t o r (3 downto 0); constant Segs_5: s t d _ l o g i c _ v e c t o r (3 downto 0 ) := "1111" ; constant Seg_1: s t d _ l o g i c _ v e c t o r (3 downto 0) := "0011"; begin process (clk, clr) begin if clr = '1' then estado <= S0; cont <= X "0"; elsif (clk'event and clk = '1') then case estado is when S0 => if cont < Segs_5 then estado <= S0; cont <= cont + 1;

else estado <= S1; cont <= X "0"; end if; when S1 => if cont < Seg_1 then estado <= S1; cont <= cont + 1; else estado <= S2; cont <= X"0"; end if; when S2 => if cont < Seg_1 then estado <= S2; cont <= cont + 1; else estado <= S3; cont <= X"0"; end if; when S3 => if cont < Segs_5 then estado <= S3; cont <= cont + 1; else estado <= S4; cont <= X"0"; end if; when S4 => if cont < Seg_1 then

estado <= S4; cont <= cont + 1; else estado <= S5; cont <= X "0"; end if; when S5 => if cont < Seg_1 then estado <= S5; cont <= cont + 1; else estado <= S0; cont <= X"0"; end if; when others=> estado <= S0; end case; end if; end process;

C2: process (estado) begin case estado is when S0 => luces <= "100001"; when S1 => luces <= "100010"; when S2 => luces <= "100100"; when S3 => luces <= "001100"; when S4 => luces <= "010100"; when S5 => luces <= "100100";

when others=> luces <= "100001; end case; end process; ends emaforo_arq;

2.2 top_semaforo.vhd library ieee; use ieee.std_logic_1164. all; entity semaforo_top is port ( clk: in s t d _ l o g i c; btn : in s t d _ l o g i c _ v e c t o r (3 downto 0); led : out s t d _ l o g i c _ v e c t o r (7 downto 2)); end semaforo_top; architecture semaforo_arq of semafor_top is component divisorreloj is port (clkin, reset: in s t d _ l o g i c; clkout: out s t d _ l o g i c); end component ;

component semaforo is port ( clk: in s t d _ l o g i c; clr: in s t d _ l o g i c; luces: out st d _ l o g i c _ v e c t o r (5 downto 0 )); end component; signal clr, clk1: s t d _ l o g i c; begin

clr <= btn(3); U1: clkdiv port map (clkin => CLK50M, reset => reset, clkout => clk1); U2: semaforo port map (clk => clk1, clr => clr, luces => led); end architecture semaforo_top;