Mt s khai nim chung v nganh thit k v ch to vi mch

Gi nh chung ta mun thit k mt h thng SoC (System on Chip). H thng nay bao
gm 1 CPU 32 bit, mt system bus 32 bit, mt lot cac thit b ngoi vi khac nhu: iu
khin memory, iu khin xut nhp, iu khin USB..., tt c cac module trn uoc gn
voi system bus. Nhin chung qui trinh thit h s uoc din ra nhu duoi y.
1. System design
Phn thit k nay c bit quan trong, nguoi thit k thuong la truong du an. Nguoi thit
k phi ly gii 100 h thng sp thit k. Nguoi thit k cn phi hiu r nguyn ly hot
ng cua toan b h thng, cac c im v cng ngh, tc xu ly, muc tiu thu nng
luong, cach b tri cac pins, cac luoc khi, cac iu kin vt ly nhu kich thuoc, nhit
, in ap...
Tt c cac buoc thit k trong system design u uoc din ra ma khng co su h tro c
bit nao tu cac cng cu chuyn dung.
Sau khi co bn thit k (yu cu) h thng, truong du an s chia nho cng vic ra cho
tung i thit k. Mi i s m nhn mt b phn nao o trong h thng, vi du i
CPU, i bus, i peripheral, i phn mm, i test...
2. Function design
Phn nay la buoc k tip cua system design, vi du cho i CPU.
Team leader s la nguoi quyt nh spec. chi tit cua CPU dua trn yu cu h thng tu
truong du an. Cac cuc design review s din ra hang tun giua cac team leaders va
truong du an. Sau nhiu review, tho lun nhu vy, mt bn spec. kha chi tit cho CPU s
uoc hoan thin duoi dng document (word, pdI) voi hang trm luoc khi (block
diagram), biu thoi gian (timing chart), cac loi bng biu.
Team leader chu trach nhim chia nho cng vic cho tung thanh vin trong i. Vi du
mt nguoi m nhn phn ALU, mt nguoi m nhn phn Decoder,...
Toi luot minh, tung thanh vin s su dung cac cng cu chuyn dung thit k b phn
(module) minh m nhn. Trao luu hin nay la dung ngn ngu thit k phn cung
(Verilog-HDL, VHDL, System-C...) hin thuc hoa cac chuc nng logic. Nguoi ta goi
muc thit k nay la thit k muc RTL (Register TransIer Level). Thit k muc RTL nghia
la khng cn quan tm n cu to chi tit cua mch in ma chi chu trong vao chuc nng
cua mch dua trn kt qu tinh toan cung nhu su lun chuyn du liu giua cac register
(Ilip-Ilop).
Vi du mt on code Verilog miu t mt b lua chon 2 bit:
/* 2-1 SELECTOR */
module SEL ( A, B, SEL, OUT );
input A, B, SEL;
output OUT;

assign OUT SEL21FUNC ( A, B, SEL );
Iunction SEL21FUNC;
input A, B, SEL;
iI ( SEL 0 )
SEL21FUNC A;
else
SEL21FUNC B;
endIunction
endmodule
Thng thuong cac Iile text nhu trn uoc goi la cac Iile RTL (truong hop vit bng ngn
ngu Verilog hoc VHDL).
D kim tra chinh ung n cua mch in, nguoi ta dung mt cng cu m phong vi du
nhu NC-Verilog (Native Code Verilog) hay NC-VHDL cua hng Cadence, ModelSim
cua hng Mentor Graphics. Qua trinh debug s uoc lp i lp li trn may tinh cho toi
khi thit k tho mn yu cu tu team leader. Thanh qu cua thanh vin la cac Iile RTL.
Team leader s tng hop cac Iile RTL tu thanh vin, ghep cac module voi nhau thanh mt
module lon, o chinh la RTL cho c CPU. Toi luot minh team leader s dung simulator
m phong va kim tra tinh ung n cua CPU, nu co vn thi s Ieedback li cho
thanh vin yu cu ho sua.
Sau khi uoc test cn thn, toan b cu truc RTL trn s uoc np cho truong du an.
Tuong tu i voi cac module khac: bus, peripherals,...
Cac module trn li uoc tip tuc ghep voi nhau cu thanh nn mt SoC hoan chinh,
bao gm: CPU, system bus, peripherals... SoC nay la thanh qu cua phn Function
design.
3. Synthesis - Place - Route
Dy la buoc chuyn nhung RTLs thit k o phn 2 xung muc thit k thp hon. Cac
chuc nng muc truu tuong cao (RTL) s uoc hoan (synthesize) i thanh cac quan h
logic (NOT, NAND, NOR, MUX,...). Cac tool chuyn dung s thuc hin nhim vu nay,
vi du nhu Design Compiler cua hng Synopsys, SynpliIy cua hng Synplicity, XST cua
hng Xilinx.... Kt qu hoan i s khac nhau tuy theo synthesis tool va th vin. Thu
vin o y la b cac "linh kin" va "macro" - uoc cung cp boi cac nha sn xut ban
dn. Vi du hng NEC co mt thu vin ring, hng SONY co mt thu vin ring, hng
Xilinx cung co thu vin cua ring minh. Vic chon thu vin nao phu thuc vao vic hng
nao s sn xut chip sau nay. Vi du SoC ln nay s mang i nho TSMC cua Dai Loan sn
xut, vy s chon thu vin cua TSMC.
Kt qu cua buoc Synthesis nay la cac "net-list" cu truc theo mt tiu chun nao o,
thuong la EDIF (Electronic Design Interchange Format).
Net-list anh du su hoan thanh thit k SoC o muc "thuong luu".
4. Layout design
Phn nay la khoi u cho thit k muc "h luu", thuong uoc m nhim boi chuyn gia
trong cac hng sn xut ban dn. Ho su dung cac cng cu CAD chuyn net-list sang
kiu data cho layout. Netlist s tro thanh bn v cach b tri cac transistor, capacitor,
resistor,... O y phi tun thu nghim ngt mt thu goi la Design Rule. Vi du chip dung
cng ngh 65nm thi phi dung cac kich thuoc la bi s cua 65nm...
Keyword: DRC (design rule check), LVS (layout versus schematic), layout design
5. Mask patten design
Buoc k tip cua layout design la mask pattern. Phn nay thuc ra ging ht voi artwork
trong thit k bn in. Cac b mask (cho cac buoc sn xut khac nhau) s uoc to ra duoi
dng data c bit. Mask data s uoc gui toi cac nha sn xut mask nhn v mt b
mask kim loi phuc vu cho cng vic sn xut tip theo.
!. S"n #u$t mask
Co th xem mask la cai khun uc vi mch ln tm silicon. Cng ngh sn xut mask
hin i chu yu dung tia in tu (EB - Electron Beam). Cac in tu voi nng luong lon
(vai chuc keV) s uoc vut thanh chum va uoc chiu vao lop Iilm Crom trn b mt
tm thuy tinh. Phn Cr khng b che boi mask (artwork) s b pha huy, kt qu la phn Cr
khng b chum electron chiu vao s tro thanh mask thuc su. Mt chip cn khong 20 toi
30 masks. Gia thanh cac tm mask nay cuc t, c vai triu USD.
%. &hu'n () *a+e
Dy la buoc tinh ch cat (SiO2) thanh Silic nguyn cht (.). Silic nguyn
cht s uoc pha thm tp cht la cac nguyn t nhom 3 hoc nhom 5. Vi du pha B s
uoc waIer loi p, pha P s ra waIer loi n. Silicon s uoc ct thanh cac tm trn uong
kinh 200mm hoc 300mm voi b day c 50um. Co cac cng ty chuyn sn xut silicon
waIer. Chng hn ShinEtsu la cng ty cung cp khong 0 silicon waIer cho th truong
ban dn Nht Bn. Gia mt tm waIer 200mm khong 20 USD.
Tu khoa: C (Czchralski) method, SOI (Silicon On Insulator), SOS (Sillicon On
Sapphire), SIMOX (Separation by IMplanted OXygen), eleven-nine, epitaxial waIer
,. &-c .u- t/nh #0 l1 *a+e
Tt c uoc thuc hin trong mi truong siu sch (ultra clean room). Sau y la mt s
processes trong clean room:
* Rua (wet process): y la buoc lam sch waIer bng cac dung dch hoa hoc. Vi du
APM (hn hop NHOH/H2O2/H2O) dung lam sch cac particle nhu bui trong khng
khi, bui tu nguoi bay ra; HPM (hn hop HCl/H2O2/H2O) dung lam sch cac tp cht va
kim loi him (Cu, Au, Pt...); HPM (hn hop H2SO/H2O2) lam sch cac tp cht huu
co (resist) va kim loi (e, Fe...); DHF (axit HF long) dung loi bo cac phn SiO2
khng cn thit. Tu khoa: RCA, LAL00, ultra clean technology
* -xi hoa (Oxidation): to SiO2 trn b mt waIer trong o lop SiO2 mong c 1 toi 2
nanomet s tro thanh gate cua transistor. Tu khoa: cu to va nguyn ly hot ng cua
MOSFET, ITRS (International Technology Roadmap Ior Semiconductor), LOCOS (local
oxidation oI silicon), STI (Swallow Trench Isolation)
* CVD (Chemical Vapor Deposition): to cac lop Iilm mong trn b mt waIer bng
phuong phap hoa hoc (SiO2, Si3N. Poly-Si, Si2). Vi du co th dung CVD o ap sut
thp trong mi truong SiH va H2 to ra lop poly-Si (Si a tinh th) lam in cuc
cho transistor. Tu khoa: CVD, LPCVD, poly-Silicon, batch process
* Cy Ion (Ion implantation): Su dung cac ngun ion nng luong cao (vai chuc toi vai
trm keV, nng c 2E-15 cm-3) bn truc tip ln b mt Si nhm thay i nng tp
cht trong Si. Vi du bn cac ion As to ra vung n lam source va drain cho
MOSFET. Tu khoa: ion implantation, source, drain, dose
* Ct (etching): loi bo cac phn SiO2 khng cn thit. Co hai loi: wet-etching dung axit
HF long ha tan SiO2; dry-etching dung plasma ct SiO2 khoi b mt Si. Tu khoa:
high-density plasma etching, RIE (Reactive Ion Etching), HF, etching
* Photolithography: phuong phap xu ly quang hoc transIer mask pattern ln b mt
waIer. aIer s uoc pht mt lop dung dch goi la resist, day cua lop nay khong
0.5um. nh sang s uoc chiu ln mask, phn anh sang i qua s lam mm resist. Sau
khi rua bng dung dch c bit (ging trang nh), phn resist khng b anh sang chiu
vao s tn ti trn waIer nhu la mask. (trong truong hop nay resist la loi positive). Tu
khoa: photolithography, EB, photo mask, KrF, ArF, F2, reticle, EUV, stepper, scanner,
OPC (optical proximity correction), PSM (phase shiIt mask), excimer laser
* Sputtering: La phuong phap phu cac nguyn tu kim loi (Al, Cu) ln b mt waIer. Ion
Ar voi nng luong khong 1 keV trong mi truong plasma s bn pha cac target kim
loi (Al, , Cu), cac nguyn tu kim loi s bt ra bam ln b mt waIer. Phn b phu s
tro thanh dy dn ni cac transistor voi nhau. Tu khoa: Multilevel interconnect, via,
contact, low-k, electro migration
* Annealing: Xu ly nhit giup cho cac lin kt chua hoan chinh cua Si (b damaged boi
ion implantation etc.) s to lin kt voi H. Vic nay co tac dung lam gim cac trap nng
luong ti b mt Si va SiO2.
* CMP (Chemical Mechanical Polishing): Lam phng b mt bng phuong phap co-hoa.
Dy la k thut moi uoc ap dung vao semiconductor process. Co tac dung h tro thm
cho cac xu ly nhu photolithography, etching etc.
2. 3i4m ta - 56ng g6i - 7u$t #89ng
Cac xu ly o phn 3 s uoc lp i lp li nhiu ln tuy thuc vao muc phuc tp cua
chip. Cui cung chip s uoc ct roi (mt tm waIer 300mm co th to uoc khong 0
con chip Pentium IV). Mt lot cac xu ly khac nhu back grinding (mai mong phn mt
duoi cua chip), bonding (ni ra cac pins, dung chi m vang hoc ng), mold (phu lop
cach in), marking (ghi tn hng sn xut etc.) Tu khoa: packaging, dicing, back
grinding, bonding, marking, PGA (pin grid array), BGA (Ball Grid Array), QFP (Quad
Flat Package)
Sau y la mt s hinh nh trong phng thi nghim sn xut vi mch
Quang cnh phng sch 1
Quang cnh phng sch 2
Wet process 1
Wet process 2
My Oxidation
My cy ion
My VCD
Mt etching !"ng p#as$a
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