library ieee;

use ieee.std_logic_1164.all;
entity tn0 is
port(
a: in std_logic;
b: in std_logic;
c: in std_logic;
d: in std_logic;
e: out std_logic);
end tn0;
architecture structural of tn0 is
signal u1_out: std_logic;
signal u2_out: std_logic;
component and2
port (i2: in std_logic; i1: in std_logic; y: out std_logic);
end component;
begin
user1: and2 port map (i1 => a, i2 =>b, y => u1_out);
user2: and2 port map (i1 => c, i2 =>d, y => u2_out);
e <= u1_out and u2_out;
end structural;