library ieee;

use ieee.std_logic_1164.all;
entity tn0 is
port(
a: in std_logic;
b: in std_logic;
c: in std_logic;
d: in std_logic;
e: out std_logic);
end tn0;
architecture dataflow of tn0 is
signal u1_out: std_logic;
signal u2_out: std_logic;
begin
u1_out <= a and b;
u2_out <= c and d;
e <= u1_out and u2_out;
end dataflow;