AUTO.

NLU

For more details and questions, contact me: thanhtam.h@gmail.com
CNG HC AVR
AVR4TIMER/COUNTER V CHUYN I ADC

Tho thun: ti liu ny thuc quyn s hu ca tc gi, bn c th t do tham kho
ti liu nhng khng c php s dng in thnh sch bo, ng ln cc din n
hay website, nhng bn c th dng ng link http://www.dieukhientudong.net
hng ti ti liu. Lin h tc gi qua email: thanhtam.h@gmail.com.

I. Bn s i n u.
Trong bi 3 ti gii thiu khi qut phng php lp trnh bng ngn ng C cho AVR vi
WinAVR v cch s dng ngt trong AVR. Bi 4 ny chng ta s kho st cc ch hot ng
ca phng php iu khin cc b nh thi, m (Timer/Counter) trong AVR. Cng c phc v
cho bi ny vn l b cng c WinAVR v phn mm m phng Proteus. Ti vn dng chip
Atmega8 lm v d. Mt iu khng may mn l khng phi tt c cc b Timer/Counter trn
tt c cc dng chip AVR l nh nhau, v th nhng g ti trnh by trong bi ny c th s khng
ng vi cc dng AVR khc nh AT90STuy nhin ti cng s c gng ch ra mt s im
khc bit c bn cc bn c th t mnh iu khin cc chip khc.
Sau bi ny, ti hy vng bn s:
- Nm bt c bn cc b Timer/Counter c trn AVR.
- S dng cc Timer/Counter nh cc b nh thi.
- S dng cc Timer/Counter nh cc b m.
- S dng cc Timer/Counter nh cc b to xung iu rng PWM.
- Vit mt v d iu khin ng c RC servo bng PWM.
II. Tng quan cc b Timer/Counter trn chip Atmega8.
Timer/Counter l cc module c lp vi CPU. Chc nng chnh ca cc b Timer/Counter,
nh tn gi ca chng, l nh th (to ra mt khong thi gian, m thi gian) v m s kin.
Trn cc chip AVR, cc b Timer/Counter cn c thm chc nng to ra cc xung iu rng
PWM (Pulse Width Modulation), mt s dng AVR, mt s Timer/Counter cn c dng nh
cc b canh chnh thi gian (calibration) trong cc ng dng thi gian thc. Cc b
Timer/Counter c chia theo rng thanh ghi cha gi tr nh thi hay gi tr m ca chng,
c th trn chip Atmega8 c 2 b Timer 8 bit (Timer/Counter0 v Timer/Counter2) v 1 b 16 bit
(Timer/Counter1). Ch hot ng v phng php iu khin ca tng Timer/Counter cng
khng hon ton ging nhau, v d chip Atmega8:
Timer/Counter0: l mt b nh thi, m n gin vi 8 bit. Gi l n gin v b ny ch
c 1 ch hot ng (mode) so vi 5 ch ca b Timer/Counter1. Ch hoat ng ca
Timer/Counter0 thc cht c th coi nh 2 ch nh (v cng l 2 chc nng c bn) l to
ra mt khong thi gian v m s kin. Ch l trn cc chip AVR dng mega sau ny nh
Atmega16,32,64chc nng ca Timer/Counter0 c nng ln nh cc b Timer/Counter1
Timer/Counter1: l b nh thi, m a nng 16 bit. B Timer/Counter ny c 5 ch
hot ng chnh. Ngoi cc chc nng thng thng, Timer/Counter1 cn c dng to ra
AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com
xung iu rng PWM dng cho cc mc ch iu khin. C th to 2 tn hiu PWM c lp trn
cc chn OC1A (chn 15) v OC1B (chn 16) bng Timer/Counter1. Cc b Timer/Counter kiu
ny c tch hp thm kh nhiu trong cc chip AVR sau ny, v d Atmega128 c 2 b,
Atmega2561 c 4 b
Timer/Counter2: tuy l mt module 8 bit nh Timer/Counter0 nhng Timer/Counter2 c
n 4 ch hot ng nh Timer/Counter1, ngoi ra n n cn c s dng nh mt module
canh chnh thi gian cho cc ng dng thi gian thc (ch asynchronous).
Trong phm vi bi 4 ny, ti ch yu hng dn cch s dng 4 ch hot ng ca cc
Timer/Counter. Ch asynchronous ca Timer/Counter2 s c b qua v c th ch ny
khng c s dng ph bin.
Trc khi kho st hot ng ca cc Timer/Counter, chng ta thng nht cch gi tt tn
gi ca cc Timer/Counter l T/C, v d T/C0 ch Timer/Counter0
III. S dng Timer/Counter.
C mt s nh ngha quan trng m chng ta cn nm bt trc khi s dng cc T/C trong
AVR:
- BOTTOM: l gi tr thp nht m mt T/C c th t c, gi tr ny lun l 0.
- MAX: l gi tr ln nht m mt T/C c th t c, gi tr ny c quy nh bi
bi gi tr ln nht m thanh ghi m ca T/C c th cha c. V d vi mt b
T/C 8 bit th gi tr MAX lun l 0xFF (tc 255 trong h thp phn), vi b T/C 16
bit th MAX bng 0xFFFF (65535). Nh th MAX l gi tr khng i trong mi
T/C.
- TOP: l gi tr m khi T/C t n n s thay i trng thi, gi tr ny khng nht
thit l s ln nht 8 bit hay 16 bit nh MAX, gi tr ca MAX c th thanh i
bng cch iu khin cc bit iu khin tng ng hoc c th nhp tr tip thng
qua mt s thanh ghi. Chng ta s hiu r v gi tr TOP trong lc kho st T/C1.
1. Timer/Counter0
Thanh ghi: c 4 thanh ghi c thit k ring cho hot ng v iu khin T/C0, l:
- TCNT0 (Timer/Counter Register): l 1 thanh ghi 8 bit cha gi tr vn hnh ca
T/C0. Thanh ghi ny cho php bn c v ghi gi tr mt cch trc tip.
- TCCR0 (Timer/Counter Control Register): l thanh ghi iu khin hot ng ca
T/C0. Tuy l thanh ghi 8 bit nhng thc cht ch c 3 bit c tc dng l CS00,
CS01 v CS02.

Cc bit CS00, CS01 v CS02 gi l cc chip chn ngun xung nhp cho T/C0
(Clock Select). Chc nng cc bit ny c m t trong bng 1.
Bng 1: chc nng cc bit CS0X
AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com

- TIMSK (Timer/Counter Interrupt Mask Register): l thanh ghi mt n cho ngt ca
tt c cc T/C trong Atmega8, trong ch c bit TOIE0 tc bit s 0 (bit u tin)
trong thanh ghi ny l lin quan n T/C0, bit ny c tn l bit cho php ngt khi c
trn T/C0. Trn (Overflow) l hin tng xy ra khi b gi tr trong thanh ghi
TCNT0 t n MAX (255) v li m thm 1 ln na.

Khi bit TOIE0=1, v bit I trong thanh ghi trng thi c set (xem li bi 3 v iu
khin ngt), nu mt trn xy ra s dn n ngt trn.
- TIFR (Timer/Counter Interrupt Flag Register): l thanh ghi c nh cho tt c cc b
T/C. Trong thanh ghi ny bit s 0, TOV0 l c ch th ngt trn ca T/C0. Khi c
ngt trn xy ra, bit ny t ng c set ln 1. Thng thng trong iu khin cc
T/C vai tr ca thanh ghi TIFR khng qu quan trng.
Hot ng: T/C0 hot ng rt n gin, hot ng ca T/C c kch bi mt tn hiu
(signal), c mi ln xut hin tn hiu kch gi tr ca thanh ghi TCNT0 li tng thm 1 n v,
thanh ghi ny tng cho n khi n t mc MAX l 255, tn hiu kch tip theo s lm thanh ghi
TCNT0 tr v 0 (trn), lc ny bit c trn TOV0 s t ng c set bng 1. Vi cch thc hot
ng nh th c v T/C0 v dng v c tng t 0 n 255 ri li quay v khng v qu trnh lp
li. Tuy nhin, yu t to s khc bit chnh l tnh hiu kch v ngt trn, kt hp 2 yu t ny
chng ta c th to ra 1 b nh thi gian hoc 1 b m s kin. Trc ht bn hy nhn li bng
1 v cc bit chn xung nhp cho T/C0. Xung nhp cho T/C0 chnh l tn hiu kch cho T/C0, xung
nhp ny c th to bng ngun to dao ng ca chip (thch anh, dao ng ni trong chip).
Bng cch t gi tr cho cc bit CS00, CS01 v CS02 ca thanh ghi iu khin TCCR0 chng ta
s quyt nh bao lu th s kch T/C0 mt ln. V d mch ng dng ca bn c ngun dao
ng clk
I/O
= 1MHz tc chu k 1 nhp l 1us ( 1 micro giy), bn t TCCR0=5 (SC02=1,
CS01=0, CS00=1), cn c theo bng 1 tn hiu kch cho T/C0 s bng clk
I/O
/1024 ngha l sau
1024us th T/C0 mi c kch 1 ln, ni cch khc gi tr ca TCNT0 tng thm 1 sau 1024us
(ch l tn s c chia cho 1024 th chu k s tng 1024 ln). Quan st 2 dng cui cng trong
bng 1 bn s thy rng tn hiu kch cho T/C0 c th ly t bn ngoi (External clock source),
AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com
y chnh l tng cho hot ng ca chc nng m s kin trn T/C0. Bng cch thay i
trng thi chn T0 (chn 6 trn chip Atmega8) chng ta s lm tng gi tr thanh ghi TCNT0 hay
ni cch khc T/C0 c th dng m s kin xy ra trn chn T0. Di y chng ta s xem
xt c th cch iu khin T/C0 theo 1 ch nh thi gian v m.
- B nh thi gian: chng ta c th to ra 1 b nh th ci t mt khong thi gian no
. V d bn mun rng c sau chnh xc 1ms th chn PB0 thay i trng thi 1 ln (nhp nhy),
bn li khng mun dng cc lnh delay nh trc nay vn dng v nhc im ca delay l
CPU khng lm g c trong lc delay, v th trong nhiu trng hp cc lnh delay rt hn ch
c s dng. By gi chng ta dng T/C0 lm vic ny, tng l chng ta cho b m T/C0
hot ng, khi n m 1ms th n s t kch hot ngt trn, trong trnh phc v ngt trn chng
tat hay i trng thi chn PB0. Ti minh ha tng nh trong hnh 1.
1ms
1ms 1ms
CPU runs CPU runs CPU runs
Timer/Counter
1ms
1ms 1ms
CPU nop CPU nop CPU nop
PB0 on
DELAY
PB0 off PB0 on
Overflow
PB0 on
Overflow
PB0 on
Overflow
PB0 off
PB0 off
Overflow
PB0 off

Hnh 1. So snh 2 cch lm vic
(CPU nop: CPU khng lm g c)
Mt vn ny sinh lc ny, nh ti trnh by trong phn trc, T/C0 ch m t 0 n 255
ri li quay v 0 (xy ra 1 ngt trn), nh th dng nh chng ta khng th ci t gi tr mong
mun bt k cho T/C0? Cu tr li l chng ta c th bng cch gn trc mt gi tr cho thanh
ghi TCNT0, khi y T/C0 s m t gi tr m chng ta gn trc v kt thc 255. Tuy nhin do
khi trn xy ra, TCNT0 li c t ng tr v 0, do vic gn gi tr khi to cho TCNT0 phi
c thc hin lin tc sau mi ln xy ra trn, v tr tt nht l t trong trnh phc v ngt trn.
Vic cn li v cng l vic quan trng nht l vic tnh ton gi tr chia (prescaler) cho
xung nhp ca T/C0 v vic xc nh gi tr khi u cn gn cho thanh ghi TCNT0 c c 1
khong thi gian nh th chnh xc nh mong mun. Trc ht chng ta s chn prescaler sao
cho hp l nht (chn gi tr chia bng cch set 3 bit CS02,CS01,CS00). Gi s ngun xung clock
nui chip ca chng ta l clk
I/O
=1MHz tc l 1 nhp mt 1us, nu chng ta prescaler=1, tc
l tn s ca T/C0 (tm gi l f
T/C0
) cng bng clk
I/O
=1MHz, c 1us T/C0 c kch v TCNT0 s
tng 1 n v. Khi gi tr ln nht m T/C0 c th t c l 256 x 1us=256us, gi tr ny nh
hn 1ms m ta mong mun. Nu chn prescaler=8 (xem bng 1) ngha l c sau 8 nhp (8us) th
TCNT0 mi tng 1 n v, kh nng ln nht m T/C0 m c l 256 x 8us=2048us, ln hn
AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com
1ms, vy ta hon ton c th s dng prescaler=8 to ra mt khong nh th 1ms. Bc tip
theo l xc nh gi tr khi u ca TCNT0 T/C0 m ng 1ms (1000us). ng vi
prescaler=8 chng ta bit l c 8us th TCNT0 tng 1 n v, d dng tnh c b m cn
m 1000/8=125 ln ht 1ms, do gi tr ban u ca TCNT0 phi l 256-125=131. Bn c
th quan st hnh 2 hiu thu o hn.
131 132 254 255 0 1 2 .......... ..........
count 125 times x 8us =1000us
Overflow
interrupt
count more
set TCNT0=131

Hnh 2. Qu trnh thc hin.
Hy to 1 Project bng Programmer Notepad vi tn gi TIMER0 v vit on code cho
Project ny nh trong list 1.
List 1. nh th 1ms vi T/C0
#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/delay.h>

int main(void){
DDRB=0xFF; //PORTB la output PORT
PORTB=0x00;

TCCR0=(1<<CS01); // CS02=0, CS01=1, CS00=0: chon Prescaler = 8
TCNT0=131; //gan gia tri khoi tao cho T/C0
TIMSK=(1<<TOIE0); // cho phep ngat khi co tran o T/C0
sei(); //set bit I cho phep ngat toan cuc

while (1){ //vng lp v tn
//do nothing
}
return 0;
}

//trinh phuc vu ngat tran T/C0
ISR (TIMER0_OVF_vect ){
PORTB ^=1; //doi trang thai Bit PB0
TCNT0=131; //gan gia tri khoi tao cho T/C0
}
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com
on code rt n gin, bn ch cn ch n 3 dng khai bo cho T/C0 (dng 9, 10, 11).
Vi dng 9: TCCR0=(1<<CS01) l 1 cch set bit CS01 trong thanh ghi iu khin TCCR0 ln 1, 2 bit
CS02 v CS00 c gi tr 0 (bn xem li bi 3 v cch set cc bit c bit trong cc thanh ghi), tm li
dng ny tng ng TCCR0=2, gi tr Prescaler c chn bng 8 (tham kho bng 1). Dng 10 chng
ta gn gi tr khi to cho thanh ghi TCNT0. V dng 11 set bit TIOE0 ln 1 cho php ngt xy ra khi
c trn T/C0. Trong trnh phc v ngt trn T/C0, chng ta s thc hin i trng thi chn PB0 bng
ton t XOR (^), ch n ngha ca ton t XOR: nu XOR mt bit vi s 1 th bit ny s chuyn
trng thi (t 0 sang 1 v ngc li). Cui cng v quan trng l chng ta cn gn li gi tr khi to cho
T/C0.
Bn c th v mt mch in m phng n gin dng 1 Oscilloscope nh trong hnh 3 kim tra
hot ng ca on code.

Hnh 3. M phng nh th ca T/C0.
- B m s kin: nh ti trnh by trong phn hot ng ca T/C0, chng ta c th dng
T/C0 nh mt b m (counter) m cc s kin (s thay i trng thi) xy ra trn chn T0.
Bng cch t gi tr cho thanh ghi TCCR0 = 6 (CS02=1, CS01=1, CS00=0) cho php m cnh
xung trn chn T0, nu TCCR0 = 7 (CS02=1, CS01=1, CS00=1) th cnh ln trn chn T0 s
c m. C s dng ngt hay khng ph thuc vo mc ch s dng. Kho st 1 v d n
gin gn ging vi v d m trong bi AVR2 nhng s dng T/C0 v ch m 1 chiu tng. Kt
ni mch in nh trong hnh 4, mi ln Button 1 c nhn, gi tr m tng thm 1. Button 2
dng reset gi tr m v 0. on code cho v d th 2 ny c trnh by trong List 2.
AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com

Hnh 4. m 1 chiu bng T/C0.
List 2. nh th 1ms vi T/C0 (v d khng s dng ngt)
#include <avr/io.h>
#include <avr/interrupt.h>

int main(void){
DDRB=0xFF; //PORTB la output PORT
PORTB=0x00;
DDRD=0x00; //khai bao PORTD la input de ket noi Button kich vao chan T0
PORTD=0xFF; //su dung dien tro keo len cho PORTD

TCCR0=(1<<CS02)|(1<<CS01); // CS02=1, CS01=1, CS00=0: xung nhip tu
//chan T0, canh xuong
TCNT0=0x00;

while (1){ //vng lp v tn
if (TCNT0==10) TCNT0=0;
PORTB=TCNT0; //xuat gia tri dem ra led 7 doan
if (bit_is_clear(PIND,7)) TCNT0=0; //Reset bo dem neu chan PD7=0
}
}
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Ni dung trong chng trnh chnh l khai bo cc hng giao tip cho cc PORT, PORTB
l ouput xut kt qu m ra led 7 on, PORTD c khi bo input v cc button c ni
vi PORT ny. T/C0 c khai bo s dng ngun kch ngoi t T0, dng cnh xung thng qua
dng TCCR0=(1<<CS02)|(1<<CS01), bn cng c th khai bo tng ng l TCCR0=6 (tham kho
bng 1). Gi tr ca b m s c xut ra PORTB kim tra. im ch trong on chng trnh ny
l macro bit_is_clear, y l mt macro c nh ngha trong file sfr_defs.h dng kim tra 1 bit
trong mt thanh ghi c bit c c xa (bng 0) hay khng, trong trng hp ca on code trn:
if(bit_is_clear(PIND,7)) TCNT0=0; ngha l kim tra xem nu chn PD7 c ko xung 0 (button 2
c nhn) th s reset b m v 0.
AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com

Nh vy vic s dng T/C0 l tng i n gin, bn ch cn khai bo cc gi tr thch hp
cho thanh ghi iu khin TCCR0 bng cch tham kho bng 1, sau khi to gi tr cho TCNT0
(nu cn thit), khai bo c s dng ngt hay khng bng cch set hay khng set bit TOIE0 trong
thanh ghi TIMSK l hon tt.
2. Timer/Counter1 (T/C1)
Timer/Counter1 l b T/C 16 bits, a chc nng. y l b T/C rt l tng cho lp trnh o
lng v iu khin v c phn gii cao (16 bits) v c kh nng to xung iu rng PWM
(Pulse Width Modulation thng dng iu khin ng c).
Thanh ghi: c kh nhiu thanh ghi lin quan n T/C1. V l T/C 16 bits trong khi rng
b nh d liu ca AVR l 8 bit (xem li bi 2) nn i khi cn dng nhng cp thanh ghi 8 bits
to thnh 1 thanh ghi 16 bit, 2 thanh ghi 8 bits s c tn kt thc bng cc k t L v H trong L
l thanh ghi cha 8 bits thp (LOW) v H l thanh ghi cha 8 bits cao (High) ca gi tr 16 bits
m chng to thnh.
- TCNT1H v TCNT1L (Timer/Counter Register): l 2 thanh ghi 8 bit to thnh
thanh ghi 16 bits (TCNT1) cha gi tr vn hnh ca T/C1. C 2 thanh ghi ny cho
php bn c v ghi gi tr mt cch trc tip. 2 thanh ghi c kt hp nh sau:

- TCCR1A v TCCR1B (Timer/Counter Control Register): l 2 thanh ghi iu
khin hot ng ca T/C1. Tt c cc mode hot ng ca T/C1 u c xc nh
thng qua cc bit trong 2 thanh ghi ny. Tuy nhin, y khng phi l 2 byte cao v
thp ca mt thanh ghi m l 2 thanh ghi hon ton c lp. Cc bit trong 2 thanh
ghi ny bao gm cc bit chn mode hay chn dng sng (Waveform Generating
Mode WGM), cc bit quy nh dng ng ra (Compare Output Match COM), cc
bit chn gi tr chia prescaler cho xung nhp (Clock Select CS)Cu trc ca 2
thanh ghi c trnh by nh bn di.





AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com
Nhn chung thuc ht cch phi hp cc bit trong 2 thanh ghi TCCR1A v
TCCR1B l tng i phc tp v T/C1 c rt nhiu mode hot ng, chng ta s
kho st chng trong phn cc ch hot ng ca T/C1 bn di. y, trong
thanh ghi TCCR1B c 3 bit kh quen thuc l CS10, CS11 v CS12. y l cc bit
chn xung nhp cho T/C1 nh truong T/C0. Bng 2 s tm tt cc ch xung nhp
trong T/C1.
Bng 2: chc nng cc bit CS12, CS11 v CS10

- OCR1A v OCR1B (Ouput Compare Register A v B): c mt s khi nim mi
m chng ta cn bit khi lm vic vi T/C1, mt trong s l Ouput Compare
(sorry, I dont wanna translate it to Vietnamese). Trong lc T/C hot ng, gi tr
thanh ghi TCNT1 tng, gi tr ny c lin tc so snh vi cc thanh ghi OCR1A
v OCR1B (so snh c lp vi tng thanh ghi), vic so snh ny trn AVR gi l
gi l Ouput Compare. Khi gi tr so snh bng nhau th 1 Match xy ra, khi
mt ngt hoc 1 s thay i trn chn OC1A (hoc/v chn OC1B) xy ra (y l
cch to PWM bi T/C1). Ti sao li c A v B? l v ngi thit k AVR mun
m rng kh nng ng dng T/C1 cho bn. A v B i din cho 2 knh (channel) v
B. Cng v iu ny m chng ta c th to 2 knh PWM bng T/C1. Tm li, c
bn 2 thanh ghi ny cha cc gi tr so snh, chc nng v cc ch hot ng
c th ca chng s c kho st trong cc phn sau.
AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com

- ICR1 (InputCapture Register 1): khi nim mi th 2 ca T/C1 l Input Capture.
Khi c 1 s kin trn chn ICP1 (chn 14 trn Atmega8), thanh ghi ICR1s
capture gi tr ca thanh ghi m TCNT1. Mt ngt c th xy ra trong trng
hp ny, v th Input Capture c th c dng cp nht gi tr TOP ca T/C1.
- TIMSK (Timer/Counter Interrupt Mask Register): cc b T/C trn AVR dng
chung thanh ghi mt n ngt, v th TIMSK cng c dng quy nh ngt cho
T/C1. C iu lc ny chng ta ch quan tm n cc bit t 2 n 5 ca TIMSK. C
tt c 4 loi ngt trn T/C1 (nh li T/C0 ch c 1 loi ngt trn)

Bit 2 trong TIMSK l TOIE1, bit quy nh ngt trn cho thanh T/C1 (tng t
trng hp ca T/C0).
Bit 3, OCIE1B l bit cho php ngt khi c 1 Match xy ra trong vic so snh
TCNT1 vi OCR1B.
Bit 4, OCIE1A l bit cho php ngt khi c 1 Match xy ra trong vic so snh
TCNT1 vi OCR1A.
Bit 5, TICIE1 l bit cho php ngt trong trng hp Input Capture c dng.
Cng vi vic set cc bit trn, bit I trong thanh ghi trng thi phi c set nu
mun s dng ngt (xem li bi 3 v iu khin ngt).
- TIFR (Timer/Counter Interrupt Flag Register): l thanh ghi c nh cho tt c cc b
T/C. Cc bit t 2 n 5 trong thanh ghi ny l cc c trng thi ca T/C1.

AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com
Cc mode hot ng: c tt c 5 ch hot ng chnh trn T/C1. Cc ch hot ng
c bn c quy nh bi 4 bit Waveform Generation Mode (WGM13, WGM12, WGM11
WGM10) v mt s bit ph khc. 4 bit Waveform Generation Mode li c b tr nm trong 2
thanh ghi TCCR1A v TCCR1B (WGM13 l bit 4, WGM12 l bit 3 trong TCCR1B trong khi
WGM11 l bit 1 v WGM10 l bit 0 trong thanh ghi TCCR1A) v th cn phi hp 2 thanh ghi
TCCR1 trong lc iu khin T/C1. Cc ch hot ng ca T/C1 c tm tt trong bng sau 3:
Bng 3: cc bit WGM v cc ch hot ng ca T/C1.


2.1. Normal mode (Ch thng)
y l ch hot ng n gin nht ca T/C1. Trong ch ny, thanh ghi m
TCNT1 c tng gi tr t 0 (BOTTOM) n 65535 hay 0xFFFF (TOP) v quay v 0. Ch
ny hon ton ging cch m Timer0 hot ng ch c khc l gi tr m cao nht l
65535 thay v 255 nh trong timer0. Nhn vo bng 3, set T/C1 Normal mode chng ta
cn set 4 bit WGM v 0, v 0 l gi tr mc nh ca cc thanh ghi nn thc t chng ta
khng cn tc ng n cc bit WGM. Duy nht mt vic quan trng cn lm l set cc bit
Clock Select (CS12, SC11, CS10) trong thanh ghi TCCR1B (xem thm bng 2). Bn c th
tham kho v d ca Timer0. on code trong list 3 l 1 v d to 1 khong thi gian 10ms
bng T/C1, normal mode:
AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com
List 3. nh th 10ms vi T/C1
#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/delay.h>

int main(void){
DDRB=0xFF; //PORTB la output PORT
PORTB=0x00;

TCCR1B=(1<<CS10); // CS12=0, CS11=0, CS10=1: chon Prescaler = 1
// thanh ghi TCCR1B duoc dung thay vi TCCR0 cua Timer0
TCNT1=55535; //gan gia tri khoi tao cho T/C1
TIMSK=(1<<TOIE1); // cho phep ngat khi co tran o T/C1
sei(); //set bit I cho phep ngat toan cuc

while (1){ //vng lp v tn
//do nothing
}
return 0;
}
//trinh phuc vu ngat tran T/C1
ISR (TIMER1_OVF_vect ){
PORTB ^=1; //doi trang thai Bit PB0
TCNT1=55535; //gan gia tri khoi tao cho T/C1
}
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

2.2. Clear Timer on Compare Match (xa timer nu xy ra bng trong so snh)-CTC
Mt cch gi tt ca ch hot ng ny l CTC, mt ch hot ng mi trn
T/C1. Nhn vo bng 3 bn s thy c 2 mode CTC (mode 4 v mode 12). Ti ly v d
mode 4 gii thch hot ng ca CTC. Khi bn set cc bit Waveform Generation Mode
tuong ng: WGM13=0, WGM12=1, WGM11=0, WGM10=0 th mode 4 c chn. Trong
mode ny, thanh ghi OCR1A cha gi tr TOP (gi tr so snh do ngi dng t), thanh ghi
m TCNT1 tng t 0, khi TCNT1 bng gi tr cha trong OCR1A th mt Compare
Match xy ra. Khi , mt ngt c th xy ra nu chng ta cho php ngt Compare Match
(set bit OCF1A trong thanh ghi TIMSK ln 1). Mode ny cng tng i n gin, mt ng
dng c bn ca mode ny l n gin ha vic m cc s kin bn ngoi. V d bn kt
ni 1 sensor m s ngi i vo 1 cn phng vi chn T1 (chn counter source ca T/C1),
bn mun rng c sau khi m 5 ngi th s thng bo 1 ln. List 4 l on code m t v
d ny:
AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com
List 4. Phi hp CTC vi m s kin
#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/delay.h>
volatile usigned char val=0; //khai bao 1 bien tam val va khoi tao =0
int main(void){
DDRB=0xFF; //PORTB la output PORT
PORTB=0x00;
TCCR1B=(1<<WGM12)|(1<<CS12)|(1<<CS11);// CS12=0, CS11=0,
//CS10=1: chon Prescaler = 1
OCR1A=4; //gan gia tri can so sanh
TIMSK(1<<OCIE1A);; // cho phep ngat khi gia tri dem bang 4
sei(); //set bit I cho phep ngat toan cuc

while (1){ //vng lp v tn
//do nothing
}
return 0;
}
//trinh phuc vu ngat compare match
ISR (TIMER1_COMPA_vect ){
val++;
if (val==10) val=0; //gioi han bien val tu 0 den 9
PORTB =val; //xuat gia tri ra PORTB
}
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Ti ch gii thch nhng im mi trong List 4. Th nht l attribute volatile dng
trc khai bo bin val, bin val c khai bo l unsigned char (8 bit, khng du) dng
cha gi tr tm thi xut ra PORTB khi c ngt xy ra. iu c bit l t kha volatile
t trc n, volatile l mt thuc tnh (attribute) ca b bin dch gcc-avr, n ni vi trnh
dch rng bin val s c dng trong chng trnh chnh v c trong cc trnh phc v ngt.
Nu bn mun cp nhp gi tr 1 bin ton cc trong cc trnh phc v ngt m bin
khng c ch nh thuc tnh volatile trc th qu trnh cp nht tht bi. Mt cch d
hiu hn, bn xem trnh ISR trong v d trn, c mi ln c ngt Compare Match xy ra,
bin val c tng thm 1 (dng 21) sau kim tra iu kin bng 10 hay khng v cui
cng l gn cho PORTB. Nu trong khai bo ca val (dng 4) chng ta khng ch nh
volatile th gi tr xut ra PORTB s lun l 1 khi c ngt. Ch l iu ny ch ng it nht
l vi phin bn WinAVR thng 12 nm 2007, cc phin bn sau c th khng cn dng
volatile (ti s cp nht sau).
Dng 8 set cc bit iu khin: TCCR1B=(1<<WGM12)|(1<<CS12)|(1<<CS11); bn
thy ti ch set bit WGM12 trong 4 bit WGM v ti mun chn mode CTC 4 (xem bng 3).
Hai bit CS12 v CS11 c set bng 1 trong khi CS10 c gi 0 chn xung clock l
t bn ngoi, chn T1 (xem bng 2). Trong dng 10, OCR1A=4; l gi tr cn so snh, chng
AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com
ta bit rng TCNT1 tng ln t 0, v th m 5 s kin th cn t gi tr so snh l 4 (0, 1,
2, 3, 4). Dng 11 set bit cho php ngt khi c Compare match xy ra (dng cho channel A).
Mode 12 ca CTC (WGM13=1, WGM12=1, WGM11=0, WGM10=0) cng tng t
mode 4 nhng ci khc l gi tr cn so snh c cha trong thanh ghi ICR1 (khng phi
OCR1A hay OCR1B). Khi nu mun dng ngt th bn phi dng ngt Input capture. C
th dng 8 trong list 4 i thnh:
TCCR1B=(1<<WGM13)|( (1<<WGM12)|(1<<CS12)|(1<<CS11); dng 10: ICR1=4 v
dng 20: ISR (TIMER1_CAPT_vect ){
Mt kh nng khc ca CTC l xut tn hiu xung vung trn chn OC1A (chn 15 trn
Atmega8) bng cch set cc bit Compare Output Mode trong thanh ghi TCCR1A. Tuy nhin
vic to cc tn hiu output trong mode CTC khng tht s th v. V vy chng ta s kho
st cch to tn hiu output trong 1 ch chuyn nghip v th v hn, ch PWM.
Trc khi bt u lm vic vi cc ch PWM ti ngh cn thit gii thiu th no l
PWM v nhc li cc khi nim gi tr m ca Timer1 (hay bt k timer no khc) trn
AVR. Trc ht, PWM hay Pulse Width Modulation c hiu theo ngha ting Vit l
xung iu rng l khi nim ch tn hiu xung m thng th chu k (Time period) ca n
c c nh, duty cycle (thi thi gian tn hiu mc HIGH) ca n c th c thay i.
Bn xem 1 v d v PWM trong hnh 5.

Hnh 5. V d v tn hiu PWM.
To ra PWM tc l to ra nhng tn hiu xung m ta c th iu khin duty cycle (v
c tn s ~ Time period nu cn thit). Timer 1 trsn Atmega8 l 1 module l tng to ra
cc tn hiu dng ny. Nhng PWM dng lm g v cch m n c s dng nh th
no? Ti ly mt v d nh trong hnh 6: mt ng c DC v mt switch button.

Hnh 6. Motor v switch.
AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com
Nu nhn button th ng c hot ng, th button th ng c dng. Tuy nhin do tc
nhn v th ca con ngi c hn, bn s thy ng c hot ng hi sng (ripple).
iu g xy ra nu bn nhn v th button vi vn tc 5000 ln/giy. Cu tr li l tay bn s
b gy v button s b hng (^^). 5000 ln/s l iu khng tng, tuy nhin nu bn lm c
nh th th tng thi gian cho 1 ln nhn+th l 1:5000=0.0002s = 200us. C s khc bit
no khng gia trng hp thi gian nhn = 150us, thi gian th 50us v trng hp thi
gian nhn l 50us cn thi gian th l 150us. Bn s d dng tm cu tr li, trong trng
hp 1 ng c s quay vi vn tc nhanh hn trng hp 2. l tng c bn s dng
PWM iu khin vn tc ng c (v iu khin nhiu th khc na). bin ci khng
tng trn (5000 ln/s) thnh hin thc, chng ta s thay th ci button c kh kia bng 1
cng tc in t (electronics switch). Thng th cc chip MOSFET c dng lm cc
kha in t. MOSFET thng c 3 chn G (gate), D (drain) v S (source). V d 1
MOSFET knh N trng thi thng thng 2 chn D v S ko c dng in chy qua, nu
in p chn G ln hn chn S khong 3V tr ln th dng in c th chy t D sang S. hy
xem cch m t tng ng 1 MOSFET vi 1 button trong hnh 7.

Hnh 7. MOSFET v button.
Vic kch cc MOSFET c th thc hin bng cc tn hiu PWM. V th tng
iu khin ng c trong hnh 6 c th c thc hin li thng qua PWM nh trong hnh 8.
12V
Microcontroller
(AVR)
PWM
12V
Driver

Hnh 8. M hnh iu khin tc ng c bng PWM n gin.
Nh vy l xong phn gii thiu v PWM, by gi chng ta sang cc khi nim s m
trong Timer. Hnh 9 minh ha cch b tr cc s m trong Timer1 trn h trc m.
AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com

Hnh 9: cc mc gi tr ca T/C1.
BOTTOM lun c c nh l 0 (gi tr nh nht), MAX lun l 0xFFFF (65535).
TOP l gi tr nh do ngi dng nh ngha, gi tr ca TOP c th c c nh l 0xFF
(255), 0x1FF (511), 0x3FF 91023) hoc nh ngha bi cc thanh ghi ICR1 hoc OCR1A.
thc cht i vi ng dng PWM th TOP chnh l Time period ca PWM. Do mc ch s
dng m c th chn TOP l cc gi tr c nh hay cc thanh ghi, ring vi ti, cho mc
ch to tn hiu PWM ti chn TOP nh ngha bi thanh ghi ICR1. Ouput Compare l gi
tr so snh ca b Timer. Trong ch PWM th Output Compare quy nh Duty cycle. Vi
T/C1, Output Comapre l gi tr trong cc thanh ghi OCR1A v OCR1B. Do c 2 thanh ghi
c lp A v B, tng ng chng ta c th to ra 2 tn hiu PWM trn 2 chn OC1A v
OC1B bng T/C1. n lc chng ta tm hiu cch to PWM trn AVR.
2.3. Fast PWM (PWM tn s cao)
Trong ch Fast PWM, 1 chu k c tnh trong 1 ln m t BOTTOM ln TOP
(single-slope), v th m ch ny gi l Fast PWM (PWM nhanh). C tt c 5 mode trong
Fast PWM tng ng vi 5 cch chn gi tr TOP khc nhau (tham kho bng 3). Vic xc
lp ch hot ng cho Fast PWM thc hin thng qua 4 bit WGM v cc bit chn dng
xung ng ra, Compare Output Mode trong thanh ghi TCCR1A, nhn li 2 thanh ghi
TCCR1A v TCCR1B.



Ch cc bit COM1A1, COM1A0 v COM1B1, COM1B0 l cc bit chn dng tn
hiu ra ca PWM (Compare Output Mode bits). COM1A1, COM1A0 dng cho knh A v
COM1B1, COM1B0 dng cho knh B. Hy i chiu bng 4.
Bng 4: m t cc bit COM trong ch fast PWM.

AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com
Ti s gii thch hot ng ca Fast PWM knh A thng qua 1 trng hp c th,
mode 14 (WGM13=1, WGM12=1, WGM11=1, WGM10=0). Trong mode 14, gi tr TOP
(cng l chu k ca PWM) c cha trong thanh ghi ICR1, khi hot ng thanh ghi
TCNT1 tng gi tr t 0, gi s cc bit ph COM1A=1, COM1A0=0, lc ny trng thi ca
chn OC1A (chn 15) l HIGH (5V), khi TCNT1 tng n bng gi tr ca thanh ghi
OCR1A th chn OC1A c xa v mc LOW (0V), thanh ghi m TCNT1 vn tip tc
tng n khi no n bng gi tr TOP cha trong thanh ghi ICR1 th TCNT1 t ng reset
v 0 v chn OC1A tr v trng thi HIGH, ci ny gi l Clear OC1A/OC1B on Compare
Match, set OC1A/OC1B at TOP m bn thy trong hng 4 bng 4. Hnh 10 m t cch to
xung PWM trn chn OC1A mode 14.

Hnh 10. Fast PMW mode 14.
R rng chng ta c th iu khin c time period v duty cycle ca PWM bng 2
thanh ghi ICR1 v OCR1A. Thng thng gi tr ca ICR1 c tnh ton v gn c nh,
gi tr ca OCR1A c thay i thc hin mc ch iu khin (nh thay i vn tc
ng c). Ch l nu chng ta set cc bit ph ngc li: COM1A=0, COM1A0=1, th tn
hiu PWM trn chn OC1A s c phn LOW t 0 n OCR1A v HIGH t OCR1A n
ICR1, y gi l set OC1A/OC1B on Compare Match, clear OC1A/OC1B at TOP (ngc
vi tn hiu trn hnh 10). Hot ng ca fast PWM knh B hon ton tng t, trong
thanh ghi ICR1 cng cha TOP ca PWM knh B v thanh ghi ICR1B cha duty cycle. Nh
vy 2 knh A v B c cng tn s hay Time period v duty cycle c iu khin c lp.
Chn xut tn hiu PWM ca knh B l chn OC1B (chn 16 trn Atmega8).
Cc mode 5, 6 v 7 ca Fast PWM hot ng hon ton tng t mode 14. im khc
nhau c bn l gi tr TOP(Time period). Trong cc mode ny gi tr TOP khng do thanh
thi ICR1 nh ngha m l cc hng s khng i. Vi mode 5, tc mode 8 bits, (WGM13=0,
WGM12=1, WGM11=0, WGM10=1) gi tr TOP l 1 hng s, TOP = 255 (s 8 bits ln
nht). Vi mode 6, tc mode 9 bits, (WGM13=0, WGM12=1, WGM11=1, WGM10=0) gi
tr TOP l 1 hng s, TOP = 511 (s 9 bits ln nht). V vi mode 7, tc mode 10 bits,
(WGM13=0, WGM12=1, WGM11=1, WGM10=1) TOP =1023 (s 10 bits ln nht). Mode
15 cng l Fast PWM trong TOP do OCR1A quy nh, v th m tn hiu ra knh A hu
nh khng phi l 1 xung, n ch thay i trng thi trong 1 clock. Theo ti, s dng Fast
PWM bn nn dng mode 14 c gii thch trn. Cc mode 5, 6, 7 cng c th dng
nhng khng nn dng mode 15.
Chng ta tin hnh vit 1 v d minh ha dng 2 knh ch fast PWM iu khin 2
ng c RC servo (gi tt l Servo). Mch in minh ha nh trong hnh 11.
AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com

Hnh 11. iu khin 2 RC servo bng PWM.
Hai button c ni vi 2 ng ngt ngoi INT0 v INT1 iu khin gc xoay ca 2
Servo. Tn ca Servo trong phn mm Protues l MOTOR-PWMSERVO. Trc khi vit
code iu khin cc Servo, bn cn bit cch iu khin chng, ti gii thiu ngn gn nh
sau:
RC servo l mt t hp gm 1 ng c DC cng sut nh, hp gim tc v b iu
khin gc quay. C 2 loi chnh l Servo thng v digital Servo, trong v d ny ti gii
thiu Servo thng (ph bin). Servo thng c 3 dy, dy mu en l dy GND, dy l
dy ngun (thng l 5V) v 1 dy trng hoc vng v dy iu khin (c mt s loi Servo
c mu dy khc, bn cn tham kho datasheet ca chng). V cc Servo c sn mch
iu khin gc quay bn trong nn chng ta khng cn bt c gii thut g m ch cn cp tn
hiu PWM cho dy iu khin l Servo c th xoay n 1 v tr no (ch l Servo
thng ch xoay na vng, iu khin servo l iu khin gc xoay ch khng phi iu
khin cn tc xoay). Hnh 12 l hnh nh servo v cch iu khin servo.

Hnh 12. Servo v cch iu khin.
AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com

Bn xem hnh 12b), iu khin servo bn cn cp cho dy iu khin mt tn hiu
PWM c Time Period khong 20ms, duty cycle ca PWM s quyt nh gc xoay ca servo.
Vi Duty cycle l 1ms, servo xoay v v tr 0
o
, khi duty cycle =2ms, gc xoay s l 180
o
, t
bn c th tnh c duty cycle cn thit khi bn mun servo xoay n 1 v tr bt k gia
0
o
v 180
o
. Sau khi hiu cch iu khin servo, chng ta c th d dng vit code iu khin
chng, ch cn to cc xung PWM bng T/C1. on code cho v d ny c trnh by trong
list 5.
List 5. iu khin servo bng PWM
#include <avr/io.h>
#include <avr/interrupt.h>

int main(void){
DDRB=0xFF; //PORTB la output PORT
PORTB=0x00;

MCUCR|=(1<<ISC11)|(1<<ISC01); //ngat canh xuong
GICR |=(1<<INT1)|(1<<INT0); //cho php 2 ngat hoat dong

TCCR1A=(1<<COM1A1)|(1<<COM1B1)|(1<<WGM11);
TCCR1B=(1<<WGM13)|(1<<WGM12)|(1<<CS10);
OCR1A=1000; //Duty cycle servo1=1000us=1ms (0 degree)
OCR1B=1500; //Duty cycle servo2=1500us=1.5ms (90 degree)
ICR1=20000; //Time period = 20000us=20ms

sei(); //set bit I cho phep ngat toan cuc
while (1){ //vng lp v tn
//do nothing
}
return 0;
}

//trinh phuc vu ngat ngoai
ISR (INT0_vect ){
if (OCR1A==1000) OCR1A=1500; //thay doi goc xoay servo1 den 90 do
else OCR1A = 1000; // thay doi goc xoay servo1 den 0 do
}
ISR (INT1_vect ){
if (OCR1B==1000) OCR1B=1500; //thay doi goc xoay servo1 den 90 do
else OCR1B = 1000; // thay doi goc xoay servo1 den 0 do
}
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Vi v d ny ti ch cn gii thch cc dng t 11 n 15 lin quan n vic xc lp
ch hot ng Fast PWM mode 14 inverse, phn cn li bn c t i chiu vi cc bi
AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com
trc. Dng 11 v 12 thc hin set cc bit iu khin Timer1, trc ht l cc bit COM. Bn
thy ti ch set 2 bit COM1A1 v COM1B1: (1<<COM1A1)|(1<<COM1B1). Hai bit
COM1A0 v COM1B0 khng set tc mc nh bng 0. i chiu vi bng 4 bn thy chng
ta s dng Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at TOP cho tt c 2
knh A v B. Chng ta set 3 bit WGM13, WGM12 (thanh ghi TCCR1B, dng 12) v
WGM11 (thanh ghi TCCR1A, dng 11) nh th thu c t hp (WGM13=1, WGM12=1,
WGM11=1, WGM10=0) tc l mode 14 c chn (bng 3). Cn li chng ta set bit CS10
khai bo rng ngun xung clock cho Timer1 bng clock cho vi iu khin (prescaler=1)
tc l 1us trong tng hp f=1Mhz. (nu bn dng cc trnh bin dch khc khng h tr
nh ngha tn cc bit th 2 dng 11 v 12 tng ng: TCCR1A=0xA2; TCCR1B=0x19).
Dng 15 chng ta khai nhp gi tr cho ICR1 cng l Time period cho PWM,
ICR1=20000 chng ta thu c Time period =20000 us = 20ms tha yu cu ca servo. Hai
dng 13 v 14 khai bo gi tr ban u ca cc duty cycle ca 2 knh PWM, cc gi tr ny
nh v tr gc xoay ca cc servo. Trong 2 trnh phc v ngt, cc gi tr ny c thay i
khi cc button c nhn.

2.4. Phase correct PWM (PWM vi pha chnh xc)
Phase correct PWM cung cp mt ch to xung PWM c phn gii cao (high
resolution) nn c gi l Phase correct PWM. Tng t Fast PWM, cng c 5 mode hot
ng thuc Phase correct PWM l cc mode 1, 2, 3, 10 v 11 (xem bng 3). Nm mode
ny tng ng cc mode 5, 6, 7, 14 v 15 ca fast PWM. V cch iu khin, Phase correct
hu nh ging fast PWM, ngha l nu bn bit cch s dng cc mode ca fast PWM th
bn s hon ton iu khin c Phase correct PWM. Khc nhau c bn ca 2 ch ny
l trong cch hot ng, nu Fast PWM c chu k hot ng trong 1 single-slope (mt sn)
th Phase correct PWM li dual-slope (hai sn). Ly v d mode 10 ca Phase correct PWM
tng ng vi mode 14 ca Fast PWM, trong mode ny thanh ghi ICR1 cha TOP v
OCR1A (hoc OCR1B i vi knh B) cha gi tr so snh. Khi hot ng, thanh ghi
TCNT1 tng t 0, khi TCNT1 bng vi OCR1A th chn OC1A c xa xung mc LOW
(ti ang ni trng hp COM1A1=1, COM1A0=0), TCNT1 tip tc tng n TOP, khi
TCNT1=TOP th TCNT1 KHNG c t ng reset v 0 nh trng hp Fast PWM m
TCNT1 bt u m ngc, tc gim tng gi tr t TOP v 0. Trong lc TCNT1 gim, n
1 lc n s bng gi tr ca OCR1A ln th 2, v ln ny, chn OC1A c set ln mc
HIGH, TCNT1 tip tc gim n 0 th 1 chu k hon tt. R rng 1 chu k l qu trnh m
trong 2 sn nn ta gi Phase correct PWM l dual-slope. Cng v tnh cht dual-slope m
tn hiu PWM trong ch ny c tnh i xng, thch hp cho cc ng dng iu khin
ng c. Hnh 13 m t cch m Phase correct PWM hot ng tron mode 10 vi ng ra o
(COM1A1=1, COM1A0=0).
AUTO.NLU

For more details and questions, contact me: thanhtam.h@gmail.com
T
C
N
T
1

Hnh 13. Phase correct PWM mode 10.
Vic vit code cho ch Phase correct PWM gn nh tng t fast PWM, bn ch
cn thay i t hp cc bit WGM da theo bng 3 v sau nhp cc gi tr ph hp cho
ICR1 v ORC1A, OCR1B l c.
2.5. Phase correct and frequency correct PWM
Ch ny c 2 mode l 8 v 9. V hu ht cc phng din, 2 mode ny ging vi 2
mode 10 v 11 ca Phase correct PWM. Ci khc nhau duy nht l thi im m thanh ghi
OCR1A v OCR1B c cp nht d liu nu c s thay i. Vic ny, nhn chung khng
nh hng n hu ht ngi dng PWM iu khin. Bn s rt kh thy s khc bit
nu bn khng phi ang vit 1 ng dng m sai s trong 1 micro giy l iu t hi. V th
ti khng cp chi tit ch ny, bn c c th tham kho datasheet ca chip hiu r
hn nu cn thit.

Ngoi ra trn chip atmega8 cn c b timer2 8 bits c PWM v asynchronous operation. V
mt chc nng timer2 ging nh phin bn 8 bit ca timer1 ( phn gii thp hn nhng c cng
ch v phng thc hot ng). im khc bit v cng l im c bit ca Timer2 l kh
nng hot ng khng ng b vi chip, n ging nh vic bn tch timer2 ra thnh 1 chip timer
ring, v th cn cung cp 1 ngun xung clock khc cho timer ny (1 thch anh khc). Ch ny
c th c dng calip (calibrate), canh chnh sai s v b cho ngun xung clock chnh trn
chip.
Ti xin kt thc bi 4 v timer v PWM y, trong bi AVR5 ti s trnh by cch s dng
b chuyn i Analog to Digital 10 bit trn cc chip AVR cng nh b so snh analog. Enjoy.