DESIGN OF SEQUENCE DETECTOR USING MEALY AND

MOORE TYPE STATE MACHINES.

(a)Mealy finite tate !a"#ine$
Ai!$ To design a 1011 sequence detector with a mealy type finite state machine using verilog.
C%&e$
module fsmmealy1011( clk,rst,inp,outp);
input clk,rst,inp;
output outp;
reg 1!0"state;
reg outp;
always#(posedge clk or posedge rst)
if(rst)
$egin
state%&'$00;
outp%0;
end
else
$egin
case(state)
&'$00!if(inp)
$egin
state%&'$01;
outp%0;
end
else
$egin
state%&'$00;
outp%0;
end
&'$01!if(inp)
$egin
state%&'$01;
outp%0;
end
else
$egin
state%&'$10;
outp%0;
end
&'$10!if(inp)
$egin
state%&'$11;
outp%0;
end
else
$egin
state%&'$00;
outp%0;
end
&'$11!if(inp)
$egin
state%&'$01;
outp%1;
end
else
$egin
state%&'$10;
outp%0;
end
default!
$egin
state%&'$00;
outp%0;
end
endcase
end
endmodule
Tet 'en"#$
module fsmsd(t$;
reg clk,rst,inp;
wire outp;
reg 1)!0" sequences;
integer i;
fsmmealy1011 test(clk,rst,inp,outp);
initial
$egin
clk%0;
rst%1;
i%0;
sequences%1*'$1010101110111001;
+) rst%0;
while(i,%1))
$egin
inp%sequencesi";
+& clk%1;+& clk%0;i%i-1;
end
end
endmodule
Re(lt$ . 1011 sequence detector using mealy type state machine has $een designed and
verified using verilog.
Si)nal fl%*$
(')M%%+e finite tate !a"#ine$
Ai!$ To design a 1011 sequence detector with a moore type finite state machine using verilog.
C%&e$
module fsmmoore1011( clk,rst,inp,outp);
input clk,rst,inp;
output outp;
reg &!0"state;
reg outp;
always#(posedge clk or posedge rst)
if(rst)
$egin
state%&'$000;
outp%0;
end
else
$egin
case(state)
/'$000!if(inp)
$egin
state%/'$001;
outp%0;
end
else
$egin
state%/'$000;
outp%0;
end
/'$001!if(inp)
$egin
state%/'$001;
outp%0;
end
else
$egin
state%/'$010;
outp%0;
end
/'$010!if(inp)
$egin
state%/'$011;
outp%0;
end
else
$egin
state%/'$000;
outp%0;
end
/'$011!if(inp)
$egin
state%/'$100;
outp%0;
end
else
$egin
state%/'$010;
outp%0;
end
/'$100!if(inp)
$egin
state%/'$001;
outp%1;
end
else
$egin
state%/'$011;
outp%1;
end
default!
$egin
state%/'$000;
outp%0;
end
endcase
end
endmodule
Tet 'en"#$
module fsmmoore(t$;
reg clk,rst,inp;
wire outp;
reg 1)!0" sequences;
integer i;
fsmmoore1011 test(clk,rst,inp,outp);
initial
$egin
clk%0;
rst%1;
i%0;
sequences%1*'$1010101110111001;
+) rst%0;
while(i,%1))
$egin
inp%sequencesi";
+& clk%1;+& clk%0;i%i-1;
end
end
endmodule
Re(lt$ . 1011 sequence detector using moore type state machine has $een designed and
verified using verilog.
Si)nal fl%*$
DESIGN OF SYNCHRONOUS COUNTERS$
(a)Dei)n %f a yn"#+%n%( (, "%(nte+$
Ai!$To design a 01$it synchronous up counter using verilog.
C%&e$
module upcounter(clk,reset,2);
input clk,reset;
output reg /!0"2;
initial
2%0'$0000;
always#(posedge clk)
$egin
if(3reset)
2,%2-1;
else
2,%0;
end
endmodule
Tet 'en"#$
module t$;
reg clk,reset;
wire /!0"2;
upcounter pav(clk,reset,2);
initial
$egin
4clk,reset5%0;
end
always
+)0 4clk5%64clk5;
always
+1)00 4reset5%4reset5-1;
endmodule
Re(lt$. 01$it synchronous up counter has $een designed and verified using verilog.
Si)nal Fl%*$
(')Dei)n %f a yn"#+%n%( &%*n "%(nte+$
Ai!$To design a 01$it synchronous down counter using verilog.
C%&e$
module downcounter(clk,reset,2);
input clk,reset;
output reg /!0"2;
initial
2%0'$1111;
always#(posedge clk)
$egin
if(3reset)
2,%211;
else
2,%0;
end
endmodule
module t$;
reg clk,reset;
wire /!0"2;
downcounter pav(clk,reset,2);
initial
$egin
4clk,reset5%0;
end
always
+)0 4clk5%64clk5;
always
+1)00 4reset5%4reset5-1;
endmodule
Re(lt$. 01$it synchronous down counter has $een designed and verified using verilog.
Si)nal Fl%*$
PROGRAM TO REALI-E A ./0ARIA1LE FUNCTION$
(a)S(! %f ,+%&("t f%+!$
Ai!$To reali7e the 8oolean function 2(345464748848548948.) using verilog.
C%&e$
module reali7ation9:;(<,2);
input /!0"<;
output 2;
reg 2;
always#(<)
$egin
if(<%%0==<%%&==<%%>==<%%?==<%%11==<%%1&==<%%1/==<%%10)
2%1;
else
2%0;
end
endmodule
Tet 'en"#$
module reali7ation9:;(t$;
reg /!0"<;
wire 2;
reali7ation9:; t$(<,2);
initial
<%0'$0000;
always
$egin
<%<-1;
+)0;
end
endmodule
Re(lt$ The given 0 varia$le 9:; $oolean function has $een reali7ed using verilog.
Si)nal Fl%*!

(')P+%&("t %f (! f%+!$
Ai!: To reali7e the $oolen function : (348494;4<48848;) using verilog.
C%&e$
module reali7ation;:9(<,2);
input /!0"<;
output 2;
reg 2;
always#(<)
$egin
if(<%%0==<%%1==<%%/==<%%)==<%%@==<%%11==<%%1))
2%0;
else
2%1;
end
endmodule
module reali7ation;:9(t$;
reg /!0"<;
wire 2;
Tet 'en"#$
reali7ation;:9 t$(<,2);
initial
<%0'$0000;
always
$egin
<%<-1;
+100;
end
endmodule
Re(lt$ The given 0 varia$le ;:9 $oolean function has $een reali7ed using verilog.
Si)nal Fl%*$

PROGRAM TO DESIGN AN 6=8 MULTIPLE=ER USING T>O
.=8 MULTIPLE=ERS$
Ai!$To design an ><1 AB< using two 0<1 multipleCers using verilog.
C%&e$
module AB<0<1(D,2,E,9);
input /!0"D;
input E;
input 1!0"9;
output reg 2;
always#(D or E or 9)
$egin
if(E)
if(91")
if(90")
2%D/";
else
2%D&";
else
if(90")
2%D1";
else
2%D0";
else
2%0;
end
endmodule
module AB<><1(D,9,2);
input @!0"D;
input &!0"9;
output 2;
wire 21,2&;
AB<0<1 a1(D/!0",21,69&",91!0");
AB<0<1 a&(D@!0",2&,9&",91!0");
or (2,21,2&);
endmodule
Tet 'en"#$
module AB<><1(t$;
reg @!0"D;
reg &!0"9;
wire 2;
AB<><1 t$(D,9,2);
initial
4D,95%0;
always
$egin
4D,95%4D,95-1;
+&0;
end
endmodule
Re(lt$.n ><1 multipleCer has $een designed using two 0<1 multipleCers and verified using
verilog.
Si)nal Fl%*$
PROGRAM TO DESIGN AN 6=9 PRIORITY ENCODER$
Ai!$To design an ></ priority encoder using verilog.
C%&e$
module priorityencoder></(<,2,F);
input @!0"<;
output reg &!0"2;
output reg F;
always#(<)
$egin
F%1;
caseC(<)
>'$1CCCCCCC!2%/'$111;
>'$01CCCCCC!2%/'$110;
>'$001CCCCC!2%/'$101;
>'$0001CCCC!2%/'$100;
>'$00001CCC!2%/'$011;
>'$000001CC!2%/'$010;
>'$0000001C!2%/'$001;
>'$00000001!2%/'$000;
default!
$egin
F%0;
2%/'$CCC;
end
endcase
end
endmodule
Tet 'en"#$
module pen></(t$;
reg @!0"<;
wire &!0"2;
wire F;
priorityencoder></ t$(<,2,F);
initial
<%0;
always
$egin
<%<-1;
+10;
end
endmodule
Re(lt$.n ></ priority encoder has $een designed and verified using verilog.
Si)nal Fl%*$
LOGIC SYNTHESIS OF 1ASIC GATES
AIM$To perform logic synthesis of $asic logic gates
RTL "#e!ati"$
Te"#n%l%)y "#e!ati"$
C+iti"al ,at#$
Netlit$
(edif gates
(edifGersion & 0 0)
(edifHevel 0)
(keywordAap (keywordHevel 0))
(status
(written
(timestamp &010 10 /0 0@ 0? )*)
(program IHeonardo9pectrum Hevel /I (version I&010a.@I))
(author IAentor JraphicsI)))
(eCternal ;KDADTDGE9
(edifHevel 0)
(technology (num$erLefinition )))
(eCternal ami0)(typ
(edifHevel 0)
(technology (num$erLefinition ))
(cell nor0&ii (cellType JEMEKDN)
(view METHD9T (viewType METHD9T)
(interface
(port .0 (direction DM;BT))
(port .1 (direction DM;BT))
(port 2 (direction :BT;BT)))))
(cell and0& (cellType JEMEKDN)
(view METHD9T (viewType METHD9T)
(interface
(port .0 (direction DM;BT))
(port .1 (direction DM;BT))
(port 2 (direction :BT;BT)))))
(cell or0& (cellType JEMEKDN)
(view METHD9T (viewType METHD9T)
(interface
(port .0 (direction DM;BT))
(port .1 (direction DM;BT))
(port 2 (direction :BT;BT)))))
(cell inv0& (cellType JEMEKDN)
(view METHD9T (viewType METHD9T)
(interface
(port . (direction DM;BT))
(port 2 (direction :BT;BT))))))
(li$rary ravichandra(li$
(edifHevel 0)
(technology (num$erLefinition ))
(cell gates (cellType JEMEKDN)
(view DMTEKO.NE (viewType METHD9T)
(interface
(port a (direction DM;BT))
(port $ (direction DM;BT))
(port y1 (direction :BT;BT))
(port y& (direction :BT;BT))
(port y/ (direction :BT;BT))
(port y0 (direction :BT;BT)))
(contents
(instance iC? (viewKef METHD9T (cellKef nor0&ii (li$raryKef ami0)(typ ))))
(instance iC) (viewKef METHD9T (cellKef and0& (li$raryKef ami0)(typ ))))
(instance iC/ (viewKef METHD9T (cellKef or0& (li$raryKef ami0)(typ ))))
(instance iC11@ (viewKef METHD9T (cellKef inv0& (li$raryKef ami0)(typ ))))
(net a
(Poined
(portKef a )
(portKef .1 (instanceKef iC) ))
(portKef .0 (instanceKef iC/ ))
(portKef . (instanceKef iC11@ ))))
(net $
(Poined
(portKef $ )
(portKef .0 (instanceKef iC) ))
(portKef .1 (instanceKef iC/ ))))
(net y1
(Poined
(portKef y1 )
(portKef 2 (instanceKef iC) ))
(portKef .0 (instanceKef iC? ))))
(net y&
(Poined
(portKef y& )
(portKef 2 (instanceKef iC/ ))
(portKef .1 (instanceKef iC? ))))
(net y/
(Poined
(portKef y/ )
(portKef 2 (instanceKef iC? ))))
(net y0
(Poined
(portKef y0 )
(portKef 2 (instanceKef iC11@ ))))))))
(design gates (cellKef gates (li$raryKef ravichandra(li$ )))
A+ea +e,%+t$
QQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQ
Nell! gates Giew! DMTEKO.NE Hi$rary! ravichandra(li$
QQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQ
Nell Hi$rary Keferences Total .rea
;adDnN ami0)(typ & C
;ad:ut ami0)(typ 0 C
$uf0& ami0)(typ / C 1 / gates
inv0& ami0)(typ 1 C 1 1 gates
nand0&(&C ami0)(typ 1 C 1 1 gates
nor0&ii ami0)(typ & C 1 & gates
Mum$er of ports ! *
Mum$er of nets ! 1)
Mum$er of instances ! 1/
Mum$er of references to this view ! 0
Total accumulated area !
Mum$er of gates ! @
Mum$er of accumulated instances ! 1/
M: wire ta$le is found
PROGRAM TO GENERATE RECTANGULAR
>A0EFORM
AIM$ To generate rectangular wave form.
0ERILOG CODE$
module rectangle;
parameter T:M%10,T:OO%);
reg clk;
initial
clk%1'$0;
always
$egin
+T:OO clk%1'$0;
+T:M clk%1'$1;
end
endmodule
>A0EFORM
RESULT$ Kectangular wave is generated using verilog hdl.
PROGRAM TO GENERATE SQUARE >A0EFORM
AIM$To generate square wave form.
0ERILOG CODE$
module square;
parameter T:M%),T:OO%);
reg clk;
initial
clk%1'$0;
always
$egin
+T:OO clk%1'$0;
+T:M clk%1'$1;
end
endmodule
>A0EFORM$
RESULT$
9quare waveform is generated using verilog hdl.