1

Digital Logic Circuits

2 marks
1) Given the two binary numbers X = 1010100 and = 1000011! "er#orm the subtraction $a)
X % and $b) % X using 2&s com"lements'
a) X = 1010100
2s complement of Y = + 0111101 --------------
Sum = 10010001
Discard end carry
Answer X - Y = 0010001
!) Y = 1000011
2s complement of X = + 0101100 ---------------
Sum = 1101111
"#ere is no end carry$
"#erefore t#e answer is Y-X = -%2s complement of 1101111) = -0010001
2)' Given the two binary numbers X = 1010100 and = 1000011! "er#orm the subtraction $a)
X % and $b) % X using 1&s com"lements'
a)& X - Y = 1010100 ' 1000011
X = 1010100
1s complement of Y = + 0111100 --------------
Sum = 10010000
(nd -around carry = + 1 --------------
Answer X - Y = 0010001
!)& Y - X = 1000011 ' 1010100
Y = 1000011
1s complement of X = + 0101011 -----------
Sum = + 1101110
"#ere is no end carry&
"#erefore t#e answer is Y - X = -%1s complement of 1101110) = -0010001
()' what is meant by "arity bit)
A parity !it is an e)tra !it included wit# a messa*e to ma+e t#e total num!er of 1s eit#er
e,en or odd& -onsider t#e followin* two c#aracters and t#eir e,en and odd parity .it# e,en parity
wit# odd parity AS-// A = 1000001 01000001 11000001$ AS-// " = 1010100 11010100
01010100& /n eac# case we add an e)tra !it in t#e left most position of t#e code to produce an e,en
num!er of1s in t#e c#aracter for e,en parity or an odd num!er of 1s in t#e c#aracter for odd
parity& "#e parity !it is #elpful in detectin* errors durin* t#e transmission of information from one
location to anot#er&
*)'+hat are registers)
0e*ister is a *roup of !inary cells& A re*ister wit# n cells can store any discrete 1uantity of
information t#at contains n !its& "#e state of a re*ister is an n-tuple num!er of 1s and 0s$ wit#
eac# !it desi*natin* t#e state of one cell in t#e re*ister&
,)' +hat is meant by register trans#er)
A re*ister transfer operation is a !asic operation in di*ital systems& /t consists of transfer of
!inary information from one set of re*isters into anot#er set of re*isters& "#e transfer may !e direct
from one re*ister to anot#er$ or may pass t#rou*# data processin* circuits to perform an operation&
-)' De#ine binary logic)
2
2inary lo*ic consists of !inary ,aria!les and lo*ical operations& "#e ,aria!les are desi*nated
!y t#e alp#a!ets suc# as A$ 2$ -$ )$ y$ 3$ etc&$ wit# eac# ,aria!le #a,in* only two distinct ,alues 1
and 0& "#ere are t#ree !asic lo*ic operations A4D$ 50$ and 45"&
.)' De#ine logic gates)
6o*ic *ates are electronic circuits t#at operate on one or more input si*nals to produce an
output si*nal& (lectrical si*nals suc# as ,olta*es or currents e)ist t#rou*#out a di*ital system in
eit#er of two reco*ni3a!le ,alues& 7olta*e- operated circuits respond to two separate ,olta*e le,els
t#at represent a !inary ,aria!le e1ual to lo*ic 1 or lo*ic 0&
/)'De#ine duality "ro"erty'
Duality property states t#at e,ery al*e!raic e)pression deduci!le from t#e postulates of
2oolean al*e!ra remains ,alid if t#e operators and identity elements are interc#an*ed& /f t#e dual of
an al*e!raic e)pression is desired$ we simply interc#an*e 50 and A4D operators and replace 1s
!y 0s and 0s !y 1s&
0)'1ind the com"lement o# the #unctions 1
1
= 2&y3& 4 2&y&3 and 1
2
= 2$y&3& 4 y3) by a""lying De
5organ&s theorem as many times as necessary'
8
1
= %)y3 + )y3) = %)y3)%)y3) = %) + y + 3)%) + y +3)
8
2
= 9)%y3 + y3): = ) + %y3 + y3) = ) + %y3)%y3)
= ) + %y + 3)%y + 3)
10)'1ind the com"lements o# the #unctions 11 = 2&y3& 4 2&y&3 and 12 = 2$y&3& 4 y3) by taking
their duals and com"lementing each literal'
81= )y3 + )y3& "#e dual of 81 is %) + y + 3)%) + y + 3)&
-omplementin* eac# literal %) + y + 3)%) + y + 3)
82= )%y3 + y3)& "#e dual of 82 is ) + %y + 3)%y + 3)&
-omplement of eac# literal ) + %y + 3)%y + 3)
11)'6tate De 5organ&s theorem'
De ;or*an su**ested two t#eorems t#at form important part of 2oolean al*e!ra& "#ey are$
1) "#e complement of a product is e1ual to t#e sum of t#e complements& %A2) = A + 2 2) "#e
complement of a sum term is e1ual to t#e product of t#e complements& %A + 2) = A2
12)'7educe 8'8&C
A&A- = 0&c 9A&A = 1: = 0
1()' 7educe 8$8 4 9)
A%A + 2) = AA + A2 = A%1 + 2) 91 + 2 = 1: = A&
1*' 7educe 8&9&C& 4 8&9C& 4 8&9C
A2- + A2- + A2- = A-%2 + 2) + A2- = A- + A2- 9A + A = 1:
= A%- + 2-) = A%- + 2) 9A + A2 = A + 2:
1,') 7educe 89 4 $8C)& 4 89&C$89 4 C)
A2 + %A-) + A2-%A2 + -) = A2 + %A-) + AA22- + A2--
= A2 + %A-) + A2-- 9A&A = 0:
= A2 + %A-) + A2- 9A&A = 1:
= A2 + A + - =A2- 9%A2) = A + 2:
= A + 2 + - + A2- 9A + A2 = A + 2:
= A + 2- + 2 + - 9A + A2 = A + 2:
= A + 2 + - + 2-
=A + 2 + - + 2
=A + - + 1
= 1 9A + 1 =1:
(
1-' 6im"li#y the #ollowing e2"ression = $8 4 9)$8 4 C& )$9& 4 C& )
Y = %A + 2)%A + - )%2 + - )
= %AA + A- +A2 +2- )%2 + -) 9A&A = 0:
= %A- + A2 + 2-)%2 + - )
= A2- + A-- + A22 + A2- + 22- + 2--
= A2- + A2-
1.)'6im"li#y the #ollowing using De 5organ&s theorem :$$89)&C)&& D;&
9%%A2)-) D: = %%A2)-) + D 9%A2) = A + 2:
= %A2) - + D
= %A + 2 )- + D
1/'6how that $X 4 & 4 X)$ X 4 &)$X&) = 0
%X + Y + XY)% X + Y)%XY) = %X + Y + X)%X + Y )%X + Y) 9A + A2 = A + 2:
= %X + Y )%X + Y )%XY) 9A + A = 1:
= %X + Y )%XY) 9A&A = 1:
= X&X + Y&X&Y
= 0 9A&A = 0:
10)'<rove that 89C 4 89C& 4 89&C 4 8&9C = 89 4 8C 4 9C
A2- + A2- + A2- + A2- =A2%- + -) + A2- + A2-
=A2 + A2- + A2-
=A%2 + 2-) + A2-
=A%2 + -) + A2-
=A2 + A- + A2-
=2%A + -) + A-
=A2 + 2- + A-
=A2 + A- +2- &&&<ro,ed
20)'Convert the given e2"ression in canonical 6=< #orm = 8C 4 89 4 9C
Y = A- + A2 + 2-
=A-%2 + 2 ) + A2%- + - ) + %A + A)2-
=A2- + A2- + A2- + A2- + A2- + A2- + A2-
=A2- + A2- +A2- + A2- 9A + A =1:
21)'Convert the given e2"ression in canonical <=6 #orm = $ 8 4 9)$9 4 C)$8 4 C)
Y = % A + 2)%2 + -)%A + -)
= %A + 2 + -&- )%2 + - + A&A )%A + 2&2 + -)
= %A + 2 + -)%A + 2 + - )%A + 2 +-)%A + 2 +-)%A + 2 + -)%A + 2 + -) 9A + 2- = %A
+ 2)%A + -) Distri!uti,e law:
= %A + 2 + -)%A + 2 + -)%A + 2 + -)%A + 2 + -)%A + 2 + -)
22)' 1ind the minterms o# the logical e2"ression = 8&9&C& 4 8&9&C 4 8&9C 4 89C&
Y = A2- + A2- + A2- + A2- =m0 + m1 +m= +m> =?<@@@@@@@@@@@@
2()'+rite the ma2terms corres"onding to the logical e2"ression = $8 4 9 4 C& )$8 4 9& 4
C&)$8& 4 9& 4 C)
Y = %A + 2 + - )%A + 2 + -)%A + 2 + -) =;1&;=&;> =A0@@@@@@@
2*)'Convert $*021'2)
B
to its e1ui,alent decimal&
%C021&2)
B
= C ) B
=
+ 0 ) B
2
+ 2 ) B
1
+ 1 ) B
0
+ 2 ) B
-1
= %B11&C)
10

*
2,) >sing 10&s com"lement subtract .2,(2 ? (2,0
; = D2B=2 10s complement of 4 = + E>DB0 -----------
Sum = 1>E2F2
Discard end carry
Answer = >E2F2
2-) +hat are called don&t care conditions)
/n some lo*ic circuits certain input conditions ne,er occur$ t#erefore t#e correspondin*
output ne,er appears& /n suc# cases t#e output le,el is not defined$ it can !e eit#er #i*# or low&
"#ese output le,els are indicated !y GX orGd in t#e trut# ta!les and are called dont care conditions
or incompletely specified functions&
2.) +rite down the ste"s in im"lementing a 9oolean #unction with levels o# @8@D Gates)
Simplify t#e function and e)press it in sum of products& Draw a 4A4D *ate for eac#
product term of t#e e)pression t#at #as at least two literals& "#e inputs to eac# 4A4D *ate are t#e
literals of t#e term& "#is constitutes a *roup of first le,el *ates& Draw a sin*le *ate usin* t#e A4D-
in,ert or t#e in,ert-50 *rap#ic sym!ol in t#e second le,el$ wit# inputs comin* from outputs of first
le,el *ates& A term wit# a sin*le literal re1uires an in,erter in t#e first le,el& How e,er if t#e sin*le
literal is complemented$ it can !e connected directly to an input of t#e second le,el 4A4D *ate&
2/) Give the general "rocedure #or converting a 9oolean e2"ression in to multilevel @8@D
diagram)
Draw t#e A4D-50 dia*ram of t#e 2oolean e)pression& -on,ert all A4D *ates to 4A4D
*ates wit# A4D-in,ert *rap#ic sym!ols& -on,ert all 50 *ates to 4A4D *ates wit# in,ert-50
*rap#ic sym!ols& -#ec+ all t#e !u!!les in t#e same dia*ram& 8or e,ery !u!!le t#at is not
compensated !y anot#er circle alon* t#e same line$ insert an in,erter or complement t#e input
literal&
20) +hat are combinational circuits)
A com!inational circuit consists of lo*ic *ates w#ose outputs at any time are determined
from t#e present com!ination of inputs& A com!inational circuit performs an operation t#at can !e
specified lo*ically !y a set of 2oolean functions& /t consists of input ,aria!les$ lo*ic *ates$ and
output ,aria!les&
(0) Give the design "rocedures #or the designing o# a combinational circuit'
"#e procedure in,ol,es t#e followin* steps$ 8rom t#e specification of t#e circuit$ determine
t#e re1uired num!er of inputs and outputs and assi*n a sym!ol to eac#& Deri,e t#e trut# ta!le t#at
defines t#e re1uired relations#ips !etween inputs and outputs& 5!tain t#e simplified 2oolean
functions for eac# output as a function of t#e input ,aria!les& Draw t#e lo*ic dia*ram and ,erify t#e
correctness of t#e desi*n&
(1) De#ine hal# adder'
A com!inational circuit t#at performs t#e addition of two !its is called a #alf adder& A #alf
adder needs two !inary inputs and two !inary outputs& "#e input ,aria!les desi*nate t#e au*end and
addend !itsI t#e output ,aria!les produce t#e sum and carry
(2) De#ine #ull adder)
A com!inational circuit t#at performs t#e adtion of t#ree !its is a full adder&/t consists of
t#ree inputs and two outputs&
(() De#ine binary adder'
A !inary adder is a di*ital circuit t#at produces t#e arit#metic sum of two !inary num!ers& /t
can !e constructed wit# full adders constructed in cascade$ wit# t#e output carry from eac# full
adder connected to t#e input carry of t#e ne)t full adder in t#e c#ain&
,
(*) +hat is over#low)
5,er flow is a pro!lem in di*ital computers !ecause t#e num!er of !its t#at #old t#e num!er
is finite and a result t#at contains n + 1 !its cannot !e accommodated& 8or t#is reason many
computers detect t#e occurrence of an o,erflow$ and w#en it occurs a correspondin* flip flop is set
t#at can !e c#ec+ed !y t#e user& An o,erflow condition can !e detected !y o!ser,in* t#e carry into
si*n !it position and t#e carry out of t#e si*n !it position& /f t#ese two carries are not e1ual$ an
o,erflow #as occurred&
(,) De#ine magnitude com"arator)
A ma*nitude comparator is a com!inational circuit t#at compares two num!ers$ A and 2$
and determines t#eir relati,e ma*nitudes& "#e outcome of t#e comparison is specified !y t#ree
!inary ,aria!les t#at indicate w#et#er aJ!$ A = !$ or A K 2&
(-) +hat are decoders)
A decoder is a com!inational circuit t#at con,erts !inary information from n input lines to a
ma)imum of 2n uni1ue output lines& /f t#e n !it coded information #as unused com!inations$ #e
decoder may #a,e fewer t#an 2n outputs&
(.) +hat are encoders)
An encoder is a di*ital circuit t#at performs t#e in,erse operation of a decoder& An encoder
#as 2n and n output lines& "#e output lines *enerate t#e !inary code correspondin* to t#e input
,alue&
(/) De#ine "riority encoder)
A priority encoder is an encoder circuit t#at includes t#e priority function& "#e operation of
priority encoder is suc# t#at if two or more inputs are e1ual to 1 at t#e same time$ t#e input #a,in*
t#e #i*#est priority will ta+e precedence&
(0) De#ine multi"le2er)
A multiple)er is com!inational circuit t#at selects !inary information from one of many
input lines and directs it to a sin*le output line& "#e selection of a particular input line is controlled
!y a set of selection lines& 4ormally t#ere are 2n input lines and n selection lines w#ose !it
com!inations determine w#ic# input is selected&
*0) De#ine binary decoder)
A decoder w#ic# #as an n- !it !inary input code and a one acti,ated output out-of -2n output
code is called !inary decoder& A !inary decoder is used w#en it is necessary to acti,ate e)actly one
of 2n outputs !ased on an n-!it input ,alue&
*1' 7e"resent binary number 1101 % 101 in "ower o# 2 and #ind its decimal eAuivalent
4 = 1 ) 2 = + 1 ) 2 2 + 0 ) 2 1 + 1 ) 2 0 + 1 ) 2 -1 + 0 ) 2 -2 + 1 ) 2 -= = 1=&>2B 10
*2' Convert $-(*) / to binary
> = C
110 011 100
Ans = 110 011 100
*(' Convert $0 9 2 % 18) B to its decimal eAuivalent'
4 = E ) 1> 2 + 2 ) 1> 1 + 2 ) 1> 0 + 1 ) 1> -1 + A %10) ) 1> -2
= 2=0C + 1D> + 2 + 0&0>2B + 0&0=E
= 2CF2&1 10
**' +hat are the di##erent classi#ications o# binary codes)
1& .ei*#ted codes 2& 4on - wei*#ted codes =& 0eflecti,e codes C& Se1uential codes B&
Alp#anumeric codes >& (rror Detectin* and correctin* codes
-
*,' Convert 0'-*0-2, decimal number to its octal eAuivalent'
0&>C0>2B ) F = B&12B
0&12B ) F = 1&0
Ans& = 0&>C0 >2B 10 = 0&B1
*-' Convert 0'12/00-2 decimal number to its he2 eAuivalent
0&12FE0>2 ) 1> = 2&0>2B 0&0>2B ) 1>
= 1&0
Ans& = 0&21 1>
*.' Convert decimal number 22'-* to he2adecimal number'
1> 22 ->
1> 1 -1
0
0&>C ) 1> = 10&2C
0&2C ) 1> = =&FC
0&FC ) 1> = 1=&CC
&CC ) 1> = D&0C
Ans& = %1> & A = D D) 1>&=
*/' +hat are the two ste"s in Gray to binary conversion)
"#e ;S2 of t#e !inary num!er is t#e same as t#e ;S2 of t#e *ray code num!er& So write it
down&"o o!tain t#e ne)t !inary di*it$ perform an e)clusi,e 50 operation !Ln t#e !it Must written
down and t#e ne)t *ray code !it& .rite down t#e result&
*0' Convert gray code 101011 into its binary eAuivalent'
Nray -ode 1 0 1 0 1 1 2inary -ode 1 1 0 0 1 0
,0' Convert 10111011 is binary into its eAuivalent gray code'
2inary -ode 1 0 1 1 1 0 1 0 1 1
Nray code 1 1 1 0 0 1 1 0
1 0 1 0
0 0 1 1
1 1 0 1
,2' 6ubstract $0 1 0 1) 2 #rom $1 0 1 1) 2
1 0 1 0 0 1 0 1 0 1 1 0
,(' 1ind 2&6 com"lement o# $1 0 1 0 0 0 1 1) 2
0 1 0 1 1 1 0 0 1 1s -omplement
+ 0 0 0 0 0 0 0 1
0 1 0 1 1 1 0 1 0 2s complement&
,*' 6ubstract 1 1 1 0 0 1 2 #rom 1 0 1 0 1 1 2 using 2&s com"lement method
1 0 1 0 1 1
+ 0 0 0 1 1 1 2s comp& of 1 1 1 0 0 1
1 1 0 0 1 0 Ans& in 2s complement form
- 0 0 1 1 1 0 Answer in true form&
,,' +hat are the advantages o# 1&s com"lement subtraction)
1) "#e 1s complement su!traction can !e accomplis#ed wit# an !inary adder& "#erefore$
t#is met#od is useful in arit#metic lo*ic circuits& 2) "#e is complement of a num!er is easily
o!tained !y in,ertin* eac# !it in t#e num!er
.
,-' 1ind the e2cess %( code and 0&s com"lement o# the number *0(
10
C 0 =
0 1 0 0 0 0 0 0 0 0 1 1
0 0 1 1 0 0 1 1 0 0 1 1 +
0 1 1 1 0 0 1 1 0 1 1 0 e)cess = code
Es complement 1 0 0 0 1 1 0 0 1 0 0 1
,.' +rite the names o# basic logical o"erators'
1& 45" L /47(0" 2& A4D =& 50
,/' 6im"li#y the #ollowing e2"ression
y = %A + 2) %A = -) %2 + -)
= %A A + A - + A 2 + 2 -) %2 + -)
= %A - + A 2 + 2 -) %2 + -)
= A 2 - + A - - + A 2 2 + A 2 - + 2 2 - + 2 - -
= A 2 - = A 2 -
,0' 6how that the @8@D connection is not associative
"#e 4A4D connection is not associati,e says t#at
A & 2 & - A & 2& -
A & 2 + - A + 2 -
A2 + - A + 2-
-0' +hat is a Logic gate)
6o*ic *ates are t#e !asic elements t#at ma+e up a di*ital system& "#e electronic *ate is a
circuit t#at is a!le to operate on a num!er of !inary inputs in order to perform a particular lo*ical
function&
-1' +rite the names o# >niversal gates'
1& 4A4D *ate 2& 450 *ate
-2' +hy are @8@D and @=7 gates known as universal gates)
"#e 4A4D and 450 *ates are +nown as uni,ersal *ates$ since any lo*ic function can !e
implemented usin* 4A4D or 450 *ates&
-(' De#ine combinational logic
.#en lo*ic *ates are connected to*et#er to produce a specified output for certain specified
com!inations of input ,aria!les$ wit# no stora*e in,ol,ed$ t#e resultin* circuit is called
com!inational lo*ic&
-*' C2"lain the design "rocedure #or combinational circuits
O "#e pro!lem definition O "#e determination of num!er of a,aila!le input ,aria!les P
re1uired 5L< ,aria!les& O Assi*nin* letter sym!ols to /L5 ,aria!les O 5!tain simplified !oolean
e)pression for eac# 5L<& O 5!tain t#e lo*ic dia*ram&
-,' De#ine hal# adder and #ull adder
"#e lo*ic circuit w#ic# performs t#e addition of two !its is a #alf adder& "#e circuit w#ic#
performs t#e addition of t#ree !its is a full adder&
--' De#ine Decoder)
A decoder is a multiple - input multiple output lo*ic circuit w#ic# con,erts coded inputs into
coded outputs w#ere t#e input and output codes are different&
-.' +hat is binary decoder)
A decoder w#ic# #as an n-!it !inary iLp code and a one acti,ated output out of 2l& output
code is called !inary decoder& /t is used w#en it is necessary to acti,ate e)actly one of 2 n out puts
!ased on an n - !it input ,alue&
/
-/' De#ine Cncoder)
An encoder #as 2n input lines and n output lines& /n encoder t#e output lines *ener- ate t#e
!inary code correspondin* to t#e input ,alue&
-0' +hat is "riority Cncoder)
A priority encoder is an encoder circuit t#at includes t#e priority function& /n priority
encoder$ if 2 or more inputs are e1ual to 1 at t#e same time$ t#e input #a,in* t#e #i*#est priority
will ta+e precedence&
.0' De#ine multi"le2er)
;ultiple)er is a di*ital switc#& /f allows di*ital information from se,eral sources to !e
routed onto a sin*le output line&
.1' +hat do you mean by com"arator
A comparator is a special com!inational circuit desi*ned primarily to compare t#e relati,e
ma*nitude of two !inary num!ers&
.2' List basic ty"es o# "rogrammable logic devices'
1& <ro*ramma!le 0ead only memory %<05;)
2& <ro*ramma!le lo*ic Arrays %<6A)
=& <ro*ramma!le Array 6o*ic %<A6)
C& 8ield <ro*ramma!le Nate Array %8<NA)
B& -omple) <ro*ramma!le 6o*ic De,ices %-<6D)
.(' De#ine 7=5
A read only memory is a de,ice t#at includes !ot# t#e decoder and t#e 50 *ates wit#in a
sin*le /- pac+a*e&
.*' De#ine address and wordD
/n a 05;$ eac# !it com!ination of t#e input ,aria!le is called on address& (ac# !it
com!ination t#at comes out of t#e output lines is called a word&
.,' +hat are the ty"es o# 7=5
1& ;as+ed 05;&
2& <ro*ramma!le 0ead only ;emory =& (rasa!le <ro*ramma!le 0ead only memory&
C& (lectrically (rasa!le <ro*ramma!le 0ead only ;emory&
.-' +hat is "rogrammable logic array)
How it differs from 05;Q /n some cases t#e num!er of donRt care conditions is e)cessi,e$
it is more economical to use a second type of 6S/ component called a <6A A <6A is similar to a
05; in conceptI #owe,er it does not pro,ide full decodin* of t#e ,aria!les and does not *enerates
all t#e minterms as in t#e 05;&&
..' +hat is mask % "rogrammable)
.it# a mas+ pro*ramma!le <6A$ t#e user must su!mit a <6A pro*ram ta!le to t#e
manufacturer&
./' +hat is #ield "rogrammable logic array)
"#e second type of <6A is called a field pro*ramma!le lo*ic array& "#e (<6A can !e
pro*rammed !y t#e user !y means of certain recommended procedures&
.0' Give the com"arison between "rom and <L8'
<7=5 1& A4D array is fi)ed and 50 array is pro*ramma!le 2& -#eaper and simple to use&
<L8 1' 2ot# A4D and 50 arrays are <ro*ramma!le 2& -ostliest and comple) t#an
<05;S&
0
/0' De#ine even "arity
/n e,en parity t#e added parity !it will ma+e t#e total num!er of 1s an e,en amount&
/1' De#ine seAuential circuit)
/n se1uential circuits t#e output ,aria!les dependent not only on t#e present input ,aria!les
!ut t#ey also depend up on t#e past #istory of t#ese input ,aria!les&
/2' Give the com"arison between combinational circuits and seAuential circuits'
;emory unit is not re1uired ;emory unity is re1uired <arallel adder is a com!inational
circuit Serial adder is a se1uential circuit
/(' +hat do you mean by "resent state)
"#e information stored in t#e memory elements at any *i,en time defineRs t#e present state
of t#e se1uential circuit&
/*' +hat do you mean by ne2t state)
"#e present state and t#e e)ternal inputs determine t#e outputs and t#e ne)t state of t#e
se1uential circuit&
/,' +hat are the ty"es o# seAuential circuits)
1& Sync#ronous se1uential circuits 2& Async#ronous se1uential circuits
/-' De#ine synchronous seAuential circuit
/n sync#ronous se1uential circuits$ si*nals can affect t#e memory elements only at discrete
instant of time&
/.' De#ine 8synchronous seAuential circuit)
/n async#ronous se1uential circuits c#an*e in input si*nals can affect memory element at
any instant of time
//' De#ine #li"%#lo"
8lip - flop is a se1uential de,ice t#at normally& samples its inputs and c#an*es its outputs
only at times determined !y cloc+in* si*nal&
/0' List various ty"es o# #li"%#lo"
1: S&0& latc# 2: D latc# =: -loc+ed S&T& flip-flop C: " flip-flop
00' +hat is race around condition)
/n t#e ST latc#$ t#e output is feed!ac+ to t#e input$ and t#erefore c#an*e in t#e output results
c#an*e in t#e input& Due to t#is in t#e positi,e #alf of t#e cloc+ pulse if S and T are !ot# #i*# t#en
output to**les continuously& "#is condition is +nown as race around condition&
01' De#ine rise time and #all time)
"#e time re1uired to c#an*e t#e ,olta*e le,el from 10U to E0U is +nown as rise time$ and
t#e time re1uired to c#an*e t#e ,olta*e le,el from E0U to 10U is +nown as fall time&
02' De#ine "ro"agation Delay)
A propa*ation delay is t#e time re1uired to c#an*e t#e output after application of t#e input&
0(' De#ine shi#t 7egisters
"#e !inary information in a re*ister can !e mo,ed from sta*e to sta*e wit#in t#e re*ister or
into or out of t#e re*ister upon application of cloc+ pulses& "#is type of !it mo,ement or s#iftin* is
essential for certain arit#metic and lo*ic operations used in microprocessors& "#is *i,es rise to a
*roup of re*isters called s#ift re*isters&
0*' +hat are the ty"es o# shi#t register)
1& Serial in serial out s#ift re*isterQ 2& Serial in parallel out s#ift re*ister =& <arallel in serial
out s#ift re*ister C& <arallel in parallel out s#ift re*ister B& 2idirectional s#ift re*ister s#ift re*ister&
0,' +hat are the ty"es o# counter)
1& Sync#ronous counter 2& Async#ronous -ounter
10
0-' +hat are the two models in synchronous seAuential circuits'
1& ;oore circuit 2& ;ealy circuit
0.' +hat is moore circuit)
.#en t#e output of t#e se1uential circuit depends only on t#e present state of t#e flip-flop$
t#e se1uential circuit is referred to as moore circuit&
0/' +hat is 5ealy circuit)
.#en t#e output of t#e se1uential circuit depends on !ot# t#e present state of flip- flop and
on t#e input$ t#e se1uential circuit is referred to as mealy circuit&
00' De#ine successor
/n a state dia*ram$ if an input se1uence$ ) ta+es a mac#ine from state si to state sM$ t#en sM is
said to !e t#e ) - successor of si&
100' De#ine strongly connected machine)
/n a se1uential mac#ine many times certain su!sets of states may not !e reac#a!le from
ot#er su!sets of states$ e,en if t#e mac#ine does not contain any terminal state& Howe,er$ if for
e,ery pair of states si$ sM of a se1uential mac#ine$ t#ere ei*#ts an input se1uence w#ic# ta+es ;
from Si to SM t#en se1uential mac#ine ; is said to !e stron*ly connected&
101' 6tate and "rove consensus theorem in 9oolean algebra)
/n simplification of 2oolean e)pression$ t#e redundant term in an e)pression can !e
eliminated to form t#e e1ui,alent e)pression& "#e t#eorem used for t#is simplification is called
consensus t#eorem& 8or e) in e)pression of t#e A2+A-+2-$ t#e term 2- is redundant and can !e
eliminated usin* -onsensus t#eorem&
102' +hat do you mean by Literal)
/n 2oolean function$ t#e total num!ers of ,aria!les in complemented or uncomplemented
form are called literals&
10(' Give 8""lications o# 5>X)
8""licationsD
1& ;VX can !e used to reali3e a 2oolean function
2& /t can !e used in communication systems e&*& time di,ision multiple)in*
10*' De#ine Latch)
/t is a se1uential de,ice t#at c#ec+s all of its inputs continuously and c#an*es its outputs
accordin*ly at any time$ independent of a cloc+in* si*nal&
10,' +hat is Lock out)
/n a counter$ if t#e ne)t state of some unused state is a*ain some unused state$ it may #appen
t#at t#e counter remains in unused state ne,er to arri,e at a used state& Suc# a condition is called
6oc+ out condition&
10-' Bow to avoid Lock out Condition)
1& "#e counter s#ould !e pro,ided wit# an additional circuit& "#is will force t#e counter from
an unused state to t#e ne)t state as initial state&
2& /t is not always necessary to force all unused states into an initial state& 2ecause from
unused states w#ic# are not forced$ t#e circuit may e,entually arri,e at a forced unused
state& "#is frees t#e circuit from t#e 6oc+ out condition&
10.' 6tate the advantages and disadvantages o# Eotem "ole out"ut)
Ad,anta*es
1& ()ternal pull up resistor is not re1uired
2& 5peratin* speed is #i*#
11
Disad,anta*es
5utput of two *ates cannot !e tied to*et#er&
10/' C2"lain the wired 8nd connection)
.#en t#e open collector outputs of two or more *ates can !e connected to*et#er$ t#e
connection is called a wired A4D&
/t is represented as
1& /n wired A4D connection$ t#e output is #i*# only w#en all t#e switc#es are open
2& Hence$ t#e output is e1ui,alent to t#e lo*ical A4D operation of t#e lo*ic function performed
!y t#e *ates&
100' 6tate the advantages and disadvantages o# wired 8@D connection'
8dvantage is$ 5utputs of two *ates can !e tied to*et#er usin* wired-A4D tec#ni1ue&
Disadvantage is$ 5peratin* Speed is 6ow&
110' +hat is o"en collector out"ut'
.#en t#e collector terminal of t#e transistor is +ept open wit#out any pull up transistor t#e
arran*ement is called open collector output&
1- marks
>@FE F
1& Determine t#e prime-implicants of t#e 2oolean function !y usin* t#e ta!ulation
met#od%w$ )$ y$ 3)=W%1$C$>$D$F$E$10$11$1B) %0efer p* 1&>2 ' 1&>C in Nodse)
2& Simplify t#e followin* 2oolean e)pression usin* Xuine ;c-lus+ey met#od
8=Ym%0$E$1B$2C$2E$=0)+d%F$11$=1)& %0efer p* 1&>> ' 1&>F in Nodse)
=& Desi*n a com!inational lo*ic dia*ram for 2-D to ()cess-= code con,erter& %0efer p*
=&=>$=&=D in Nodse)
C& 8ind a minimum sum of products e)pression for t#e followin* function usin* Xuine-
;c-lus+y met#od&
8 %A$2$-$D$() = Y%0$2$=$B$D$E$11$1=$1C$1>$1F$2C$2>$2F$=0) %0efer p* 1&>2 -1&>C in Nodse)
B& Determine t#e minimum sum of products and minimum product of sums for f =
!cd+!cd+acd+a!!cd& %0efer p* 1&C2 P 1&BC in Nodse)
>& 8ind t#e minterm e)pansion of f %a$ !$ c$ d) = a %!+d) +acd %0efer notes)
D& ()plain wit# necessary dia*ram a 2-D to D se*ment display decoder& %0efer p* =&BB ' =&BE in
Nodse)
E& .it# a suita!le !loc+ dia*ram e)plain t#e operation of 2-D adder %0efer p* =&20 ' =&22 in
Nodse)
10& Draw and e)plain t#e wor+in* of a carry-loo+ a#ead adder& %0efer p* =&1B ' =&1F in Nodse)
>@FE FF
1& Desi*n a ;5D ' 10 sync#ronous counter usin* ST flip-flops& .rite t#e
e)citation ta!le and state ta!le& %0efer p* B&=D$ B&=F in Nodse)
2& Desi*n a se1uential circuit wit# four flip-flops A2-D& "#e ne)t states of 2$ -$ and D
are e1ual to t#e present states of A$ 2$ - respecti,ely& "#e ne)t state of A is e1ual to
t#e (X- 50 of present states of - and D& %0efer p* B&F> in Nodse)
=& Desi*n a mod- D counter usin* ST flip-flops& %0efer p* B&CE - B&B1 in Nodse)
C& Desi*n a 2-D Vp L Down counter usin* S 0 flip-flops& %0efer p* B&EF ' B&102 in Nodse)
B& Desi*n a sync#ronous decade counter usin* D flip-flops& %0efer p* B&E2$ B&E= in Nodse)
12
>& ()plain t#e wor+in* of ST flip- flop& .#at is race around conditionQ How is it
o,ercomeQ ()plain t#ese concepts wit# rele,ant timin* dia*rams& %0efer p* C&1= -C&1> in
Nodse)
D& Desi*n a = ' !it up L down counter usin* ST flip ' flops and ()plain its wor+in* wit# timin*
dia*rams& %0efer p* B&C2$ B&C= in Nodse)
F& Vsin* S0 flip-flops desi*n a parallel counter$ w#ic# counts in t#e se1uence
101$110$001$010$000$111$101Z%0efer p* B&F1$ B&F2 in Nodse)
E& Desi*n a sync#ronous se1uential counter usin* ST flip-flop and a,oid loc+ out condition$ for
C[>[D[=[1[CZ %0efer p* B&2F$ B&2E in Nodse)
10& ()palin t#e operation of ;aster Sla,e ST flip-flop wit# suita!le dia*rams& %0efer C&1D ' C&1E
in Nodse)
>@FE FFF
1' Desi*n an async#ronous se1uential circuit t#at #as two inputs X1 and X1 and one output \&
.#en X1=0$ t#e output \ is 0& "#e first c#an*e in X2 t#at occurs w#ile X1 is 1 will cause
output \ to !e 1& "#e output \ will remain 1 until X1 returns to 0& %0efer p* >&1F->&21 in
Nodse)
2' Desi*n a pulse mode circuit #a,in* two input lines X1 and X2 and one output line \& "#e
circuit s#ould produce an output pulse to coincide wit# t#e last input pulse in t#e se1uenceX1$
X2$ X2& 4o ot#er input se1uence s#ould produce an output pulse& %0efer p* >&=C ' >&=B in
Nodse)
=& Draw t#e state dia*ram and o!tain t#e primiti,e flow ta!le for a circuit wit# two inputs )1 and
)2 and two outputs 31 and 32 t#at satisfies t#e followin* conditions&
1& .#en )1)2=00$ output 3132=00&
2& .#en )1=1 and )2 c#an*es from 0 to 1$ t#e output 3132=01&
=& .#en )2=1 and )1 c#an*es from 0 to 1$ output 3132=10&
C& 5t#erwise output does not c#an*e& % 0efer p* >&2>$ >&2D in Nodse)
B& Define t#e followin* i) async#ronous se1uential circuits$ ii) -ycles$ iii) critical race$
i,) non- critical race ,) race ,i) flow ta!le ,ii) primiti,e flow ta!le ,iii) sta!le state % 0efer
notes)
.' An async#ronous se1uential circuit #as two internal states and one output& "#e e)citation and
output function descri!in* t#e circuit are as follows&
Y1=)1)2+)1y2+)2y1
Y2=)2+)1y1y2+)1y1
\=)2+y1 %refer >&2C ' >&2> in Nodse)
>@FE FG
1& Desi*n a com!inatorial circuit usin* 05; and <6A& "#e circuit accepts =-!it num!er and
*enerates an output !inary num!er e1ual to s1uare of input num!er& %0efer p* S&>$ SD in
Nodse)
2& .rite a descripti,e note on memories& %0efer p* D1$ D2 in Nodse)
=& Discuss on t#e concept and applications of 05;$ <05; and (<05; %0efer p* D&2 ' D&> in
Nodse)
C& Discuss on t#e wor+in* of 8<NA$ <6A$ <A6$ <05; % 0efer section F&2$=$C$B in Nodse)
B& Ni,e t#e comparison !etween <05;$ <6A$ and <A6 %0efer p* F-=1 in Nodse)
>& /mplement t#e followin* 2oolean function usin* <A6 %0efer p* F&1E-F&21 in Nodse)
.%A$2$-$D) = Ym%0$2$>$D$F$E$12$1=)
)%A$2$-$D) = Ym%0$2$>$D$F$E$12$1=$1C)
y%A$2$-$D) = Ym%2$=$F$E$10$12$1=)
3%A$2$-$D) = Ym%1$=$C$>$E$12$1C)
D& 0eali3e t#e functions *i,en usin* a <6A wit# > inputs$ C outputs and 10 A4D *ates
1(
f1%A$2$-$D$($8) = Ym%0$1$D$F$E$10$11$1B$1E$2=$2D$=1$=2$==$=B$=E$C0$C1$CD$>=)
f2%A$2$-$D$($8) = Ym%F$E$10$11$12$1C$21$2B$2D$C0$C1$C2$C=$CC$C>$BD$BE) %0efer p* F&C2 '
F&CC in Nodse)
F& Draw t#e circuit of a -;5S two input 4A4D *ate and 450 *ate and e)plain its operation&
%0efer p* E&=F ' E&C1 in Nodse)
E& ()palin a!out !asic circuit and 450 *ate of (-6 wit# its c#aracteristics& %0efer p* E&CF '
E&B0 in Nodse)
10& ()plain a!out ""6$ its wired lo*ic and a!out t#e totem pole output$ t#ree state output ""6
wit# its c#aracteristics& %0efer p* E&1= ' E&=> in Nodse)
>@FE G
1& ()palin t#e !loc+ dia*ram of a typical processor unit wit# control si*nals and Arit#metic unit
% 0efer p* 10&=F ' 10&C0 and 10&2> ' 10&2E in Nodse)
2& Desi*n A6V$ S#ift re*ister and S#ifter wit# its lo*ic Dia*ram& %0efer p* 10&=0 -10&=F in
Nodse)
=& Desi*n Simple -omputer wit# its 2loc+ dia*ram& %0efer p* 10&21 -1010&2B in Nodse)
C& .rite an HD6 pro*ram for full adder and C-!it -omparator %0efer p* 11&>2$ 11&>D-11&>F in
Nodse)
B& .rite an HD6 !e#a,ioural description of ST flip-flop usin* if-else statement !ased on t#e
,alue of t#e present state& %0efer p* S&F in Nodse)
>& .rite a 7HD6 code for a serial adder %0efer 4otes)
D& .rite a 7HD6 code for a " flip-flop %0efer 4otes)
F& .rite a 7HD6 code for 8S;& %0efer 4otes)