1.

If you need the design to run at a particular frequency, then you need to set a
PERIOD constraint on the clock signal.
2. The !ini!u! period reported "y #$T is "ased on the slo%est clock in the design.
If your D&'(Digital clock !anager) is changing the frequency (for e*a!ple !ultiplying the
input clock "y 2), then this !ini!u! period refers to the slo%est of the D&' input or
output clocks.
Minimum Period: Minimum Delay from any synchronous
element to another. Is also d
isplayed in Mhz.
Maximum path delay from/to any node: Maximum delay from
any node to any other no
de.
Minimum input arrival time before clock: This is the
minimum lobal !""#$T I% &$
"!'$
Maximum input arrival time after clock: This is the
maximum lobal !""#$T I% ("T
$'
Minimum output arrival time before clock: This is the
minimum lobal !""#$T !)T
&$"!'$
Maximum output arrival time after clock: This is the
maximum lobal !""#$T !)T (
"T$'