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DSP Integrated Circuits 5
DSP Integrated Circuits 5
VLSI Design
First Semester
Reg. No. :
2.
3.
4.
1.
y(n ) = ax (n ) + y(n 1) .
6.
7.
8.
9.
10.
5.
(a)
(16)
11.
PART B (5 16 = 80 Marks)
(b)
(a)
(i)
(ii)
(16)
(8)
12.
(b)
13.
(16)
(a)
Explain the procedure for the design of IIR filter using Chebyshevs
approximation.
(16)
Or
14.
(a)
Write down the standard procedure for mapping of DSP algorithms onto
hardware.
(16)
(b)
(b)
Or
(a)
(ii)
15.
(i)
(8)
Complex multipliers.
(8)
(ii)
(8)
Draw and explain the layout of VLSI circuit for FFT processor.
(b)
Or
(16)
J 7792