LI NI U

Ngy nay cng vi s pht trin ca khoa hc k thut, x hi ngy cng vn

minh hin i v nhu cu v giao thng ngy cng tr nn cn thit, nht l trong cc
khu vc thnh th. Do nhu cu ca i sng con ngi, c bit l nhu cu i li, cc
loi phng tin giao thng tng mt cch chng mt. Ring ti Vit Nam s lng
xe my trong nhng nm qua tng mt cch t bin, mt xe lu thng trn ng
ngy mt nhiu, trong khi h thng ng x ti Vit Nam cn qu nhiu hn ch
nn thng gy ra cc hin tng nh kt xe, ch tc giao thng gi cao im v c
bit tai nn giao thng ngy cng ph bin tr thnh mi him ha cho nhiu ngi.
V l do cc lut l giao thng ln lt ra i v c a vo s dng.
Trong h thng n giao thng l cng c iu khin giao thng cng cng thc t
v hiu qu c vai tr rt ln trong vic m bo an ton v gim thiu tai nn giao
thng.
T thc t , em quyt nh chn ti Xy dng h thng iu khin n
giao thng dng vi iu khin 89S52 lm ti cho bi tiu lun ca mn hc Vi
x l v vi iu khin trong o lng v iu khin t ng.
Sau qu trnh t tm ti v hc hi, cng vi s gip ca cc thy gio trong
b mn v cc bn sinh vin trong lp, cui cng em cng hon thnh xong ti
ny. Trong qu trnh lm ti, chc chn lun c thiu st trong ni dung cng nh
cch trnh by nn em mong cc thy v cc bn s gp chn thnh sau ny em c
th vn dng hon thnh tt cc ti khc, n tt nghip v quan trng hn l
cho cng vic sau ny.
Em xin chn thnh cm n !

Hu, ngy 7 thng 12 nm 2013

1
Phan Hu an - in t vin thng K34

MC LC
LI NI U ........................................................................................................... 1
MC LC .................................................................................................................. 2
I/ GII THIU V VI IU KHIN AT89S52 ................................................... 3
1. Tng quan v 89S52 ................................................................................... 3
2. M t cc chn ca 89S52 ......................................................................... 5
2.1. S chn 89S52 .......................................................................... 5
2.2. Chc nng ca cc chn 89S52 ..................................................... 5
3. T chc b nh bn trong 89S52 .............................................................. 7
3.1. RAM a dng................................................................................. 9
3.2. RAM c th nh a ch bit .......................................................... 9
3.3. Cc bank thanh ghi ........................................................................ 9
3.4. Cc thanh ghi c chc nng c bit ............................................. 9
3.4.1. Thanh ghi trng thi chng trnh (PSW) ..................... 10
3.4.2. Thanh ghi TIMER .......................................................... 11
3.4.3. Thanh ghi ngt (INTERRUPT) ...................................... 12
II/ XY DNG H THNG IU KHIN N GIAO THNG .................. 15
1. Ch hot ng ..................................................................................... 15
2. Cc thnh phn chnh ca h thng ....................................................... 15
3. Cc linh kin s dng .............................................................................. 15
4. Nguyn l hot ng ................................................................................ 16
5. S thut ton ....................................................................................... 16
6. S mch................................................................................................ 17
6.1. S nguyn l trn ISIS ca phn mm Protues ...................... 17
6.2. S mch in .............................................................................. 17
6.3. Hnh nh thit k 3D trn ARES ca phn mm Proteus ............ 18
6.4. Hnh nh thc t ........................................................................... 18
7. Chng trnh lp trnh Assembly .......................................................... 19
8. Nhn xt ca gio vin ............................................................................. 23

2
Phan Hu an - in t vin thng K34

I/ GII THIU V VI IU KHIN AT89S52

1. Tng quan v 89S52
AT89S52 l h IC 8051 vi iu
khin do hng Atmel sn xut. Cc sn
phm AT89S52 thch hp cho nhng ng
dng iu khin. Vic x l trn byte v
cc ton s hc cu trc d liu nh
c thc hin bng nhiu ch truy
xut d liu nhanh trn RAM ni. Tp
lnh cung cp mt bng tin dng ca
nhng lnh s hc 8 bit gm c lnh nhn
v lnh chia. N cung cp nhng h tr
m rng trn chip dng cho nhng bin
mt bit nh l kiu d liu ring bit cho php qun l v kim tra bit trc tip trong
h thng iu khin.
AT89S52 cung cp nhng c tnh chun nh: 8 KByte b nh ch c c th xa
v lp trnh nhanh (EPROM), 128 Byte RAM, 32 ng I/O, 3 TIMER/COUNTER 16
Bit, 5 vect ngt c cu trc 2 mc ngt, mt Port ni tip bn song cng, 1 mch dao
ng to xung Clock v b dao ng ON-CHIP.
Cc c im ca chip AT89S52 c tm tt nh sau:
8 KByte b nh c th lp trnh nhanh, c kh nng ti 1000 chu k ghi/xo.
Tn s hot ng t: 0Hz n 24 MHz.
3 mc kha b nh lp trnh.
3 b Timer/counter 16 Bit.
128 Byte RAM ni.
4 Port xut /nhp I/O 8 bit.
Giao tip ni tip.
64 KB vng nh m ngoi.
64 KB vng nh d liu ngoi.
4 s cho hot ng nhn hoc chia.

3
Phan Hu an - in t vin thng K34

S khi ca AT89S52

4
Phan Hu an - in t vin thng K34

2. M t cc chn ca 89S52

Mc d cc thnh vin ca h
8051(v d 8751, 89S52, 89C51,
DS5000) u c cc kiu ng v
khc nhau, chng hn nh hai hng
chn DIP (Dual In-Line Pakage),
dng v dt vung QPF (Quad Flat
Pakage) v dng chip khng c chn
LLC (Leadless Chip Carrier) th
chng u c 40 chn cho cc chc
nng khc nhau nh vo ra I/O, c

AT89S52

2.1. S chn 89S52

RD , ghi WR , a ch, d liu v

ngt. Cn phi lu mt s hng

cung cp mt phin bn 8051 c 20
chn vi s cng vo ra t hn cho
cc ng dng yu cu thp hn. Tuy
nhin v hu ht cc nh pht trin s
dng chp ng v 40 chn vi hai hng chn DIP nn ta ch tp trung m t phin bn
ny.
2.2. Chc nng ca cc chn 89S52
Port 0: t chn 32 n chn 39 (P0.0 _P0.7). Port 0 c 2 chc nng: trong cc
thit k c nh khng dng b nh m rng n c chc nng nh cc ng IO, i
vi thit k ln c b nh m rng n c kt hp gia bus a ch v bus d liu.
Port 1: t chn 1 n chn 9 (P1.0 _ P1.7). Port 1 l port IO dng cho giao tip
vi thit b bn ngoi nu cn.
Port 2: t chn 21 n chn 28 (P2.0 _P2.7). Port 2 l mt port c tc dng kp
dng nh cc ng xut/nhp hoc l byte cao ca bus a ch i vi cc thit b
dng b nh m rng.
Port 3: t chn 10 n chn 17 (P3.0 _ P3.7). Port 3 l port c tc dng kp. Cc
chn ca port ny c nhiu chc nng, c cng dng chuyn i c lin h n cc c
tnh c bit ca 89S52 nh bng sau:

5
Phan Hu an - in t vin thng K34

Bit

Tn

Chc nng chuyn i

P3.0

RXD

Ng vo d liu ni tip.

P3.1

TXD

Ng xut d liu ni tip.

P3.2

INT0

Ng vo ngt cng th 0.

P3.3

INT1

Ng vo ngt cng th 1.

P3.4

T0

Ng vo TIMER/ COUNTER th 0.

P3.5

T1

Ng vo ca TIMER/ COUNTER th 1.

P3.6

WR

Tn hiu ghi d liu ln b nh ngoi.

P3.7

RD

Tn hiu c b nh d liu ngoi.

PSEN (Program store enable):

PSEN l tn hiu ng ra c tc dng cho php c b nh chng trnh
m rng v thng c ni n chn OE ca Eprom cho php c cc byte
m lnh.
PSEN mc thp trong thi gian 89S52 ly lnh. Cc m lnh ca chng trnh
c c t Eprom qua bus d liu, c cht vo thanh ghi lnh bn trong 89S52
gii m lnh. Khi 89S52 thi hnh chng trnh trong ROM ni, PSEN mc cao.
ALE (Address Latch Enable):
Khi 89S52 truy xut b nh bn ngoi, Port 0 c chc nng l bus a ch v d
liu do phi tch cc ng d liu v a ch. Tn hiu ra ALE chn th 30 dng
lm tn hiu iu khin gii a hp cc ng a ch v d liu khi kt ni chng
vi IC cht.
Tn hiu chn ALE l mt xung trong khong thi gian port 0 ng vai tr l
a ch thp nn cht a ch hon ton t ng.
EA (External Access): Tn hiu vo EA (chn 31) thng c mc ln mc 1
hoc mc 0. Nu mc 1, 89S52 thi hnh chng trnh t ROM ni. Nu mc 0,
89S52 thi hnh chng trnh t b nh m rng. Chn EA c ly lm chn cp
ngun 21V khi lp trnh cho Eprom trong 89S52.

6
Phan Hu an - in t vin thng K34

RST (Reset): Khi ng vo tn hiu ny a ln

mc cao t nht 2 chu k my, cc thanh ghi bn
trong c np nhng gi tr thch hp khi
ng h thng. Khi cp in mch phi t ng
reset.
Cc gi tr t v in tr c chn l:
R1=10, R2=220, C=10 F.
Cc ng vo b dao ng X1, X2:
B to dao ng c tch hp bn trong
89S52. Khi s dng 89S52, ngi ta ch cn ni
thm thch anh v cc t. Tn s thch anh ty
thuc vo mc ch ca ngi s dng, gi tr t
thng c chn l 33p.

3. T chc b nh bn trong 89S52

B nh trong 89S52 bao gm ROM v RAM. RAM trong 89S52 bao gm
nhiu thnh phn: phn lu tr a dng, phn lu tr a ch ha tng bit, cc bank
thanh ghi v cc thanh ghi chc nng c bit.
AT89S52 c b nh c t chc theo cu trc Harvard: c nhng vng b nh
ring bit cho chng trnh v d liu. Chng trnh v d liu c th cha bn trong
89S52 nhng 89S52 vn c th kt ni vi 64K byte b nh chng trnh v 64K byte
d liu bn ngoi.

7
Phan Hu an - in t vin thng K34

Bn b nh Data bn trong Chip 89S52 c t chc nh sau:

a ch
byte

a ch

a ch bit

byte

a ch bit

8
Phan Hu an - in t vin thng K34

RAM bn trong AT89S52 c phn chia nh sau:

Cc bank thanh ghi c a ch t 00H n 1FH.
RAM a ch ha tng bit c a ch t 20H n 2FH.
RAM a dng t 30H n 7FH.
Cc thanh ghi chc nng c bit t 80H n FFH
3.1. RAM a dng
RAM a dng c a ch t 30h 7Fh c th truy xut mi ln 8 bit bng cch
dng ch nh a ch trc tip hay gin tip.
Cc vng a ch thp t 00h 2Fh cng c th s dng cho mc ch nh trn,
ngoi cc chc nng c bit c cp phn sau.
3.2. RAM c th nh a ch bit
Vng a ch t 20h -2Fh gm 16 byte c th thc hin nh vng RAM a dng
(truy xut mi ln 8 bit) hay thc hin truy xut mi ln 1 bit bng cc lnh x l bit.
3.3. Cc bank thanh ghi
Vng a ch 00h 1Fh c chia thnh 4 bank thanh ghi: bank 0 t 00h 07h,
bank 1 t 08h 0Fh, bank 2 t 10h 17h v bank 3 t 18h 1Fh. Cc bank thanh ghi
ny c i din bng cc thanh ghi t R0 n R7. Sau khi khi ng th h thng
bank 0 c chn s dng.
Do c 4 bank thanh ghi nn ti mt thi im ch c mt bank thanh ghi c
truy xut bi cc thanh ghi R0 n R7. Vic thay i bank thanh ghi c thc hin
thng qua thanh ghi t trng thi chng trnh (PSW).
3.4. Cc thanh ghi c chc nng c bit
Cc thanh ghi trong 89S52 c nh dng nh mt phn ca RAM trn chip v
vy mi thanh ghi s c mt a ch (ngoi tr thanh ghi b m chng trnh v thanh
ghi lnh v cc thanh ghi ny him khi b tc ng trc tip). Cng nh R0 n R7,
89S52 c 21 thanh ghi c chc nng c bit (SFR: Special Function Register) vng
trn ca RAM ni t a ch 80H n 0FFH.

9
Phan Hu an - in t vin thng K34

Sau y l mt vi thanh ghi c bit thng c s dng:

3.4.1. Thanh ghi trng thi chng trnh (PSW: Program Status Word)
BIT

SYMBOL

ADDRESS

DESCRIPTION

PSW.7

CY

D7H

Cary Flag

PSW.6

AC

D6H

Auxiliary Cary Flag

PSW.5

F0

D5H

Flag 0

PSW4

RS1

D4H

Register Bank Select 1

PSW.3

RS0

D3H

Register Bank Select 0

00=Bank 0; address 00H07H
01=Bank 1; address 08H0FH
10=Bank 2; address 10H17H
11=Bank 3; address 18H1FH

PSW.2

OV

D2H

Overlow Flag

PSW.1

D1H

Reserved

PSW.0

DOH

Even Parity Flag

Chc nng tng bit trng thi chng trnh

- C Carry CY (Carry Flag):C nh thng n c dng cho cc lnh ton
hc: C =1 nu php ton cng c s trn hoc php tr c mn v ngc li C
= 0 nu php ton cng khng trn v php tr khng c mn.
- C Carry ph AC (Auxiliary Carry Flag):
Khi cng nhng gi tr BCD
(Binary Code Decimal), c nh ph AC c set nu kt qu 4 bit thp nm
trong phm vi iu khin 0AH - 0FH. Ngc li AC = 0
- C 0 (Flag 0):
C 0 (F0) l 1 bit c a dng dng cho cc ng dng ca ngi dng.
- Nhng bit chn bank thanh ghi truy xut:
RS1 v RS0 quyt nh dy thanh ghi tch cc. Chng c xa sau khi reset h
thng v c thay i bi phn mm khi cn thit.
Ty theo RS1, RS0 = 00, 01, 10, 11 s c chn Bank tch cc tng ng l
Bank 0, Bank1, Bank2 v Bank3.
10
Phan Hu an - in t vin thng K34

RS1

RS0

BANK

- C trn OV (Over Flag):

C trn c set sau mt hot ng cng hoc tr nu c s trn ton hc.
- Bit Parity (P):
Bit t ng c set hay Clear mi chu k my lp Parity chn vi thanh
ghi A. S m cc bit 1 trong thanh ghi A cng vi bit Parity lun lun chn. V d A
cha 10101101B th bit P set ln mt tng s bit 1 trong A v P to thnh s chn.
Bit Parity thng c dng trong s kt hp vi nhng th tc ca Port ni
tip to ra bit Parity trc khi pht i hoc kim tra bit Parity sau khi thu.
3.4.2. Thanh ghi TIMER
Vi iu Khin 89S52 c 3 timer 16 bit, mi timer c bn cch lm vic. Ngi
ta s dng cc timer :
o nh khong thi gian.
o m s kin.
o To tc baud cho port ni tip trong 89S52.
Trong cc ng dng nh khong thi gian, ngi ta lp trnh timer nhng
khong u n v t c trn timer. C c dng ng b ha chng trnh
thc hin mt tc ng nh kim tra trng thi ca cc ng vo hoc gi s kin ra cc
ng ra. Cc ng dng khc c th s dng vic to xung nhp u n ca timer o
thi gian tri qua gia hai s kin (v d o rng xung).

11
Phan Hu an - in t vin thng K34

3.4.3. Thanh ghi ngt (INTERRUPT)

Mt ngt l s xy ra mt iu kin, mt s kin m n gy ra treo tm thi thi
chng trnh chnh trong khi iu kin c phc v bi mt chng trnh khc.
Cc ngt ng mt vai tr quan trng trong thit k v ci t cc ng dng vi
iu khin. Chng cho php h thng p ng bt ng b vi mt s kin v gii
quyt s kin trong khi mt chng trnh khc ang thc thi.
- T chc ngt ca 89S52:
C 5 ngun ngt 89S52: 2 ngt ngoi, 2 ngt t timer v 1 ngt port
ni tip. Tt c cc ngt theo mc nhin u b cm sau khi reset h thng v c cho
php tng ci mt bng phn mm. Mc u tin ca cc ngt c lu trong thanh
ghi IP (Interrupt Priority) hay ni cch khc thanh ghi IP cho php chn mc u tin
cho cc ngt (gi tr thanh ghi IP khi reset l 00h).

Bit

K hiu

a ch bit

IP.7

Khng c m t

IP.6

Khng c m t

IP.5

ET2

BDH

Chn mc u tin cao (=1) hay thp (=0) ti

timer 2

IP.4

ES

BCH

Chn mc u tin cao (=1) hay thp (=0) ti

cng ni tip.

IP.3

ET1

BBH

Chn mc u tin cao (=1) hay thp (=0) ti

timer 1

IP.2

EX1

BAH

Chn mc u tin cao (=1) hay thp (=0) ti

ngt ngoi 1

IP.1

ET0

B9H

Chn mc u tin cao (=1) hay thp (=0) ti

timer 0

IP.0

EX0

B8H

Chn mc u tin cao (=1) hay thp (=0) ti

ngt ngoi 0

M t

12
Phan Hu an - in t vin thng K34

 Nu 2 ngt xy ra ng thi th ngt no c no c mc u tin cao hn s

c phc v trc.
Nu 2 ngt xy ra ng thi c cng mc u tin th th t u tin c
thc hin t cao n thp nh sau: ngt ngoi 0 timer 0 ngt ngoi 1 timer 1
cng ni tip timer 2.
Nu chng trnh ca mt ngt c mc u tin thp ang chy m c mt
ngt xy ra vi mc u tin cao hn th chng trnh ny tm dng chy mt
chng trnh khc c mc u tin cao hn.

- Cho php v cm ngt:

Mi ngun ngt c cho php hoc cm ngt qua mt thanh ghi chc nng t
bit c nh a ch bit IE (Interrupt Enable: cho php ngt) a ch A8H.

Bit

K hiu

a ch bit

IE.7

EA

AFH

Cho php / Cm ton b

IE.6

AEH

Khng c m t

IE.5

ET2

ADH

Cho php ngt t Timer 2 (8052)

IE.4

ES

ACH

Cho php ngt port ni tip

IE.3

ET1

ABH

Cho php ngt t Timer 1

IE.2

EX1

AAH

Cho php ngt ngoi 1

IE.1

ET0

A9H

Cho php ngt t Timer 0

IE.0

EX0

A8H

Cho php ngt ngoi 0

M t

Tm tt thanh ghi IE

13
Phan Hu an - in t vin thng K34

- Cc c ngt:
Khi iu kin ngt xy ra th ng vi tng loi ngt m loi c c t ln
mc cao xc nhn ngt.
Ngt

Thanh ghi SFR v v tr bit

Bn ngoi 0

IE0

TCON.1

Bn ngoi 1

IE1

TCON.3

Timer 1

TF1

TCON.7

Timer 0

TF0

TCON.5

Port ni tip

TI

SCON.1

Port ni tip

RI

SCON.0

Cc loi c ngt
- Cc vect ngt:
Khi chp nhn ngt, gi tr c np vo PC gi l vector ngt. N l a ch bt
u ca ISR cho ngun to ngt, cc vector ngt c cho bng sau :
Ngt

a ch vector

Reset h thng

RST

0000H

Bn ngoi 0

IE0

0003H

Timer 0

TF0

000BH

Bn ngoi 1

IE1

0013H

Timer 1

TF1

001BH

Port ni tip

TI v RI

0023H

Timer 2

002BH

Vector reset h thng (RST a ch 0000H) c trong bng ny v theo ngha

ny, n ging ngt: n ngt chng trnh chnh v np cho PC gi tr mi.

14
Phan Hu an - in t vin thng K34

II/ XY DNG H THNG IU KHIN N GIAO THNG

1. Ch hot ng
Thc t ti mi giao l, h thng n giao thng lun c cc ch hot ng
khc nhau nh: ch gi cao im, ch bnh thng, ch gi thp im (ban
m sau 22h) v i khi c ch t ng nhng ng khi giao nhau vi ng tu
ha Nhng v y l bi tiu lun nn em ch xy dng h thng iu khin n giao
thng ch bnh thng: n xanh 20s, n vng 5s v n 25s trn 2 lan
ng.
2. Cc thnh phn chnh ca h thng
H thng n giao thng gm 4 phn chnh sau:
- Mch iu khin trung tm dng vi iu khin AT89S52.
- Mch dao ng, reset.
- Mch hin th thi gian m li dng Led 7 on.
- Mch hin th n trng thi: xanh, vng, .
3. Cc linh kin s dng
- Vi iu khin AT89S52.
- 4 Led 7 on ( Ant chung) hin th thi gian m li.
- 6 Led trng thi: 2 xanh l, 2 vng v 2 .
- 4 transistor C828A (NPN).
- 1 IC n p 7805.
- 1 in tr thanh 10K.
- 1 thch anh 12MHz v 2 t gm 33pF.
- 1 t ha 10 F v cc tr loi 1k - 10k.
- 1 cng tc ngun v 1 ngun pin 9V.

15
Phan Hu an - in t vin thng K34

4. Nguyn l hot ng
Mch n giao thng hot ng da trn ni dung lp trnh cho vi iu khin
AT89S52. AT89S52 a d liu n cc Led trng thi ( xanh, vng, ) iu khin
cc Led ny ng, m. Ngoi ra, n cn xut d liu n cc transistor tng dng
cho cc Led 7 on, cc transistor s iu khin vic ng m cc Led 7 on bng
vic m thi gian li.
Nh vy mi khi bt u thc hin vic m li, nu trc l ny n xanh hoc
n vng th trc l bn kia s n v ngc li. AT89S52 s xut ra cc cng I/O
nhng xung cc mc cao hoc mc thp iu khin cc transistor t iu khin
cc n hin th.

5. S thut ton
Ch bnh
thng
Begin

Chng trnh
chnh

Ch bnh
thng

Ch iu khin

End.

a) S thut ton tng qut

Bt n xanh 1

Bt n 1

Bt n 2

Bt n xanh 2

Chy chng trnh

qut Led 7 on v
m li thi gian.

Chy chng trnh

qut Led 7 on v
m li thi gian.

Bt n vng 1

Bt n 1

Bt n 2

Bt n vng 2

Chy chng trnh

qut Led 7 on v
m li thi gian.

Chy chng trnh

qut Led 7 on v
m li thi gian.

b) S thut ton chi tit

16
Phan Hu an - in t vin thng K34

6. S mch

6.1. S nguyn l trn ISIS ca phn mm Protues

6.2. S mch in
17
Phan Hu an - in t vin thng K34

6.3. Hnh nh thit k 3D trn ARES ca phn mm Protues

6.4. Hnh nh thc t

18
Phan Hu an - in t vin thng K34

7. Chng trnh lp trnh Assembly

ORG 00H
MAIN:
CALL CTA
CALL CTB
CALL CTC
CALL CTD
JMP MAIN
CTA:
MOV P1,#10000100B
MOV R0,#20
MOV R1,#25
LAPA:
CALL HIENTHI
DEC R0
DEC R1
CJNE R0,#5,LAPA
RET

CTB:
MOV P1,#01000100B
MOV R0,#5
MOV R1,#5
LAPB:
CALL HIENTHI
DEC R0
19
Phan Hu an - in t vin thng K34

DEC R1
CJNE R0,#0,LAPB
RET

CTC:
MOV P1,#00110000B
MOV R0,#25
MOV R1,#20
LAPC:
CALL HIENTHI
DEC R0
DEC R1
CJNE R0,#5,LAPC
RET

CTD:
MOV P1,#00101000B
MOV R0,#5
MOV R1,#5
LAPD:
CALL HIENTHI
DEC R0
DEC R1
CJNE R0,#0,LAPD
RET

20
Phan Hu an - in t vin thng K34

HIENTHI:
MOV R7,#100
QUET:
MOV P0,#00H
MOV A,R0
MOV B,#10
DIV AB
MOV DPTR,#MALED
MOVC A,@A+DPTR
MOV P2,A
SETB P0.0
CALL DELAY
CLR P0.0
MOV A,B
MOVC A,@A+DPTR
MOV P2,A
SETB P0.1
CALL DELAY
CLR P0.1

MOV A,R1
MOV B,#10
DIV AB
MOV DPTR,#MALED
MOVC A,@A+DPTR
MOV P2,A
21
Phan Hu an - in t vin thng K34

SETB P0.2
CALL DELAY
CLR P0.2
MOV A,B
MOVC A,@A+DPTR
MOV P2,A
SETB P0.3
CALL DELAY
CLR P0.3
DJNZ R7,QUET

RET
MALED:DB
11000000B,11111001B,10100100B,10110000B,10011001B,10010010B,10000010B,1
1111000B,10000000B,10010000B
RET

DELAY:
MOV R4,#30
LAP:MOV R5,#35
LAPM:
NOP
DJNZ R5,LAPM
DJNZ R4,LAP
RET
END

22
Phan Hu an - in t vin thng K34

8. Nhn xt ca gio vin

............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................
............................................................................................................................................

23
Phan Hu an - in t vin thng K34