Jan 7, 2010 Agrawal: Low Power CMOS Design 1

Vishwani D. Agrawal
James J. Danaher Professor
ECE Dept., Auburn University, Auburn, AL 36849
www.eng.auburn.edu/~vagrawal

23
rd
International Conference on VLSI Design
Education Forum, January 7, 2010
Bangalore, India
Jan 7, 2010 Agrawal: Low Power CMOS Design 2
F. M. Wanlass and C. T. Sah, Nanowatt Logic using Field-Effect
Metal-Oxide-Semiconductor Triodes, IEEE International Solid-
State Circuits Conference Digest, vol. IV, February 1963, pp.
32-33.
No static leakage
path exists for either
1 or 0 input.
Jan 7, 2010 Agrawal: Low Power CMOS Design 3
V
DD

Ground
C
L
R
R
Dynamic Power
= C
L
V
DD
2
/2 + P
sc


Static power
= V
DD
I
leakage

V
i
V
o
i
sc
Jan 7, 2010 Agrawal: Low Power CMOS Design 4
Why is it a concern?
Jan 7, 2010 Agrawal: Low Power CMOS Design 5
Ten years from now,
microprocessors will run at 10GHz
to 30GHz and be capable of
processing 1 trillion operations per
second about the same number of
calculations that the world's fastest
supercomputer can perform now.

Unfortunately, if nothing changes
these chips will produce as much
heat, for their proportional size, as a
nuclear reactor. . . .
Patrick P. Gelsinger
Senior Vice President
General Manager
Digital Enterprise Group
INTEL CORP.

Jan 7, 2010 Agrawal: Low Power CMOS Design 6
4004
8008
8080
8085
8086
286
386
486
Pentium
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
P
o
w
e
r

D
e
n
s
i
t
y

(
W
/
c
m
2
)

Hot Plate
Nuclear
Reactor
Rocket
Nozzle
Suns
Surface
Source: Intel
Design practices that reduce power
consumption by at least one order of
magnitude; in practice 50%
reduction is often acceptable.
Low-power design methods:
Algorithms and architectures
High-level and software techniques
Gate and circuit-level methods
Test power
Jan 7, 2010 Agrawal: Low Power CMOS Design 7
Dynamic Power
Signal transitions
Logic activity
Glitches
Short-circuit
Static Power
Leakage
Jan 7, 2010 Agrawal: Low Power CMOS Design 8
P
total
= P
dyn
+ P
stat

= P
tran
+ P
sc
+ P
stat
Then


= P
tran
+ P
sc
+ P
stat
Now
Each transition of a gate consumes CV
2
/2.
Methods of power saving:
Minimize load capacitances
Transistor sizing
Reduce transitions
Logic design
Glitch reduction
Jan 7, 2010 Agrawal: Low Power CMOS Design 9
Design a digital circuit for minimum transient
energy consumption by eliminating hazards
Jan 7, 2010 Agrawal: Low Power CMOS Design 10
Total transitions = 6
Essential transitions = 2
Glitch transitions = 4
Jan 7, 2010 Agrawal: Low Power CMOS Design 11
Delay
D < DPD
A



B
C
A
B



C
D D Hazard or glitch
DPD
DPD: Differential path delay
time
Jan 7, 2010 Agrawal: Low Power CMOS Design 12
Delay
D < DPD
A



B
C
A
B



C
D
No glitch
DPD
Delay buffer
time
Jan 7, 2010 Agrawal: Low Power CMOS Design 13
Delay
D > DPD
A



B
C
A
B



C
D > DPD
Filtered glitch
DPD
time

Maintain specified critical path delay.
Glitch suppressed at all gates by
Path delay balancing
Glitch filtering by increasing inertial delay of gates or by
inserting delay buffers when necessary.
A linear program optimally combines all objectives.
Jan 7, 2010 Agrawal: Low Power CMOS Design 14
Delay
D
Path delay = d1
Path delay = d2
Minimum transient energy condition: |d1 d2| < D
Variables: gate and buffer delays, arrival time
variables.
Objective: minimize number of delay buffers.
Subject to: overall circuit delay constraint for all
input-output paths.
Subject to: minimum transient energy condition for
all multi-input gates.
Reference:
T. Raja, V. D. Agrawal and M. L. Bushnell, Variable Input
Delay CMOS Logic for Low Power Design, IEEE Trans.
CAD, vol. 17, no. 10, pp. 1534-1545, Oct. 2009.

Jan 7, 2010 Agrawal: Low Power CMOS Design 15
Jan 7, 2010 Agrawal: Low Power CMOS Design 16
1
1
Critical path delay = 6
1
1
1
1
1
1
1
Jan 7, 2010 Agrawal: Low Power CMOS Design 17
Gate delay variables: d
4
. . . d
12
Buffer delay variables: d
15
. . . d
29
Arrival time variables (earliest): t
4
. . . T
29

(longest): T
4
. . . . T
29

For Gate 7:
T
7
T
5
+ d
7
t
7
t
5
+ d
7
d
7
> T
7
- t
7

T
7
T
6
+ d
7
t
7
t
6
+ d
7
Jan 7, 2010 Agrawal: Low Power CMOS Design 18
Jan 7, 2010 Agrawal: Low Power CMOS Design 19
T
16
+ d
19
= T
19

t
16
+ d
19
= t
19

Buffer 19:
T
11
maxdelay
T
12
maxdelay
maxdelay is specified
Jan 7, 2010 Agrawal: Low Power CMOS Design 20
Need to minimize the number of buffers.
Because that leads to a nonlinear objective
function, we use an approximate criterion:
minimize (all buffer delays)
i.e., minimize d
15
+ d
16
+ + d
29

This gives near optimum results.
Jan 7, 2010 Agrawal: Low Power CMOS Design 21
Jan 7, 2010 Agrawal: Low Power CMOS Design 22
1
2
Critical path delay = 6
2
1
1
1
1
2
1
2
1
Jan 7, 2010 Agrawal: Low Power CMOS Design 23
1
1
Critical path delay = 7
3
2
1
1
1
2
1
2
Jan 7, 2010 Agrawal: Low Power CMOS Design 24
1
4
Critical path delay = 11
5
3
3
1
1
2
1
Jan 7, 2010 Agrawal: Low Power CMOS Design 25
Power Saving: Average 58%, Peak 68%
Jan 7, 2010 Agrawal: Low Power CMOS Design 26
Dynamic Power
Signal transitions
Logic activity
Glitches
Short-circuit
Static Power
Leakage
Jan 7, 2010 Agrawal: Low Power CMOS Design 27
Jan 7, 2010 Agrawal: Low Power CMOS Design 28
65nm CMOS technology:
Low threshold transistors, gate delay 5ps, leakage current 10nA.
High threshold transistors, gate delay 12ps, leakage 1nA.
Minimize leakage current without increasing critical path delay. What is the
percentage reduction in leakage power?
What will be leakage power reduction if 30% critical path delay increase is allowed?
Jan 7, 2010 Agrawal: Low Power CMOS Design 29
Reduction in leakage power = 1 (41+710)/(1110) = 32.73%
Critical path delay = 25ps
5ps
5ps
5ps
5ps
5ps
5ps
5ps
12ps
12ps
12ps
12ps
Jan 7, 2010 Agrawal: Low Power CMOS Design 30
Several solutions are possible. Notice that any 3-gate path can have 2 high threshold
gates. Four and five gate paths can have only one high threshold gate. One solution
is shown in the figure below where six high threshold gates are shown with shading
and the critical path is shown by a dashed red line arrow.

Reduction in leakage power = 1 (61+510)/(1110) = 49.09%
Critical path delay = 29ps
12ps
12ps
12ps
12ps
12ps
12ps
5ps
5ps
5ps
5ps
5ps
Assign every gate i an integer [0,1] variable Xi.
Define ILP constraints for critical path delay.
Define objective function to minimize total
leakage.
Let ILP find values of Xis:
If Xi = 1, assign low threshold to gate i
If Xi = 0, assign high threshold to gate i

Jan 7, 2010 Agrawal: Low Power CMOS Design 31
1 1.1 1.2 1.3 1.4 1.5
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Normalized Critical Path Delay
N
o
r
m
a
l
i
z
e
d

L
e
a
k
a
g
e

P
o
w
e
r
C432
C880
C1908
Jan 7, 2010 Agrawal: Low Power CMOS Design 32
0
100
200
300
400
500
600
700
800
900
M
i
c
r
o
w
a
t
t
s
Original circuit Optimized
design
Leakage power
Dynamic power
Total power
Jan 7, 2010 Agrawal: Low Power CMOS Design 33
Y. Lu and V. D. Agrawal, CMOS
Leakage and Glitch
Minimization for Power-
Performance Tradeoff, Journal
of Low Power Electronics
(JOLPE), vol. 2, no. 3, pp. 378-
387, December 2006.
Jan 7, 2010 Agrawal: Low Power CMOS Design 34
M2
R4
A datapath
R1 R2
M1
R3
Jan 7, 2010 Agrawal: Low Power CMOS Design 35
LFSR1 LFSR2
M1
M2
MISR1 MISR2
Test time
T
e
s
t

p
o
w
e
r


T1: test for M1
T2: test for M2
Jan 7, 2010 Agrawal: Low Power CMOS Design 36
R1 LFSR2
M1
M2
MISR1 MISR2
Test time
T
e
s
t

p
o
w
e
r


T1: test for M1
T2: test for M2
Test resources: Typically registers and
multiplexers that can be reconfigured as test
pattern generators (e.g., LFSR) or as output
response analyzers (e.g., MISR).
Test resources (R1, . . .) and tests (T1, . . .) are
identified for the system to be tested.
Each test is characterized for test time, power
dissipation and resources it requires.
Jan 7, 2010 Agrawal: Low Power CMOS Design 37
Jan 7, 2010 Agrawal: Low Power CMOS Design 38
T1 T2 T3 T4 T5 T6
R2 R1 R3 R4 R5 R6 R7 R8 R9
Reference:
R. M. Chou, K. K. Saluja and V. D. Agrawal, Scheduling
Tests for VLSI Systems Under Power Constraints, IEEE
Trans. VLSI Systems, vol. 5, no. 2, pp. 175-185, June 1997.
Jan 7, 2010 Agrawal: Low Power CMOS Design 39
T1
(2, 100)
T2
(1,10)
T3
(1, 10)
T4
(1, 5)
T5
(2, 10)
T6
(1, 100)
Tests that form a
clique can be
performed concurrently
(test session)
Power
Test time
Pmax = 4
CLIQUE NO. i TEST SESSION
TEST LENGTH, Li POWER, Pi
1 T1, T3, T5 100 5
2 T1, T3, T4 100 4
3 T1, T6 100 3
4 T1, T5 100 4
5 T1, T4 100 3
6 T1. T3 100 3
7 T2, T6 100 2
8 T2, T5 10 3
9 T3, T5 10 3
10 T3, T4 10 2
11 T1 100 2
12 T2 10 1
13 T3 10 1
14 T4 5 1
15 T5 10 2
16 T6 100 1
Jan 7, 2010 Agrawal: Low Power CMOS Design 40
For each clique (test session) i, define:
Integer variable, xi = 1, test session selected, or xi = 0,
test session not selected.
Constants, Li = test length, Pi = power.
Constraints to cover all tests:
T1 is covered if x1 + x2 + x3 + x4 + x5 + x6 + x11 1
Similar constraint for each test, Tk
Constraints for power: Pi xi Pmax

Jan 7, 2010 Agrawal: Low Power CMOS Design 41
Objective function:
Minimize Li xi
all cliques
Solution:
x3 = x8 = x10 = 1, all other xis are 0
Test session 3 includes T1 and T6
Test session 8 includes T2 and T5
Test session 10 includes T3 and T4
Test length = L3 + L8 + L10 = 120
Peak power = max {P3, P8, P10} = 3 (Pmax = 4)
Jan 7, 2010 Agrawal: Low Power CMOS Design 42
Underlying theme in our research use of
mathematical optimization methods for power
reduction at gate level:
Dynamic power
Leakage power
Power minimization under process variation
Test power
Other research
Min-max power estimation
Architecture level power management
Software, instruction set
Multicore


Jan 7, 2010 Agrawal: Low Power CMOS Design 43
T. Raja, MS 2002, PhD 2004 (NVIDIA)
S. Uppalapati, MS 2004 (Intel)
F. Hu, PhD 2006 (Intel)
Y. Lu, PhD 2007 (Intel)
J. D. Alexander, MS 2008 (Texas Instruments)
K. Sheth, MS 2008
M. Allani, PhD
J. Yao, PhD
K. Kim, PhD
M. Kulkarni, MS

Jan 7, 2010 Agrawal: Low Power CMOS Design 44
Dissertations:
http://www.eng.auburn.edu/~vagrawal/THESIS/thesis.html
Papers:
http://www.eng.auburn.edu/~vagrawal/TALKS/talks.html
Jan 7, 2010 Agrawal: Low Power CMOS Design 45