CMP 231 Cristiano W.

Arajo
An RTOS in Hardware for Energy
Efficient
Software-based TCP/IP Processing
CMP 231 Cristiano W. Arajo
Goals
Target Network Applications
Reduce NRE ( Non Recurring Engineering )
Reduce Time and energy consumption
TCP/IP Packet processing
Task schedule and management
RTOS queues management




CMP 231 Cristiano W. Arajo
Typical TCP/IP application architecture
Hardware
RTOS
Header
Rearrangement
TCP
checksum
Memory
copy
Protocol
processing
Application
processing
SOFTWARE HARDWARE
RTOS
CMP 231 Cristiano W. Arajo
ARTESSO TCP/IP application architecture
Hardware
RTOS
Header
Rearrangement
TCP
checksum
Memory
copy
Protocol
processing
Application
processing
SOFTWARE HARDWARE
RTOS
CMP 231 Cristiano W. Arajo
Architecture
Hardwired RTOS + CPU Core
Proposed innovation
Header rearrangement HW
No innovation
Dedicated TCP checksum HW
No innovation
Memory Copy using DMA
No innovation
CMP 231 Cristiano W. Arajo
Hardwired RTOS
Implements uTron 4.0 Specification
256 tasks supported
Parcial SW implementation
Architecture
RISC CPU
Virtual Queue



CMP 231 Cristiano W. Arajo
Virtual Queue
Stores queue order in register
(Instead of unsed large queues)
Retrieves element from queue
Power x Speed ? ( not shown )


T1
T2
T4
Q1
Q2
Q3
1
1
2
2
3
4
CMP 231 Cristiano W. Arajo
Time Comparison
Power Analysis of Embedded Operating
Systems ( Robert P. Dick et. All ) IEEE 2000
32.10%
72.80%
2.70%
2.80%
10.50%
92.70%
15.30%
32.20%
9.90%
4.50%
27.20%
97.30%
Application (no sub-
division)
Memory Copy
TCP Checksum
Header Rearrangement
Protocol Processing
RTOS
CMP 231 Cristiano W. Arajo
Critics
TCP/IP application can be rearranjed to 1%
RTOS power consumption using SW

TCP Offload Engine already used in
1Gbs/10Gbs interfaces

Sell 2 diferent concepts
HW RTOS
TCP specific HW

CMP 231 Cristiano W. Arajo
Conclusion
Product:
Kernelon Silicion main product.
Website News dated in Jan. 2011
Virtual Queue
A new way to implement RTOS in Hardware ?