//////////////////////////////////////////////////////////////////////////////////

// Company:
// Engineer:
//
// Create Date: 10:45:44 05/09/2014
// Design Name:
// Module Name: rashmi
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rashmi( input s0, s1, rst,
output enable1,enable2,

output reg [6:0]m,

output reg [6:0]r
);

reg [3:0] tensbcd;

reg [3:0] onesbcd;
reg [21:0]count;
//reg sclk;

reg i,d,s,a,b;
reg x,y;
always@(s0,rst,s)
begin
if(rst=='b1 || b=='b1 || s=='b1)
x='b0;
else
if(s0=='b1 && s1=='b0 )
x='b1;
end

always@( s1,rst,s)
begin

if(rst=='b1 || a=='b1 || s=='b1)

y='b0;
else
if(s1=='b1 && s0=='b0 )
y='b1;

end

always @(x,s1,y,s0,i,d)
begin
i= x && s1;
d= y && s0;
s= i || d;
end

////////////////////////////////////////////////////////////////

always@( s,rst,onesbcd,tensbcd,s0,s1)
begin

if(rst=='b1 )
begin
onesbcd='b0000;
tensbcd='b0000;

a='b0;
b='b0;

end
else

if(i=='b1)
begin
onesbcd=onesbcd+1;
if(onesbcd>'b1001)
begin
tensbcd=tensbcd+1;
onesbcd='b0000;
end
else if(tensbcd>'b1001)
begin
tensbcd='b0000;
onesbcd='b0000;
end
a='b1;
b='b0;
end

if(d=='b1)
begin
onesbcd=onesbcd-1;
if(onesbcd=='b0000)

begin
tensbcd=tensbcd-1;
onesbcd='b1001;

end

b='b1;
a='b0;
end

if(s0=='b0 && s1=='b0)

begin
a='b0;
b='b0;
end
end

/*always @(posedge clk)

begin
count=count+1;
sclk=count[21];
end*/

/*always@ (posedge sclk)

begin
if (rst)
begin
tensbcd='b0;
onesbcd='b0;
end
else

onesbcd=onesbcd+'b1;

if(onesbcd>'d9)
begin

onesbcd='d0;
tensbcd=tensbcd+'b1;
end

else
tensbcd=tensbcd;

end*/

always@(onesbcd)
begin
case(onesbcd)
'd0:m=7'b0000001;
'd1:m=7'b0011111;
'd2:m=7'b0100100;
'd3:m=7'b0001100;
'd4:m=7'b0011010;
'd5:m=7'b1001000;
'd6:m=7'b1000000;
'd7:m=7'b0011101;
'd8:m=7'b0000000;
'd9:m=7'b0001000;
default:m=7'b1111110;
endcase
end

always@(tensbcd)
begin
case(tensbcd)
'd0:r=7'b0000001;
'd1:r=7'b0011111;
'd2:r=7'b0100100;
'd3:r=7'b0001100;

'd4:r=7'b0011010;
'd5:r=7'b1001000;
'd6:r=7'b1000000;
'd7:r=7'b0011101;
'd8:r=7'b0000000;
'd9:r=7'b0001000;
default:r=7'b1111110;
endcase
end

assign enable1='b1;
assign enable2='b1;
endmodule