BJT Small Signal Model and AC ampliers

B
v
BE
v

v
sat
i i
C
v
CE
We calculated the DC behavior of
the BJT (DC biasing) with a sim-
ple large-signal model as shown. In
active-linear region, this model is
simply: v
BE
= 0.7 V, i
C
= i
B
.
This model is sucient for calcu-
lating the Q point as we are only
interested in ensuring sucient de-
sign space for the amplier, i.e., Q
point should be in the middle of
the load line in the active linear re-
gion. In fact, for our good biasing
scheme with negative feedback, the
Q point location is independent of
BJT parameters. (and, therefore,
independent of model used!)
A comparison of the simple model
with the iv characteristics of the
BJT shows that our simple large-
signal model is very crude and is
not accurate for AC analysis.
For example, the input AC signal results in small changes in v
BE
around 0.7 V (Q point) and
corresponding changes in i
B
. The simple model cannot be used to calculate these changes
(It assume v
BE
is constant!). Also for a xed i
B
, i
C
is not exactly constant as is assumed in
the simple model (see i
C
vs v
CE
graphs). As a whole, the simple large signal model is not
sucient to describe the AC behavior of BJT ampliers where more accurate representations
of the amplier gain, input and output resistance, etc. are needed.
A more accurate, but still linear, model can be developed by assuming that the changes in
transistor voltages and currents due to the AC signal are small compared to corresponding
Q-point values and using a Taylor series expansion. Consider function f(x). Suppose we
know the value of the function and all of its derivative at some known point, x
0
. Then, value
ECE60L Lecture Notes, Winter 2002 57
of the function in the neighborhood of x
0
can be found from the Taylor Series expansion as:
f(x
0
+ x) = f(x
0
) + x
df
dx

x=x
0
+
(x)
2
2
d
2
f
dx
2

x=x
0
+ ...
Close to our original point of x
0
, x is small and the high order terms of this expansion
(terms with (x)
n
, n = 1, 2, 3, ...) usually become very small. Typically, we consider only
the rst order term, i.e.,
f(x
0
+ x) f(x
0
) + x
df
dx

x=x
0
The Taylor series expansion can be similarly applied to function of two or more variables
such as f(x, y):
f(x
0
+ x, y
0
+ y) f(x
0
, y
0
) + x
f
x

x
0
,y
0
+ y
f
y

x
0
,y
0
In a BJT, there are four parameters of interest: i
B
, i
C
, v
BE
, and v
CE
. The BJT iv charac-
teristics plots, specify two of the above parameters, v
BE
and i
C
in terms of the other two,
i
B
and v
CE
, i.e., v
BE
is a function of i
B
and v
CE
(written as v
BE
(i
B
, v
CE
) similar to f(x, y))
and i
C
is a function of i
B
and v
CE
, i
C
(i
B
, v
CE
).
Lets assume that BJT is biased and the Q point parameters are I
B
, I
C
, V
BE
and V
CE
. We
now apply a small AC signal to the BJT. This small AC signal changes v
CE
and i
B
by small
values around the Q point:
i
B
= I
B
+ i
B
v
CE
= V
CE
+ v
CE
The AC changes, i
B
and v
CE
results in AC changes in v
BE
and i
C
that can be found
from Taylor series expansion in the neighborhood of the Q point, similar to expansion of
f(x
0
+ x, y
0
+ y) above:
v
BE
(I
B
+ i
B
, V
CE
+ v
CE
) = V
BE
+
v
BE
i
B
i
B
+
v
BE
v
CE
v
CE
i
C
(I
B
+ i
B
, V
CE
+ v
CE
) = I
C
+
i
C
i
B
i
B
+
i
C
v
CE
v
CE
where all partial derivatives are calculated at the Q point and we have noted that at the Q
point, v
BE
(I
B
, V
CE
) = V
BE
and i
C
(I
B
, V
CE
) = I
C
. We can denote the AC changes in v
BE
ECE60L Lecture Notes, Winter 2002 58
and i
C
as v
BE
and i
C
, respectively:
v
BE
(I
B
+ i
B
, V
CE
+ v
CE
) = V
BE
+ v
BE
i
C
(I
B
+ i
B
, V
CE
+ v
CE
) = I
C
+ i
C
So, by applying a small AC signal, we have changed i
B
and v
CE
by small amounts, i
B
and
v
CE
, and BJT has responded by changing , v
BE
and i
C
by small AC amounts, v
BE
and
i
C
. From the above two sets of equations we can nd the BJT response to AC signals:
v
BE
=
v
BE
i
B
i
B
+
v
BE
v
CE
v
CE
, i
C
=
i
C
i
B
i
B
+
i
C
v
CE
v
CE
where the partial derivatives are the slope of the iv curves near the Q point. We dene
h
ie

v
BE
i
B
, h
re

v
BE
v
CE
, h
fe

i
C
i
B
, h
oe

i
C
v
CE
Thus, response of BJT to small signals can be written as:
v
BE
= h
ie
i
B
+ h
re
v
CE
i
C
= h
fe
i
B
+ h
oe
v
CE
which is our small-signal model for BJT.
We now need to relate the above analytical model to circuit elements so that we can solve
BJT circuits. Consider the expression for v
BE
v
BE
= h
ie
i
B
+ h
re
v
CE
Each term on the right hand side should have units of Volts. Thus, h
ie
should have units of
resistance and h
re
should have no units (these are consistent with the denitions of h
ie
and
h
re
.) Furthermore, the above equation is like a KVL: the voltage drop between base and
emitter is written as sum of voltage drops across two elements. The voltage drop across the
rst element is h
ie
i
B
. So, it is resistor with a value of h
ie
. The voltage drop across the
second element is h
re
v
CE
. Thus, it is dependent voltage source.
-
+
ie
V = h i
B 1
i

v
re 2 CE
V = h v

re CE
h v

v
ie
-
h
+ +
-
+
+
-
-
E
B
E
B
ECE60L Lecture Notes, Winter 2002 59
Now consider the expression for i
C
:
i
C
= h
fe
i
B
+ h
oe
v
CE
Each term on the right hand side should have units of Amperes. Thus, h
fe
should have no
units and h
oe
should have units of conductance (these are consistent with the denitions of
h
oe
and h
fe
.) Furthermore, the above equation is like a KCL: the collector current is written
as sum of two currents. The current in rst element is h
fe
i
B
. So, it is dependent current
source. The current in the second element is proportional to h
oe
/v
CE
. So it is a resistor
with the value of 1/h
oe
.
B fe
h i
1/h
oe
i
C
i
C
i = h i
1 fe B

CE
v
2
i = h
oe

CE
v

CE
v

+
-
E
C
+
-
E
C
B fe
h i
1/h
oe
i
C
-
+

CE
v
BE
v
re
h v
CE

_
+
B
E
C
-
+
E
B
ie
h
i
Now, if put the models for BE and
CE terminals together we arrive at
the small signal hybrid model for
BJT. It is similar to the hybrid
model for a two-port network (Carl-
son Chap. 14).
The small-signal model is mathematically valid only for signals with small amplitude. But
the model is so useful that is often used for sinusoidal signals with amplitudes approaching
those of Q-point parameters by using average values of h parameters. h parameters are
given in manufacturers spec sheets for each BJT. It should not be surprising to note that
even in a given BJT, h parameter can vary substantially depending on manufacturing
statistics, operating temperature, etc. Manufacturers spec sheets list these h parameters
and give the minimum and maximum values. Traditionally, the geometric mean of the
minimum and maximum values are used as the average value in design (see table).
Since h
fe
= i
C
/i
B
, BJT = i
C
/i
B
is sometimes called h
FE
in manufacturers spec sheets
and has a value quite close to h
fe
. In most electronic text books, , h
FE
and h
fe
are used
interchangeably.
ECE60L Lecture Notes, Winter 2002 60
Typical hybrid parameters of a general-purpose 2N3904 NPN BJT
Minimum Maximum Average*
r

= h
ie
(k) 1 10 3
h
re
0.5 10
4
8 10
4
2 10
4
h
fe
100 400 200
h
oe
(S) 1 40 6
r
o
= 1/h
oe
(k) 25 1,000 150
r
e
= h
ie
/h
fe
() 10 25 15
* Geometric mean.
As h
re
is small, it is usually ignored in analytical calculations as it makes analysis much
simpler. This model, called the hybrid- model, is most often used in analyzing BJT circuits.
In order to distinguish this model from the hybrid model, most electronic text books use a
dierent notation for various elements of the hybrid- model:
r

= h
ie
r
o
=
1
h
oe
= h
fe

B fe
h i
1/h
oe
i
C
i
B
ie
h
BE
v
C B
+
_
E
i
C
i
B
C B
+
_
E
v

B
i
r
o
r
BE
=
The above hybrid- model includes a current-controlled current source. This implies that
BJT behavior is controlled by i
B
. In reality, v
BE
controls the BJT behavior. A variant of the
hybrid- model can be developed which includes a voltage-controlled current source. This
can be achieved by noting it the above model that v
BE
= h
ie
i
B
and
i
C
i
B
r
o

m BE
g v

BE
v
C B
E
+
_
h
fe
i
B
= h
fe
v
BE
h
ie
= g
m
v
BE
g
m

h
fe
h
ie
Transfer conductance
r
e

1
g
m
=
h
ie
h
fe
Emitter resistance
ECE60L Lecture Notes, Winter 2002 61
BJT Amplier Circuits
As we have developed dierent models for DC signals (simple large-signal model) and AC
signals (small-signal model), analysis of BJT circuits follows these steps:
DC biasing analysis: Assume all capacitors are open circuit. Analyze the transistor circuit
using the simple large signal mode as described in pp 57-58.
AC analysis:
1) Kill all DC sources
2) Assume coupling capacitors are short circuit. The eect of these capacitors is to set a
lower cut-o frequency for the circuit. This is analyzed in the last step.
3) Inspect the circuit. If you identify the circuit as a prototype circuit, you can directly use
the formulas for that circuit. Otherwise go to step 3. 3) Replace the BJT with its small
signal model.
4) Solve for voltage and current transfer functions and input and output impedances (node-
voltage method is the best).
5) Compute the cut-o frequency of the amplier circuit.
Several standard BJT amplier congurations are discussed below and are analyzed. Because
most manufacturer spec sheets quote BJT h parameters, I have used this notation for
analysis. Conversion to notation used in most electronic text books (r

, r
o
, and g
m
) is
straight-forward.
Common Collector Amplier (Emitter Follower)
R
E
R
2
V
CC
v
i
v
o
R
1
c
C
DC analysis: With the capacitors open circuit, this circuit is the
same as our good biasing circuit of page 57 with R
c
= 0. The
bias point currents and voltages can be found using procedure
of pages 57 and 58.
AC analysis: To start the analysis, we kill all DC sources:
R
E
v
o
R
1
R
2
v
i
R
E
R
2
v
i
v
o
R
1
CC
V = 0
c
C C
E
c
C
B
ECE60L Lecture Notes, Winter 2002 62
We can combine R
1
and R
2
into R
B
(same resistance that we encountered in the biasing
analysis) and replace the BJT with its small signal model:
v
i
R
B
h i
fe B
E
R
E 1/h
oe
i
B
ie
h
o
v
C
v
i

B fe
h i
1/h
oe
i
C
ie
h
i
B
v
o
R
E
C
c

BE
v
C
B c
E
B
_
+
C
B
R
The gure above shows why this is a common collector conguration: collector is shared
between input and output AC signals. We can now proceed with the analysis. Node voltage
method is usually the best approach to solve these circuits. For example, the above circuit
will have only one node equation for node at point E with a voltage v
o
:
v
o
v
i
r

+
v
o
0
r
o
i
B
+
v
o
0
R
E
= 0
Because of the controlled source, we need to write an auxiliary equation relating the control
current (i
B
) to node voltages:
i
B
=
v
i
v
o
r

Substituting the expression for i

B
in our node equation, multiplying both sides by r

, and
collecting terms, we get:
v
i
(1 + ) = v
o
_
1 + + r

_
1
r
o
+
1
R
E
__
= v
o
_
1 + +
r

r
o
R
E
_
Amplier Gain can now be directly calculated:
A
v

v
o
v
i
=
1
1 +
r

(1 + )(r
o
R
E
)
Unless R
E
is very small (tens of ), the fraction in the denominator is quite small compared
to 1 and A
v
1.
To nd the input impedance, we calculate i
i
by KCL:
i
i
= i
1
+ i
B
=
v
i
R
B
+
v
i
v
o
r

ECE60L Lecture Notes, Winter 2002 63

Since v
o
v
i
, we have i
i
= v
i
/R
B
or
R
i

v
i
i
i
= R
B
Note that R
B
is the combination of our biasing resistors R
1
and R
2
. With alternative biasing
schemes which do not require R
1
and R
2
, (and, therefore R
B
), the input resistance of
the emitter follower circuit will become large. In this case, we cannot use v
o
v
i
. Using the
full expression for v
o
from above, the input resistance of the emitter follower circuit becomes:
R
i

v
i
i
i
= R
B
[r

+ (R
E
r
o
)(1 + )]
and it is quite large (hundreds of k to several M) for R
B
. Such a circuit is in fact
the rst stage of the 741 OpAmp.
The output resistance of the common collector amplier (in fact for all transistor ampliers)
is somewhat complicated because the load can be congured in two ways (see gure): First,
R
E
, itself, is the load. This is the case when the common collector is used as a current
amplier to raise the power level and to drive the load. The output resistance of the circuit
is R
o
as is shown in the circuit model. This is usually the case when values of R
o
and A
i
(current gain) is quoted in electronic text books.
R
2
V
CC
v
i
v
o
R
L
R
1
C
c
E
= R
E
R is the Load
R
E
R
2
V
CC
v
i
v
o
R
1
C
c
R
L
Separate Load
v
i
R
B
i
B
o
v
R
E
R
o
C
c B
C
E

r
r
o

B
i
v
i
R
B
i
B
C
c
R
E
o
R
B
C
E

r
r
o

B
o
v
R
L
i
Alternatively, the load can be placed in parallel to R
E
. This is done when the common
collector amplier is used as a buer (A
v
1, R
i
large). In this case, the output resistance
is denoted by R

o
(see gure). For this circuit, BJT sees a resistance of R
E
R
L
. Obviously,
if we want the load not to aect the emitter follower circuit, we should use R
L
to be much
ECE60L Lecture Notes, Winter 2002 64
larger than R
E
. In this case, little current ows in R
L
which is ne because we are using
this conguration as a buer and not to amplify the current and power. As such, value of
R

o
or A
i
does not have much use.
v
i
R
B
i
B
R
o
i
T
v
T
C
c B
C
E
r

o
r

B
i
+

When R
E
is the load, the output resistance can
be found by killing the source (short v
i
) and nd-
ing the Thevenin resistance of the two-terminal
network (using a test voltage source).
KCL: i
T
= i
B
+
v
T
r
o
i
B
KVL (outside loop): r

i
B
= v
T
Substituting for i
B
from the 2nd equation in the rst and rearranging terms we get:
R
o

v
T
i
T
=
(r
o
) r

(1 + )(r
o
) + r

(r
o
) r

(1 + )(r
o
)
=
r

(1 + )

r

= r
e
where we have used the fact that (1 + )(r
o
) r

.
When R
E
is the load, the current gain in this amplier can be calculated by noting i
o
= v
o
/R
E
and i
i
v
i
/R
B
as found above:
A
i

i
o
i
i
=
R
B
R
E
In summary, the general properties of the common collector amplier (emitter follower)
include a voltage gain of unity (A
v
1), a very large input resistance R
i
R
B
(and can
be made much larger with alternate biasing schemes). This circuit can be used as buer for
matching impedance, at the rst stage of an amplier to provide very large input resistance
(such in 741 OpAmp). As a buer, we need to ensure that R
L
R
E
. The common collector
amplier can be also used as the last stage of some amplier system to amplify the current
(and thus, power) and drive a load. In this case, R
E
is the load, R
o
is small: R
o
= r
e
and
current gain can be substantial: A
i
= R
B
/R
E
.
Impact of Coupling Capacitor:
Up to now, we have neglected the impact of the coupling capacitor in the circuit (assumed
it was a short circuit). This is not a correct assumption at low frequencies. The coupling
capacitor results in a lower cut-o frequency for the transistor ampliers. In order to nd the
cut-o frequency, we need to repeat the above analysis and include the coupling capacitor
ECE60L Lecture Notes, Winter 2002 65
impedance in the calculation. In most cases, however, the impact of the coupling capacitor
and the lower cut-o frequency can be deduced be examining the amplier circuit model.
+

V L
o
I
o
+

i
i
+

o
AV
i
i
V
c
Voltage Amplifier Model
C
Z
R
+

V
R
Consider our general model for any
amplier circuit. If we assume that
coupling capacitor is short circuit
(similar to our AC analysis of BJT
amplier), v

i
= v
i
.
When we account for impedance of the capacitor, we have set up a high pass lter in the
input part of the circuit (combination of the coupling capacitor and the input resistance of
the amplier). This combination introduces a lower cut-o frequency for our amplier which
is the same as the cut-o frequency of the high-pass lter:

l
= 2 f
l
=
1
R
i
C
c
Lastly, our small signal model is a low-frequency model. As such, our analysis indicates
that the amplier has no upper cut-o frequency (which is not true). At high frequencies,
the capacitance between BE , BC, CE layers become important and a high-frequency small-
signal model for BJT should be used for analysis. You will see these models in upper division
courses. Basically, these capacitances results in amplier gain to drop at high frequencies.
PSpice includes a high-frequency model for BJT, so your simulation should show the upper
cut-o frequency for BJT ampliers.
ECE60L Lecture Notes, Winter 2002 66
R
C
V
CC
R
1
v
o
v
i
C
c
R
2
R
C
V
CC
R
1
v
o
v
i
C
c
C
b R
E
R
2
Good Bias using a
bypass capacitor
Poor Bias
Common Emitter Amplier
DC analysis: Recall that an emitter resistor is
necessary to provide stability of the bias point.
As such, the circuit conguration as is shown
has as a poor bias. We need to include R
E
for
good biasing (DC signals) and eliminate it for
AC signals. The solution to include an emit-
ter resistance and use a bypass capacitor to
short it out for AC signals as is shown.
For this new circuit and with the capacitors open circuit, this circuit is the same as our
good biasing circuit of page 57. The bias point currents and voltages can be found using
procedure of pages 57 and 58.
AC analysis: To start the analysis, we kill all DC sources, combine R
1
and R
2
into R
B
and
replace the BJT with its small signal model. We see that emitter is now common between
input and output AC signals (thus, common emitter amplier. Analysis of this circuit is
straightforward. Examination of the circuit shows that:
v
i
R
B
i
B
o
v
R
o
R
C
C
c B
E
C
r

B
o
r
i
v
i
= r

i
B
v
o
= (R
c
r
o
) i
B
A
v

v
o
v
i
=

r

(R
c
r
o
)

r

R
c
=
R
c
r
e
R
i
= R
B
r

R
o
= r
o
The negative sign in A
v
indicates 180

phase shift between input and output. The circuit

has a large voltage gain but has medium value for input resistance.
As with the emitter follower circuit, the load can be congured in two ways: 1) R
c
is the
load. Then R
o
= r
o
and the circuit has a reasonable current gain. 2) Load is placed in
parallel to R
c
. In this case, we need to ensure that R
L
R
c
. Little current will ow in R
L
and R
o
and A
i
values are of not much use.
Lower cut-o frequency: Both the coupling and bypass capacitors contribute to setting
the lower cut-o frequency for this amplier. After some involved analysis one arrives at:

l
= 2 f
l
=
1
R
i
C
c
+
1
(R
E
+ r
e
)C
b
ECE60L Lecture Notes, Winter 2002 67
C
V
CC
R
1
R
2
E
R
c
C
v
o
v
i
R
Common Emitter Amplier with Emitter resistance
A problem with the common emitter amplier is that its gain
depend on BJT parameters A
v
(/r

)R
c
. Some form of feed-
back is necessary to ensure stable gain for this amplier. One
way to achieve this is to add an emitter resistance. Recall im-
pact of negative feedback on OpAmp circuits: we traded gain
for stability of the output. Same principles apply here.
DC analysis: With the capacitors open circuit, this circuit is the
same as our good biasing circuit of page 57. The bias point
currents and voltages can be found using procedure of pages 57
and 58.
AC analysis: To start the analysis, we kill all DC sources, combine R
1
and R
2
into R
B
and
replace the BJT with its small signal model. Analysis is straight forward using node-voltage
method.
1
C
v
i
i
C
i
B v
o

BE
v
R
E
R
C
R
B
+
_
B
E
C

B
r
o
i
v
E
v
i
r

+
v
E
R
E
i
B
+
v
E
v
o
r
o
= 0
v
o
R
C
+
v
o
v
E
r
o
+ i
B
= 0
i
B
=
v
i
v
E
r

(Controlled source aux. Eq.)

Substituting for i
B
in the node equations and noting 1 + , we get:
v
E
R
E
+
v
E
v
i
r

+
v
E
v
o
r
o
= 0
v
o
R
C
+
v
o
v
E
r
o

v
E
v
i
r

= 0
Above are two equations in two unknowns (v
E
and v
o
). Adding the two equation together
we get v
E
= (R
E
/R
C
)v
o
and substituting that in either equations we can nd v
o
.
Alternatively, we can nd compact and simple solutions by noting that terms containing r
o
in the denominator are usually small as r
o
is quite large. In this case, the node equations
simplify to (using r

/ = r
e
):
v
E
_
1
R
E
+
1
r
e
_
=
v
i
r
e
v
E
=
R
E
R
E
+ r
e
v
i
v
o
=
R
C
r
e
(v
E
v
i
) =
R
C
r
e
_
R
E
R
E
+ r
e
1
_
v
i
=
R
C
R
E
+ r
e
v
i
ECE60L Lecture Notes, Winter 2002 68
Then, the voltage gain and input and output resistance can also be easily calculated:
A
v
=
v
o
v
i
=
R
C
R
E
+ r
e

R
C
R
E
R
i
= R
B
[(R
E
+ r
e
)] R
o
= r
e
As before the minus sign in A
v
indicates a 180

phase shift between input and output signals.

Note the impact of negative feedback introduced by the emitter resistance. The voltage gain
is independent of BJT parameters and is set by R
C
and R
E
as R
E
r
e
(recall OpAmp
inverting amplier!). The input resistance is increased dramatically.
C
V
CC
R
1
R
2
v
o
v
i
C
c
C
b
R
E1
R
R
E2
A Possible Biasing Problem: The gain of the common
emitter amplier with the emitter resistance is approximately
R
C
/R
E
. For cases when a high gain (5-20) is needed, R
E
may
be become so small that the necessary good biasing condition,
V
E
= R
E
I
E
> 1 V cannot be fullled. The solution is to use a
by-pass capacitor as is shown. The AC signal sees an emitter
resistance of R
E1
while for DC signal the emitter resistance is
R
E
= R
E1
+ R
E2
.
Lower cut-o frequency: Both the coupling and bypass ca-
pacitors contribute to setting the lower cut-o frequency for this
amplier. After some involved analysis one arrives at:

l
= 2 f
l
=
1
R
i
C
c
+
1
(R
E2
+ r
e
)C
b
Note that if the by-pass capacitor does not exist, the second term should not be included in
the expression for
l
.
ECE60L Lecture Notes, Winter 2002 69
Summary of BJT Ampliers
R
E
R
2
V
CC
v
i
v
o
R
1
c
C
C
V
CC
R
1
R
2
v
o
v
i
C
c
C
b
R
R
E
C
V
CC
R
1
R
2
v
o
v
i
C
c
C
b
R
E1
R
R
E2
Common Collector (Emitter Follower):
A
v
=
(R
E
r
o
)(1 + )
r

+ (R
E
r
o
)(1 + )
1
R
i
= R
B
[r

+ (R
E
r
o
)(1 + )] R
B
R
o
=
(r
o
) r

(1 + )(r
o
) + r

= r
e
2 f
l
=
1
R
i
C
c
Common Emitter:
A
v
=

r

(R
c
r
o
)

r

R
c
=
R
c
r
e
R
i
= R
B
r

R
o
= r
o
2 f
l
=
1
R
i
C
c
+
1
(R
E
+ r
e
)C
b
Common Emitter with Emitter Resistance:
A
v
=
R
C
R
E1
+ r
e

R
C
R
E1
R
i
= R
B
[(R
E1
+ r
e
)]
R
o
= r
e
2 f
l
=
1
R
i
C
c
+
1
(R
E2
+ r
e
)C
b
ECE60L Lecture Notes, Winter 2002 70
Examples of Analysis and Design of BJT Ampliers
Example 1: Find the bias point and AC amplier parameters of this circuit (Manufacturers
spec sheets give: h
fe
= 200, h
ie
= 5 k, h
oe
= 10 S).
r

= h
ie
= 5 k r
o
=
1
h
oe
= 100 k = h
fe
= 200 r
e
=
r

= 25
DC analysis:
v
i
v
o
0.47 F
9 V
18k
22k 1k
V
BB
I
B
BE
V
CE
V
C
I
R
B
+
_
+
_
+

9 V
1k
Replace R
1
and R
2
with their Thevenin equivalent and
proceed with DC analysis (all DC current and voltages
are denoted by capital letters):
R
B
= 18 k 22 k = 9.9 k
V
BB
=
22
18 + 22
9 = 4.95 V
KVL: V
BB
= R
B
I
B
+ V
BE
+ 10
3
I
E
I
B
=
I
E
1 +
=
I
E
201
4.95 0.7 = I
E
_
9.9 10
3
2.1
+ 10
3
_
I
E
= 4 mA I
C
, I
B
=
I
C

= 20 A
KVL: V
CC
= V
CE
+ 10
3
I
E
V
CE
= 9 10
3
4 10
3
= 5 V
DC Bias summary: I
E
I
C
= 4 mA, I
B
= 20 A, V
CE
= 5 V
AC analysis: The circuit is a common collector amplier. Using the formulas in page 70,
A
v
1
R
i
R
B
= 9.9 k
R
o
r
e
= 25
f
l
=

l
2
=
1
2R
B
C
c
=
1
2 9.9 10
3
0.47 10
6
= 36 Hz
ECE60L Lecture Notes, Winter 2002 71
Example 2: Find the bias point and AC amplier parameters of this circuit (Manufacturers
spec sheets give: h
fe
= 200, h
ie
= 5 k, h
oe
= 10 S).
r

= h
ie
= 5 k r
o
=
1
h
oe
= 100 k = h
fe
= 200 r
e
=
r

= 25
DC analysis:
v
o
v
i
4.7 F
47 F
15 V
34 k 1 k
270 5.9 k
240
V
BB
I
B
BE
V
CE
V
C
I
R
B
+
_
+
_
+

15 V
= 510
270 + 240
Replace R
1
and R
2
with their Thevenin equivalent and
proceed with DC analysis (all DC current and voltages
are denoted by capital letters). Since all capacitors are
replaced with open circuit, the emitter resistance for DC
analysis is 270 + 240 = 510 .
R
B
= 5.9 k 34 k = 5.0 k
V
BB
=
5.9
5.9 + 34
15 = 2.22 V
KVL: V
BB
= R
B
I
B
+ V
BE
+ 510I
E
I
B
=
I
E
1 +
=
I
E
201
2.22 0.7 = I
E
_
5.0 10
3
2.1
+ 510
_
I
E
= 3 mA I
C
, I
B
=
I
C

= 15 A
KVL: V
CC
= 1000I
C
+ V
CE
+ 510I
E
V
CE
= 15 1, 510 3 10
3
= 10.5 V
DC Bias summary: I
E
I
C
= 3 mA, I
B
= 15 A, V
CE
= 10.5 V
AC analysis: The circuit is a common collector amplier with an emitter resistance. Note
that the 240 resistor is shorted out with the by-pass capacitor. It only enters the formula
for the lower cut-o frequency. Using the formulas in page 70:
A
v
=
R
C
R
E1
+ r
e
=
1, 000
270 + 25
= 3.39
R
i
R
B
= 5.0 k
R
o
r
e
= 25
f
l
=

l
2
=
1
2R
i
C
c
+
1
2(R
E2
+ r
e
)C
b
=
1
25.0 10
3
4.7 10
6
+
1
2(240 + 25)47 10
6
= 20 Hz
ECE60L Lecture Notes, Winter 2002 72
Example 3: Design a BJT amplier with a gain of 4 and a lower cut-o frequency of 100 Hz.
The Q point parameters should be I
C
= 3 mA and V
CE
= 7.5 V. (Manufacturers spec sheets
give:
min
= 100, = 200, h
ie
= 5 k, h
oe
= 10 S).
C
V
CC
R
1
R
2
E
R
c
C
v
o
v
i
R
v
CE
i
C
i
B
v
BE
R
C
R
E
V
CC
V
BB
R
B
+
_
+
_
+

= h
ie
= 5 k r
o
=
1
h
oe
= 100 k r
e
=
r

= 25
The prototype of this circuit is a common emitter amplier with an
emitter resistance. Using formulas of page 70 (r
e
= r

/h
fe
= 25 ),
|A
v
| =
R
C
R
E
+ r
e

R
C
R
E
= 4
The lower cut-o frequency will set the value of C
c
.
We start with the DC bias: As V
CC
is not given, we need to
choose it. To set the Q-point in the middle of load line, set
V
CC
= 2V
CE
= 15 V. Then, noting I
C
I
E
,:
V
CC
= R
C
I
C
+ V
CE
+ R
E
I
E
15 7.5 = 3 10
3
(R
C
+ R
E
) R
C
+ R
E
= 2.5 k
Values of R
C
and R
E
can be found from the above equation
together with the AC gain of the amplier, A
V
= 4. Ignoring r
e
compared to R
E
(usually a good approximation), we get:
R
C
R
E
= 4 4R
E
+ R
E
= 2.5 k R
E
= 500 , R
C
= 2. k
Commercial values are R
E
= 510 and R
C
= 2 k. Use these commercial values for the
rest of analysis.
We need to check if V
E
> 1 V, the condition for good biasing. V
E
= R
E
I
E
= 510310
3
=
1.5 > 1, it is OK (See next example for the case when V
E
is smaller than 1 V).
We now proceed to nd R
B
and V
BB
. R
B
is found from good bias condition and V
BB
from
a KVL in BE loop:
R
B
( + 1)R
E
R
B
= 0.1(
min
+ 1)R
E
= 0.1 101 510 = 5.1 k
KVL: V
BB
= R
B
I
B
+ V
BE
+ R
E
I
E
V
BB
= 5.1 10
3
3 10
3
201
+ 0.7 + 510 3 10
3
= 2.28 V
ECE60L Lecture Notes, Winter 2002 73
Bias resistors R
1
and R
2
are now found from R
B
and V
BB
:
R
B
= R
1
R
2
=
R
1
R
2
R
1
+ R
2
= 5 k
V
BB
V
CC
=
R
2
R
1
+ R
2
=
2.28
15
= 0.152
R
1
can be found by dividing the two equations: R
1
= 33 k. R
2
is found from the equation
for V
BB
to be R
2
= 5.9 k. Commercial values are R
1
= 33 k and R
2
= 6.2 k.
Lastly, we have to nd the value of the coupling capacitor:

l
=
1
R
i
C
c
= 2 100
Using R
i
R
B
= 5.1 k, we nd C
c
= 3 10
7
F or a commercial values of C
c
= 300 nF.
So, are design values are: R
1
= 33 k, R
2
= 6.2 k, R
E
= 510 , R
C
= 2 k. and
C
c
= 300 nF.
Example 4: Design a BJT amplier with a gain of 10 and a lower cut-o frequency of
100 Hz. The Q point parameters should be I
C
= 3 mA and V
CE
= 7.5 V. A power supply
of 15 V is available. Manufacturers spec sheets give:
min
= 100, h
fe
= 200, r

= 5 k,
h
oe
= 10 S.
C
V
CC
R
1
R
2
E
R
c
C
v
o
v
i
R
r

= h
ie
= 5 k r
o
=
1
h
oe
= 100 k r
e
=
r

= 25
The prototype of this circuit is a common emitter amplier with an
emitter resistance. Using formulas of page 70:
|A
v
| =
R
C
R
E
+ r
e

R
C
R
E
= 10
The lower cut-o frequency will set the value of C
c
.
We start with the DC bias: As the power supply voltage is given, we set V
CC
= 15 V. Then,
noting I
C
I
E
,:
V
CC
= R
C
I
C
+ V
CE
+ R
E
I
E
15 7.5 = 3 10
3
(R
C
+ R
E
) R
C
+ R
E
= 2.5 k
ECE60L Lecture Notes, Winter 2002 74
Values of R
C
and R
E
can be found from the above equation together with the AC gain of
the amplier A
V
= 10. Ignoring r
e
compared to R
E
(usually a good approximation), we get:
R
C
R
E
= 10 10R
E
+ R
E
= 2.5 k R
E
= 227 , R
C
= 2.27 k
C
V
CC
R
1
R
2
v
o
v
i
C
c
C
b
R
E1
R
R
E2
v
CE
i
C
i
B
v
BE
R
C
V
CC
V
BB
R
B
R
E1
R
E2
+
_
+
_
+

+
We need to check if V
E
> 1 V which is the condition for good
biasing: V
E
= R
E
I
E
= 227 3 10
3
= 0.69 < 1. Therefore,
we need to use a bypass capacitor and modify our circuits as is
shown.
For DC analysis, the emitter resistance is R
E1
+ R
E2
while for
AC analysis, the emitter resistance will be R
E1
. Therefore:
DC Bias: R
C
+ R
E1
+ R
E2
= 2.5 k
AC gain: A
v
=
R
C
R
E1
= 10
Above are two equations in three unknowns. A third equation is
derived by setting V
E
= 1 V to minimize the value of R
E1
+R
E2
.
V
E
= (R
E1
+ R
E2
)I
E
R
E1
+ R
E2
=
1
3 10
3
= 333
Now, solving for R
C
, R
E1
, and R
E2
, we nd R
C
= 2.2 k,
R
E1
= 220 , and R
E2
= 110 (All commercial values).
We can now proceed to nd R
B
and V
BB
:
R
B
( + 1)(R
E1
+ R
E2
)
R
B
= 0.1(
min
+ 1)(R
E1
+ R
E2
) = 0.1 101 330 = 3.3 k
KVL: V
BB
= R
B
I
B
+ V
BE
+ R
E
I
E
V
BB
= 3.3 10
3
3 10
3
201
+ 0.7 + 330 3 10
3
= 1.7 V
Bias resistors R
1
and R
2
are now found from R
B
and V
B
B:
R
B
= R
1
R
2
=
R
1
R
2
R
1
+ R
2
= 3.3 k
V
BB
V
CC
=
R
2
R
1
+ R
2
=
1
15
= 0.066
ECE60L Lecture Notes, Winter 2002 75
R
1
can be found by dividing the two equations: R
1
= 50 k and R
2
is found from the
equation for V
BB
to be R
2
= 3.6k . Commercial values are R
1
= 51 k and R
2
= 3.6k
Lastly, we have to nd the value of the coupling and bypass capacitors:

l
=
1
R
i
C
c
+
1
R
E2
C
b
= 2 100
This is one equation in two unknown (C
c
and C
B
) so one can be chosen freely. Typically
C
b
C
c
as R
i
R
B
R
E
. Using R
i
R
B
= 3.3 k and choosing C
b
= 47 F, one nd
C
c
= 0.7 F (commercial value of 0.68 F).
So, are design values are: R
1
= 50 k, R
2
= 3.6 k, R
E1
= 220 , R
E2
= 110 , R
C
=
2.2 k, C
b
= 47 F, and C
c
= 680 nF.
ECE60L Lecture Notes, Winter 2002 76