(Codientu - Org) PIC18

LP TRNH VK
PIC VI MPLAB C18

HBK TPHCM BKIT4U
EDITTER: TRI - IUH

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EITTER ! TRI - IUH

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Bi 1 : Ci t MPLAB IDE 8.36

1.1 Gii thiu
MPLAB IDE l phn mm c h tr bi Microchip, dng soan tho code cho cc ng dung
ca PIC. Hin tai, thng 8/2010 MPLAB IDE c phin bn 8.51. Trong ti liu ny ti chon
phin bn 8.36 v n c kh nhiu li v cu hnh . Cc phin bn khc nh 8.43, ban c th
khng chon cu hnh ban u nhng bn thn n c th tu ng tm kim cc th vin cn
thit trong qu trnh bin dich. Vi phin bn 8.36 chng ta phi cu hnh ton b cho IDE.
1.2 Ci t MPLAB IDE 8.36
Bc 1 : Double Click vo file setup trong th muc MPLAB IDE 8.36. Mn hnh Welcome s
hin ra nh sau. Ban chon Next tip tuc.

Hnh 1.1 : Welcome to MPLAB IDE 8.36

Bc 2 : Chon I accept the term of the license agreement v chon Next.
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Hnh 1.2 : License Agreement

Bc 3 : ch mc inh l ci t Complete v chon Next tip tuc.

Hnh 1.3 : Chon ci t complete

Bc 4 : Chon ng dn ci t, ta nn mc inh l C:\Program Files\Microchip\
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Hnh 1.4 : Chon ng dn ci t

Bc 5 : Tip tuc chon I accept cho Maestro License v C32 License.

Hnh 1.5 : Maestro License
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Hnh 1.6 : C32 License

Bc 6 : Giao din sau tng kt lai cc lua chon ca ban, nhn Next tin hnh ci t. Nu
mun hiu chnh ban nhn Back.

Hnh 1.7 : Bt u ci t

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Hnh 1.8 : Ch ci t xong

Bc 7 : Khi ci t xong MPLAB IDE s hi ban c cn ci Hi Tech khng. y l compiler C
h tr cho MPLAB IDE, tuy nhin ta s khng dng compiler ny m s dng MPLAB C18. Ban
chon No nhn Finish hon tt vic ci t MPLAB IDE.

Hnh 1.9 : Ci t hon tt

Thng bo di u xut hin, thng k cc ti liu hng dn i km. Cc ti liu ny u
nm trong th muc ci t C:\Program Files\Microchip\
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Hnh 1.10 : Cc ti liu hng dn

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Bi 2 : Ci t compi!" MPLAB C18

2.1 Gii thiu
Khi ci t xong MPLAB IDE, compiler mc inh cho n l MPASM, dng dich project vit
bng ASM sang file HEX. Mun vit chong trnh bng C, ta cn phi ci t thm 1 compiler
khc c h tr cho chip PIC ang dng. Trong phn ny, ti th nghim trn vi iu khin
PIC18F4520 v chon compiler C18 h tr cho lp trnh C chun.
2.2 C#c $%c ci t
Bc 1 : Double Click vo file MPLAB C18 V1.0.exe tin hnh ci t, mn hnh welcome
ca MPLAB C18 s hin ra nh sau :

Hnh 2.1 : Welcome MPLAB C18

Bc 2 : Chon noi lu tr cho cc file bin dich ca MPLAB C18, ta c th mc inh l
C:\mcc18 .

Hnh 2.2 : Chon ng dn lu tr

Bc 3 : Chon lua cc thnh phn ca gi MCC18, thng thng ta s chon ht tt c cc gi
trong compier C18.
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Hnh 2.3 : Chon cc gi ci t

Bc 4 : Nhn Next tin hnh ci t

Hnh 2.4 : Ci t C18

Ch cho n khi ci t xong.
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Hnh 2.5 : Ch ci t C18

Bc 5 : Nhn Finish kt thc ci t MPLAB C18.

Hnh 2.6 : Kt thc ci t C18

2.3 C&p 'h&t (' C18 )!"*io' 3.+1
Phin bn m ta va ci t l C18 v1.0. cp nht ln v3.01, ta s double click v file
MPLAB-C18-pgrade-doc-v3_01.exe. Mn hnh welcome s hin ra nh sau:

Hnh 2.7 : Welcome C18 update

Chon I Accept v nhn Next tip tuc ci t.
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Hnh 2.8 : License Agreement

Cc ti liu h tr lp trnh cho compiler C18 i km.

Hnh 2.9 : Cc ti liu hng dn

Chon th muc mc inh cho vic update (ging vi th muc ci t C18)
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mc inh cc thnh phn s c ci t, khng cn phi check thm.

Hnh 2.10 : Cc gi ci t C18 v3.01

Check chon thm cc option di y MPLAB IDE tu ng cu hnh cc thng s tong thch
vi phin bn C18 v3.01
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Hnh 2.11 : Chon cu hnh update cho MPLAB IDE

Chon Next tin hnh Update

Hnh 2.12 : Tin hnh ci t

Ch cho n khi hon tt.
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Hnh 2.13 : Ch cho n khi hon tt

Nhn Finish kt thc.

Hnh 2.14 : Ci t hon tt

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Bi 3 : ,-o p"o.!ct t"(' MPLAB 8.36 ) C18 3.+1

Tao 1 project ln u trn MPLAB kh phc tap. Ngi s dung cn phi cu hnh cho MPLAB
kh nhiu. Tuy nhin hu ht cc thng s cu hnh ny s c lu lai cho ln sau, chng ta
ch cn phi thit lp 1 ln. Phn ny hng dn cch tao 1 project on gin trn MPLAB cho
chip 18F4520 v mach nap PICKit2 trn board BKIT PIC.
3.1 ,-o mi p"o.!ct
Kch hoat chong trnh MPLAB IDE 8.36 t biu tng Microchip trn mn hnh Desktop, ca s
sau y s hin ra.

Hnh 3.1 : Mn hnh khi ng ca MPLAB IDE 8.36

Chon menu Project v chon New

Hnh 3.2 : Tao mi project

Ca s sau y hin ra, ban t tn cho project khung Project Name v chon ng dn cho
n khung Project Directory.
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Hnh 3.3 : t tn v chon th muc lu tr

Ca s lm vic ca project s hin ra bn tri nh hnh di y. Nu ca s project khng
hin ra ban s chon menu View v chon Project.

Hnh 3.4 : Ca s project

Chon compile C18 cho project ny bng cch chon vo menu Project v chon Select Language
Toolsuite.
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Hnh 3.5 : Chon Language ToolSuite (Compiler)

Chon Active Toolsuite l Microchip C18 Toolsuite. Cc ng dn ca cc chong trnh trong
gi compiler cho C18 c cu hnh trong lc ci t C18 upgrade, ban khng cn phi
chnh lai. Cc gi ny u nm trong th muc C:\mcc18.

Hnh 3.6 : Chon compiler C18
3.2 C/u h0'h cho chip
Phn ny c nh hng i vi qu trnh dich v nap cho chip. Chon menu Configure v chon
Select Device. chon chip.
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Hnh 3.7 : Select Device

Giao din di y hin ra v ban chon cho ng chip m mnh ang dng. y ti chon chip
PIC18F4520.

Nhn OK ng ca s ny lai. Tip theo l vic lua chon cu hnh thach anh v 1 s cu
hnh khc. Ban vo lai menu Configure v chon Configuration Bits.
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Hnh 3.8 : Configuration Bits

Mn hnh ban cu hnh cho ch hoat ng ca chip di y hin ra. Check b du chon
Configuration Bits set in code ban c th thay i cc thng s.
Thng s u tin l ch thach anh, ty vo mi loai chip v thach anh m chon lua khc
nhau. y ti s dung thach anh ngoi 12MHz nn s chon ch thach anh l HS (High
Speed). Cc ch thach anh ca PIC18F4520 s c cp cc bi sau.

PORTB bit 4-0 ch mt inh l cc chn analog. Khi khng s dung analog ban cn phi
chnh sang ch Digital khi reset.

Disable chc nng Low Voltage Programming (LVP - Nap in p thp), mach PICKit2 khng
h tr chc nng ny.

Sau khi hon thnh ban check lai Configuration Bits set in code v ng ca s ny lai.
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Hnh 3.9 : Thit lp thach anh, PortB, LVP

3.3 ,-o mi 1i! ) 233 th% )i' cho p"o.!ct
Bc tip theo l tao file source vit code. T toolbar ban c th chon New File hoc v
menu File v chon New.

Hnh 3.10 : Tao mi source file
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Mt file mi c tao ra vi tn mc inh l Untitled nh hnh di y.

Hnh 3.11 : File mi c tao ra

Ban nhn v menu File v chon Save As. lu lai file ny. Ca s di y hin ra v ban
chon ng dn lu cho chnh xc. Thng thng ta s lu trong th muc cha project hin
tai cho d qun l.

Hnh 3.12 : Lu file trong th muc cha project

Nhn Save lu file vi tn mi l main.c v ng ca s trn lai. Bc tip theo l add file
va mi lu (main.c) v th muc Source File ca project. Click chut phi vo Source File v
chon Add Files.
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Hnh 3.13 : Add file vo Source Files

Chon ng dn n file main.c v nhn Open.

Hnh 3.14 : Browse ng dn n main.c

File main.c s c add vo muc Source File ca project nh hnh bn di.
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Hnh 3.15 : Add xong main.c cho Source Files

Tip theo ta s add cc th vin cho project. u tin l Header Files. Cng tong tu nh khi
add file vo Source File, click chut phi v chon Add Files. Browse ng dn n C:\mcc18\h
v chon file p18f4520.h hoc g tn file ny vo muc File name ri nhn Open.

Hnh 3.16 : Add Header File

Add file vo muc Linker Script, browse ng dn n C:\mcc18\lkr v chon file 18f4520.lkr.
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Hnh 3.17 : Add file Linker Script

Add file lib vo muc Library Files, 18f4520.lib tai th muc C:\mcc18\lib

Hnh 3.18 : Add Library File
3.4 C/u h0'h cho 5u# t"0'h 36ch p"o.!ct
Khi dich project, compiler cn 1 s file object ca n (chng han nh c018i.o), ta cn phi ch
ng dn tm kim cc file object ny cho compiler. i vi 1 s phin bn MPLAB, n tu
ng tm ng cc file ny. Tuy nhin i vi phin bn 8.36 ta cn phi ch inh ng dn
tm kim. T menu Project, chon Build Option v chon Project.
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Giao din Build Option hin ra, tai muc Show Directories for ban chon Include Search Path,
chon New v Browse ng dn n C:\mcc18\h.
Sau chnh sang Library Search Path v tao mi 1 ng dn C:\mcc18\lib

Hnh 3.19 : Tao ng dn cho include file

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Hnh 3.20 : Tao ng dn cho Library File

Nhn OK hon tt vic cu hnh ca qu trnh dich.
3.7 8i9t co3! cho p"o.!ct
Double Click vo file main.c v bt u vit code cho project. Ta vit 1 oan code nh lm
cho cc led ni vi PORTB ca vi iu khin sng xen k (PORTB 0xAA)
Code:
#include <p18f4520.h>
void main()
{
TRISB = 0x00;
PORTB = 0xAA;
while(1);
}
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Hnh 3.21 : Double Click v main.c v vit code

kim tra code vit c li hay khng ban vo menu Project v chon Build All hoc nhn t
hp phm nng Ctrl F10. Nu khng c li thng bo BUILD SUCCEEDED s xut hin.

Hnh 3.22 : Bin dich thnh cng
3.6 :9t ';i )i $o2"3
Sau khi bin dich thnh cng, ban kt ni my tnh vi board nap v chay th chong trnh.
Vi mach BKIT PIC ban cm dy USB vo chn mach nap, bt cng tt ngun v gat tt c cc
switch ca SW2 ln ON kt ni mach nap PICKit2.
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Hnh 3.23 : Kt ni vi PICKit2 trn BKIT PIC

Gat tt c cc switch ca SW1 ln ON enable nt Reset, Led PortB v chn thach anh
ngoi.

Hnh 3.24 : Enable Reset, Led v XTAL ngoi
3.< C/u h0'h m-ch '-p
T menu Programmer chon Select Programmer v chon mach nap tong ng l PICKit2. Mun
chon mach nap khc hoc kt ni vi mach nap li ban phi chon lai None ri sau mi chon
lai mach nap.

Hnh 3.25 : Chon mach nap

thun tin cho qu trnh lp trnh, ta nn thit lp thm 1 s thng s cho mach nap c
th tu ng nap v chay chong trnh khi bin dich khng c li. lm c iu ny ta s
chon Programmer v chon Settings.
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Hnh 3.26 : Setting cho mach nap

Giao din sau hin ra v ban check chon Program after successful build (Nap chong trnh khi
bin dich thnh cng) v Run after a successful program (Chay chong trnh khi nap thnh
cng). Nhn OK kt thc.

Hnh 3.27 : Cu hnh nap v chay chong trnh

By gi ban nhn lai t hp phm Ctrl F10 (Build All), MPLAB s lm 1 loat cc thao tc nu
khng c li : Dich chong trnh Nap chong trnh Ko chn VDD ln mc cao th chn
Reset v chong trnh bt u chay trn board.
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Hnh 3.28 : Dich - Nap - Chay chong trnh

Hnh nh chong trnh chay trn board BKIT PIC nh sau :

Hnh 3.29 : Chong trnh chay trn BKIT PIC

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Bi 4 : :h=o *#t c#c ch9 > 32o >'?

1.1 Gii thiu
Dng PIC18F c 10 ch dao ng khc nhau, k hiu v tn goi ca chng nh sau:
1. LP : Low Power Crystal , thach anh c tn s dao ng thp (khong vi chuc kHz).
2. XT : Crystal/ Resonator, thach anh/resonator c tn s trung bnh (di 4MHz).
3. HS : High Speed Crystal/Resonator, thach anh/resonator c tn s cao (trn 4Mhz).
4. HSPLL : High Speed Crystal/Resonator with Phase Locked Loop enabled, thach anh tn
s cao vi b khuyt ai PLL.
5. RC : External Resistor/Capacitor with Fosc/4 output on RA6, dao ng RC ngoi,output
vi tn s chia 4 chn RA6.
6. RCIO : External Resistor/Capacitor with I/O on RA6, chn RA6 l I/O.
7. INTIO1 : Internal Oscillator with Fosc/4 output on RA6 and I/O on RA7, dao ng ni,
output chn RA6, input/output chn RA7 vi tn s Fosc/4 .
8. INTIO2 : Internal Oscillator with I/O on RA6 and RA7, dao ng ni vi RA6, RA7 l
I/O.
9. EC : External Clock with Fosc/4 output, clock ngoi, RA6 l output tn s Fosc/4.
10. ECIO : External Clock with I/O on RA6, clock ngoi, RA6 l chn I/O.
1.2 C"@*t2 ) A!*o'2to"
y l loai dao ng on gin nht. Resonator cn c tn goi khc l Ceramic Resonator. Hnh
nh ca Crystal v Resonator nh hnh bn di. Cc loai dao ng LP, XT, HS, HSPLL s dng
Crystal hoc Resonator.

ch hoat ng ny, Crystal/Resonator s c kt ni vi 2 chn OSC1 v OSC2 ca vi
iu khin nh hnh di y.

Khi dng Crystal, gi tri ca tu in phu thuc vo tn s ca Crystal nh bng di y

Bng 2 1 : Gi tri Capacitor cho Crystal

Gi tri ca tu in cng cao th dao ng cng n inh, nhng b lai thi giai khi ng s lu
hon.
Khi dng Resonator, gi tri ca tu in nh sau:
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Bng 2 2 : Gi tri Capacitor cho Resonator

Khi tn s resonator ln hon 3.5 MHz ta nn cu hnh l HS thay v XT.
1.3 EBt!"'2 CocC
Ngun dao ng clock ngoi c ni vo chn OSC1. c im ca loai dao ng ny l vi
iu khin hoat ng ngay khi c ngun cp (hoc thc dy t ch sleep) m khng cn
tn thi gian khi ng (start-up time). i vi chip PIC18F th dao ng ny c 2 loai :
EC : chn RA6 output vi tn s Fosc/4 (Fosc l tn s clock a vo chn OSC1). Chn
output ny c th dng kim tra hoc lm chn clock cho 1 s ng dung (nh 1 tn
hiu ng b). Trong ca s Configuration Bits, tn goi ca ch ny l EC-CLKOUT
on RA6.

ECIO : chn RA6 truy xut nh 1 I/O bnh thng. Trong ca s Configuration Bits, tn
goi ca ch ny l EC-Port on RA6.

1.4 D2o >'? AC
i vi 1 vi ng dung khng i hi chnh xc v inh thi cao th dao ng RC l 1 lua
chon tit kim. Do tn s dao ng tai chn OSC1 phu thuc vo in p cp, in tr, tu
in, nhit v thm ch l hng sn xut chip, nn tn s dao ng RC khng c chnh
xc. Ch ny cng c 2 loai l RC (RC-CLKOUT on RA6, Port on RA7) : Clock out vi tn s
chia 4 chn RA6 v RCIO (RC-Port on RA6, Port on RA7) : RA6, RA7 s dung nh I/O.
1.7 B> Chu9ch -i tD' *; PLL
PLL l 1 mach tch hp bn trong chip, c tc dung nng tn s input ln nhiu ln, nng cao
tc thuc thi chong trnh ca vi iu khin. B PLL c th c dng kt hp vi nhiu ch
hoat ng thach anh ca vi iu khin PIC.
HSPLL : PLL khi dng vi ch HS c th nhn gp 4 ln tn s input. Khi tn s
input ti a l 10Mhz, tn s khuch ai at 40MHz. Trong ca s Configuration Bits tn
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goi ca ch ny l HS-PLL enabled freq 4xFosc1. Trong ch ny bit PLLEN
khng c tc dung.
PLL v INTOSC : PLL cng c th c dng kt hp vi b dao ng ni, khi tn s
khuch ai c th at 32Mhz. Ch ny phi c thit lp bng phn mm, khng c
option chon lua trong ca s Configuration Bits. PLLEN bit dng kch hoat ch
ny.
1.6 B> 32o >'? '>i
Gn tong tu vi b dao ng External Clock, b dao ng ni (Internal Oscillator Block) cng
c 2 ch , output tn s Fosc/4 chn RA6 v ch I/O chn ny. Tn s ca b dao
ng ni c lp trnh software. Cc thanh ghi nh hng n tn s ny l OSCCON v
OSCTUNE.
b dao ng ni c 2 ngun clock, ngun clock 8MHz v ngun clock RC 31kHz. B ngun
clock 8MHz s i qua 1 b chia (Prescaller) v cp clock cho thit bi hoat ng. Gi tri ca b
chia ny c xc inh bi 3 bit IRCF2:IRCF0 trong thanh ghi OSCCON.

Khi gi tri cc bit u l 0 th vic chon clock source dua vo bit INTRC trong thanh ghi
OSCTUN. Nu INTRC 0 th tn s ly t clock source th 2, 31kHz. Ngc lai tn s s l
8MHz/256 31.5kHz (b chia l 256 cho clock 8MHz).

Khi tn s ca b dao ng ni l 4MHz hoc 8MHz (OSCCON6:4 110 hoc 111) th n c
th c s dung kt hp vi b PLL. kch hoat b PLL ta phi set bit PLLEN thanh ghi
OSCTUNE ln 1.

1.< D!mo
Kit BKIT PIC c thit k dng switch gat kt ni vi thach anh (crystal) 20MHz, nn ta c
th s dung ch thach anh ngoi khng PLL (PLL ch dng c vi thach anh nh hon
10MHz) hoc dng thach anh ni kt hp vi PLL.

demo tn s cung cp cho chip, ta s vit chong trnh c 1s tng gi tri ca PORTB ln 1
on vi.
Mt cu lnh trong PIC chim 4 chu k dao ng.

1.7.1 Thch anh ngoi 20MHz

Ta s dng 2 vng lp for tao hiu ng delay. Vi chu k 20MHz ta phi m 5 000 000 chu
k lnh (do 1 chu k lnh chim 4 chu k dao ng).

Khi mun tnh ton chnh xc thi gian, ta phi dng cc cu lnh ASM. Khi vit bng ngn
ng C, ta ch c th c lng gn ng. Cu lnh (for i0 I MAX_I i) tn khong 4
chu k lnh : i tn 2 chu k lnh, i MAX_I tn 2 chu k lnh, lnh gn i 0 ch thuc hin 1
ln nn ta c th b qua.

Vy hm tao hiu ng tr hon 1s vi tn s 20MHz ta s vit nh sau:
Code:
void delay1s_20MHz()
{
int i,j;
for(i=0;i<250;i++)
{
for(j=0;j<1250;j++)
{
}
}
}

Nh cp trn, 1 vng for thuc hin khong 4 chu k lnh nn tng s chu k lnh ca 2
vng for trn l (250 4) (1250 4) 5 000 000.
35

Hm main ta c th vit nh sau:
Code:
void main()
{
TRISB = 0x00; //setup PORTB is output
PORTB = 0x00; //init value
while(1)
{
PORTB++; //increase PORTB
Delay1s_20MHz(); //call delay 1s
}
}
Chnh ch thach anh trong ca s Configuration Bits l HS, PORTB l Digital (mc inh l
analog), Disable chc nng nap in p thp (LVP), dich v nap chong trnh ta s thy gi tri
PORTB tng dn sau 1s.
Chnh ch thach anh sang ch LP hoc XT, dich v nap lai chong trnh ban s thy
chong trnh khng chay hoc chay sai. Do vi thach anh 20MHz ta phi chon l HS nh
datasheet ca PIC18F4520.

1.7.2 Thch anh ni 8MHz

Cng tong tu nh trn, ch thach anh ni 8MHz ta phi thuc hin 2 000 000 chu k lnh.

Hm tao hiu ng tr hon 1s vi tn s 20MHz ta s vit nh sau:
Code:
void delay1s_8MHz()
{
int i,j;
for(i=0;i<250;i++)
{
for(j=0;j<1250;j++)
{
}
}
}
s dung c thach anh ni 8MHz, trc tin ta phi cu hnh l dng thach anh ni trong
ca s Configuration Bits (chon INT RC Port on RA6, Port on RA7), sau vit code trong
hm main lua chon b Prescaller cho ngun clock 8MHz. Ta s set 3 bit 6:4 ca thanh
ghi OSCCON ln 1. Hm main s vit nh sau:
Code:
void main()
{
OSCCON |= 0x70 //set bit <6:4> -> freq = 8MHz
while(1)
{
Delay1s_8MHz(); //call delay 1s
}
}

1.7.3 Thch anh ni 8MHz v PLL

Khi s dung thach anh ni 8MHz v b PLL nhn 4, tn s dao ng cp cho chip s l 32MHz,
vy ta phi m 8 000 000 chu k lnh. Hm tao hiu ng delay s nh sau:
Code:
36

void delay1s_8MHzPLL()
{
int i,j;
for(i=0;i<500;i++)
{
for(j=0;j<1000;j++)
{
}
}
}
Hm main ngoi vic chon Prescaller cho clock ni ta phi set thm bit PLLEN (bit 6) trong
thanh ghi OSCTUNE:
Code:
void main()
{
OSCCON |= 0x70 //set bit <6:4> -> freq = 8MHz
OSCTUNE |= 0x40 //enable PLL
while(1)
{
Delay1s_8MHzPLL(); //call delay 1s
}
}

37

Bi 7 : I't!""upt ) '?Et ,im!"

2.1 I't!""upt t"o'? PIC
Dng PIC18F4520 (2420, 2520, 4420) c nhiu ngun ngt (interrupt source) v 2 mc u
tin ngt (high priority interrupt v low priority interrupt). Vector ngt c mc u tin cao c
ia ch 0x08 cn ngt c mc u tin thp c ia ch 0x18. Khi hm phuc vu ngt qung cho
ngt u tin thp ang xy ra, ngt u tin cao xy ra s tam dng ngt u tin thp v phuc
vu cho ngt u tin cao.

i vi 1 ngt, thng thng c 3 bit iu khin n:
Flag bit : C bo hiu interrupt, khi flag bit c set, ngt s xy ra.
Enable bit : Cho php ngt i vi cc ngt c mt na (maskabled interrupt)
Priority bit : Thit lp u tin ngt, khi c set ngt s c mc u tin cao.
c th thit lp mc u tin cho cc ngun ngt, ta phi enable chc nng u tin ngt
bng cch set IPEN bit (Interrupt Priority Enable bit : RCON7).

Khi IPEN 1 : GIEH bit (INTCON7) s enable cc ngt c mc u tin cao, GIEL bit
(INTCON6) s enable cc ngt c mc u tin thp. Khi ngt ton cuc, Flag bit, Enable bit
c set, ngt s c kch hoat, con tr chong trnh s nhy ti ia ch 0x08 hoc 0x18 ty
theo ngt c thip lp l u tin cao (Priority bit l 1) hay u tin thp (Priority bit l 0).

Khi IPEN 0 : y l trng hp mc inh, disable chc nng u tin ngt (goi l ch
compatibility mode). INTCON6 lc ny l PEIE bit, enable hay disable cc ngt ngoai vi
(peripheral interrupt). INTCON7 lc ny l GIE bit, enable hay disable tt c cc ngun
ngt. ch compatibility ny, tt c cc ngt s nhy n ia ch 0x08.

Khi cc ngun ngt c cng u tin, chng s cng nhy n 1 ia ch ngt. Hm phuc vu
ngt qung cn phi kim tra tt c cc c xc inh ngun ngt no ang gy ra ngt. C
ngt cn c xa trnh hin tng ngt quy (recursive interrupt), vi iu khin s lp
v tn trong hm ngt cho n khi trn stack.

im ch quan trong trong thanh ghi INTCON l khi IPEN 1 : INTCON7 1 s enable
tt c cc ngt c u tin cao nhng khi INTCON7 0 n lai disable tt c cc ngt, bao
gm c ngt u tin thp. Mt ngt u tin thp ngoi vic thit lp GIEL (INTCON6) cn
phi set lun c bit GIEH (INTCON7).

2.2 Gii thiu ,im!"+
Timer0 c 2 ch 16 bit hoc 8 bit. Clock cp cho timer 0 c th l clock ni hoc clock ngoai
(ly t chn T0CKI). Ngoi ra Timer0 cn c b Prescaller chia tn s clock.

Hnh 2.1 : Thanh ghi iu khin T0CON

Timer0 c iu khin bi thanh ghi T0CON. ngha cc bit trong thanh ghi ny nh sau:
Bit < ,MA+FG : Bt tt Timer 0.
1 : Bt Timer 0 .
0 : Tt Timer 0.
Bit 6 ,+8BI, : Chon cu hnh cho Timer 0.
1 : Timer 16 bit.
0 : Timer 8 bit.
Khi hoat ng ch 16 bit, gi tri ca b inh thi (counter)/ b m Timer 0 c ghi vo
2 thanh ghi TMR0H v TMR0L. Ngc lai, ch 8 bit, gi tri m c lu trong thanh ghi
TMR0L.
Bit 7 ,+CH : Chon ngun clock cho Timer 0.
1 : Clock ngoi t chn T0CKI.
38

0 : Clock ni (Fosc/4).
Bit 4 ,+HE : Chon ch kch Timer 0 khi dng ngun ngoi.
1 : Timer 0 m ln khi c tn hiu t High sang Low chn T0CKI.
0 : Timer 0 m ln khi c tn hiu t Low sang High chn T0CKI.
Bit 3 PHA : Bt/ Tt ch Prescaller cho Timer 0.
1 : Tt Prescaller.
0 : Cho php Prescaller.
Bit 2 : + ,+PH2 :,+PH+ : Chon gi tri Prescaller.
111 : 1:256 011 : 1:16
110 : 1:128 010 : 1:8
101 : 1:64 001 : 1:4
100 : 1:32 000 : 1:2
Khi chon b Prescaller, tn s ca Timer 0 s bi chia xung. V du thach anh dng cho mach l
20MHz, th tn s ca clock ni l Fosc/4 5MHz. Nu ta chon Prescaller l 1:2 th tn s m
ca timer 0 l 2.5MHz.

Khi Timer 0 m trn t FF :FF (ch 16 bit) hoc FF (ch 8 bit) ln 0, c TMR0IF s c
bt ln 1 v gy ra ngt nu cc bit cho php ngt (ngt ton cuc, ngt timer0) c set ln 1.

2.3 L&p t"0'h mo3u! ,im!"+
2.3.1 H ini!"!i#$0
Trong phn ny, chng ta s khi tao timer0 ch 16 bit, s dung clock ni v prescaller
1:2, ngt timer0 s c cu hnh l ngt u tin thp v sau mi 1ms s xy ra ngt 1 ln.

Timer0 s m ln sau mi ln tch cuc ca clock. Trong ch 16 bit, khi gi tri trong 2 thanh
ghi TMR0H:TMR0L chuyn t FFFF sang 0000 s xy ra ngt, c TMR0IF s c bt ln 1.

Mach BKIT PIC s dung thach anh 20MHz, nn clock ni cho timer0 s l 5MHz (timer0 s m
5 000 000 on vi trong 1 giy). c c ngt 1ms ta s nap cho thanh ghi TMR0H:TMR0L
gi tri thp hon FFFF 7+++ on vi.

V Timer0 c cu hnh s dung prescaller 1:2, nn con s ny s thp hon FFFF 27++ on vi
: 65535 2500 63035 I63B. Vic nap gi tri ny cho thanh ghi TMR0 s c thuc hin
trong hm phuc vu ngt qung timer0_isr.

enable ngt timer 0, ta cn set bit ngt ton cuc GIE, set bit ngt thp GIEL, set bit enable
timer 0 TMR0IE v c ngt timer 0 TMR0IF trong thanh ghi INTCON. Cu hnh u tin ngt
timer 0 l ngt thp bng cch clear bit TMR0IP trong thanh ghi INTCON2.

Hm ngt timer0 s c khi tao nh sau:
Code:
void init_timer0()
{
counter0 = 0;//counter for virtual timer
timer0_flag = 0;//flag for virtual timer
T0CON = 0x00;//timer0 16bit mode, internal
clock, Prescaller 1:2
RCONbits.IPEN = 1;//enable interrupt priority
INTCON2bits.TMR0IP = 0;//low interrupt priority
INTCONbits.GIE = 1;//enable global interrupt
INTCONbits.GIEL =1;//enable low priority interrupt
INTCONbits.TMR0IE = 1;//enable timer0 interrupt
INTCONbits.TMR0IF = 1;//force timer0 interrupt

}
2.3.2 H !i#$0"i%$
Hm ny c goi khi ngt Timer0 xy ra. i vi tt c cc ngt ca PIC, ta cn phi xa c
ngt trc tin v n khng c tu ng xa bng phn cng. Trong hm phuc vu ngt qung
Timer0 ny ta nn tt n i bng cch xa bit TMR0ON, nap lai gi tri cho 2 thanh ghi m
39

Timer0. cui hm phuc vu ngt qung ta s bt cho Timer0 m ln (set bit TMR0ON). Gi
tri trong 2 thanh ghi m Timer0 s tng dn theo mi xung nhip ca clock, v khi at gi tri
FFFF n s xy ra ngt ln tip theo.
Code:
void timer0_isr()
{
INTCONbits.TMR0IF = 0; //clear interrupt flag
T0CONbits.TMR0ON = 0; //stop timer 0

TMR0H = 0xF6; //reconfig timer 0
TMR0L = 0x3B; //1ms interrupt

//CODE HERE
virtual_timer();
//END CODE
T0CONbits.TMR0ON = 1; //start timer 0
}
goi c hm ny, ta phi dng thm ch thi pragma dich 1 hm tai ia ch nht inh v
ch thi pragma interrupt dich hm ny l dang hm interrupt. Timer0 c cu hnh l
ngt u tin mc thp (low priority interrupt), nn khi ngt xy ra, con tr chong trnh s
nhy ti ia ch 0x18. Chong trnh hin thuc lnh goi hm timer0_isr c hin thuc cui
file main.c
Code:
#pragma code
#pragma interrupt low_interrupt_isr
void low_interrupt_isr()
{
if(INTCONbits.TMR0IF == 1)
timer0_isr();
}
#pragma code _vector_low = 0x18
void _vector_low(void)
{
low_interrupt_isr();
}
#pragma code
void main()
{
while(1)
{
}
}
Vi ch thi u tin, hm vecter_low s c dich tai ia ch 0x18, l ia ch vector ngt thp.
Do 2 ia ch ngt ca PIC l 0x08 cho ngt cao v 0x18 cho ngt thp cch gn nhau, nn ta
s ch t tht t lnh tai 2 ia ch ny. Trn y ch t 1 lnh goi hm low_interrupt_isr tai
ia ch 0x18. Trong hm ny ta s kim tra ngt ang xy ra c phi l Timer0 hay khng
bng cch xt bit th 2 ca thanh ghi INTCON (bit TMR0IF) trc khi goi hm timer0_isr. Hm
main() by gi phi thm ch thi #pragma code compiler dich hm ny 1 vng nh khc
trong vng code memory.

Ngoi Timer0, PIC cn c thm 3 Timer na. V cc chc nng co bn nh Timer0, chng cn
c thm 1 vi chc nng c bit khc.

2.4 Gii thiu ,im!" 1
Khc vi Timer0 l 1 interrupt, Timer1 l 1 Peripheral Interrupt. V vy c th enable cho
ngt Timer1, ta phi set bit PEIE.
40

Tong tu vi Timer0, Timer1 cng c chc nng counter t clock ngoi ( chn T13CKI) v
tng gi tri ln 1 mi khi c clock canh ln chn T13CKI.

Khi chon clock ngoi, T1SNC bit dng chon ch cho counter, l Ansynchronous Counter
hoc Synchronous Counter. Hai loai counter ny u tng gi tri m ln 1 sau mi ln tch
cuc ca clock, im khc bit ca chng nm kt ni phn cng. Synchronous Counter cp
clock cho tt c cc flip flop trong khi Ansynchronous Counter ch cp clock cho flip flop u
tin.

Hnh 2.2: Synchronous Counter

Hnh 2.3 : Ansynchronous Counter

Bn canh , Timer1 cn c th m ln nh dao ng ngoi 2 chn T1OSI v T1OSO. Ngi
ta thng dng thach anh 32,768kHz v bin Timer1 thnh 1 b Real Time Clock (ng h thi
gian thuc) . So kt ni nh sau:
41

Hnh 2.4 : Timer1 Osillator

s dung c chc nng ny ta cn phi set bit T1OSCEN.

Chc nng c bit cui, Timer1 l ngn clock cho module CCP. Chi tit v module ny s c
trnh by Bi 16. Hai timer cn lai thng c dng tch hp vi cc module khc, Timer2
(c thm b Post Scaller) s c dng cho module PWM Bi 14 v Timer3 s c dng cho
module Capture Bi 16.
2.7. G?Et ,im!"1 ) ,im!"2
Ti#$ 1&
Khi khng c interrupt priority : GIE enable all interrupts, PEIE/GIEL enable all peripheral
interrupt.

Khi c interrupt priority : GIE enable all high interrupt, nhng nu bng 0 s disable all
interrupts. Nn nu set timer 1 l interrupt mc thp th phi set GIEH ln enable, sau
set tip GIEL enable interrupt u tin thp. Nu timer1 mc cao th phi set GIEH enable
high interrupt v set PEIE v timer1 l peripheral interrupt.
Ti#$ 2&
Timer 8 bit, gi tri trong thanh ghi TMR2 khi bng vi PR2 s set c TMR2IF v gy ra ngt.
Prescaller l b chia tn s input. (1,4,16)
PostScaller l b chia tn s output. (1-16)
Timer 2 l peripheral interrupt.
Code:
42

void init_timer2()
{
T2CON = 0x00;
//postscaller 1
T2CONbits.T2OUTPS0 = 1;
//prescaller 4
T2CONbits.T2CKPS0 = 1;

}
void init_timer2_interrupt()
{
//enable timer 2 interrupt
PIE1bits.TMR2IE = 1;
//enable interrupt priority
RCONbits.IPEN = 1;
//enable timer1 low priority interrupt
IPR1bits.TMR2IP = 0;

INTCONbits.GIEH = 1;
INTCONbits.GIEL = 1;
//force into interrupt
TMR2 = 0x00;
PR2 = 200;
PIR1bits.TMR2IF = 1;
}
#pragma code vector_high = 0x08
void _vector_high(void)
{
_asm
goto timer1_isr_high
_endasm
}
#pragma code vector_low = 0x18
void _vector_low(void)
{
_asm
btfsc PIR1, 0, 0
goto timer1_isr_low
btfsc PIR1, 1, 0
goto timer2_isr_low
_endasm
}
#pragma interrupt timer2_isr_low
void timer2_isr_low()
{
static int counter = 0;
counter++;
PIR1bits.TMR2IF = 0;

if(counter == 6250)
{
PORTB++;
counter = 0;
}
}

43

Bi 6 : M2 t"&' phJm

3.1 :h#i 'im
Ma trn phm l cch kt ni cc phm theo hng v ct. Cch kt ni nh vy s tit kim
c ti nguyn ca vi iu khin. V du di y l cch mc ma trn phm 4x4 :

Hnh 3.1 : Ma trn phm 4x4

Ta c 16 phm v 8 tn hiu iu khin. Nu mc 16 phm ny nh cc phm on, ta phi cn
n 16 tn hiu iu khin.
3.2 Gi=i mK m2 t"&' phJm
Ta xt 1 ma trn phm 2x2 nh hnh di y:

Hnh 3.2 : Ma trn 2x2

Khi phm A c nhn th in p tai C1 s bng R1. Nh vy nu ban u tai C1 v C2 l mc
cao, R1 l mc thp v R2 l mc cao, th khi phm A c nhn, in p tai C1 (ban u l
mc cao) s bi ko xung mc thp.
44

Hnh 3.3 : Phm A c nhn

Tong tu nu phm B c nhn th C2 s bi ko xung mc thp.
xc inh 2 phm C v D c c nhn hay khng, ta s nng in p tai R1 ln mc cao,
ko in p tai R2 ln mc cao (chuyn hng tch cuc).

Hnh 3.4 : Phm D c nhn

Nh vy, xc inh vi tr ca phm no c nhn, ta s duyt qua tt c cc hng v xt
cc phm hng . uy c tn hin DEACTIVE l mc 1 v tn hin ACTIVE l mc 0, tng
bc gii m ma trn phm nh sau:
Cho tn hiu cc ct l DEACTIVE
Ci t tn hin tai cc ct l INPUT
Cho tn hin cc hng l DEACTIVE
Ci t tn hiu cc hng l OUTPUT
Lp qua cc hng
o Cho tn hiu hng ang xt l ACTIVE.
o Xt cc ct trong hng ang cho ACTIVE, ct no c tn hiu ACTIVE l phm
tong ng c nhn.
Kt thc vng lp
3.3 8i9t ch%L'? t"0'h

45

Chong trnh dnh cho gii m ma trn gm 2 phn : phn u dng khi tao cc chn vi
iu khin, phn 2 l duyt qua cc hng v ct xc inh phm no c nhn. File
key_matrix.h inh ngha cc hng s v 2 hm dng trong ma trn phm:
Code:
#define TRIS_BUTTON TRISC
#define PORT_BUTTON PORTC
#define MAX_COL 4
#define MAX_ROW 4
extern char key_data[];
extern char key_code[];
void init_key_matrix();
void scan_key_matrix();
'#("co)# l 1 mng 16 phn t tong ng vi 16 phm, nu phm c nhn th phn t
tong ng c gi tri l 1.

'#(")a!a cng l 1 mng 16 phn t, ta c th dng lu thng tin cho phm vi tr th
nht, chng han nh data hin thi s 0 (0x3F) trn led 7 oan.
3.3.1 *h+i !o a !$,n -h.
Theo nh so kt ni ma trn phm hnh 4.1, ta s khi tao cc hng l output v cc ct
l input. uy inh DEACTIVE l mc 1 nn ta s gn gi tri ban u ca PORTC l 0xFF.
Code:
void init_key_matrix()
{
TRIS_BUTTON = 0x0F; //C3-C0:input C7-C4:output
PORT_BUTTON = 0xFF;
}
3.3.2 /01! a !$,n -h.
Nh cp gii thut trn, ta s ln lt duyt qua tt c cc hng bng cch xut tn
hiu ca hng l ACTIVE (mc 0) ri xt tng ct.
Code:
void scan_key_matrix()
{
int i,j;
//loop all rows
for(i=0;i<MAX_ROW;i++)
{
//pull down row i
PORT_BUTTON &= ~(1<<(7-i));
//loop all cols
for(j=0;j<MAX_COL;j++){
//reset key code
key_code[i*MAX_ROW+j] = 0;

//when col j is activated
if((PORT_BUTTON & (1<<j)) == 0){
//set key code
key_code[i*MAX_ROW+j] = 1;
}
}
//pull up row i
PORT_BUTTON |= (1<<(7-i));
}
}
3.3.3 H ain
file main.c, ta s include file key_matrix.h c th goi c cc hm ca n. Bin
key_code c extern file key_matrix.h nn ta cng c th truy xut file main.c.
Code:
46

#include "KEY_MATRIX\\key_matrix.h"
void main()
{
int i;
TRISB = 0x00; //init PORTB for output
PORTB = 0x00; //initial value
init_key_matrix();
while(1)
{
scan_key_matrix();
for(i=0;i<16;i++)
{
if(key_code[i] != 0)
{
PORTB = i;
break;
}
}
}
}
Code chi tit ca ma trn phm cc ban c th tham kho Bai7.

47

Bi < : Ch;'? "u'? cho m2 t"&' phJm

4.1 G?u@(' J ch;'? "u'?

Hnh 4.1 : Hin tng rung phm

Hnh trn minh hoa mc in p ca 1 phm nhn tch cuc mc 0, trang thi
bnh thng, in p vi iu khin nhn vo l 5V cn khi nhn l 0V. Tuy nhin, do rung
co hoc ca phm, tai thi im va nhn xung, in p s khng n inh trong 1 khong thi
gian, trc khi n inh mc 0V. Hiu tng ny goi l rung phm.
Mc d khong thi gian in p mc 0 trong giai oan rung phm l nh nhng cng
vi iu khin nhn c. V vy khi ta xt nu in p l 0 th goi hm func() th hm ny s
c goi rt nhiu ln, l iu m ta khng mong mun. khc phuc hin tng rung phm,
c 2 hng gii quyt : dng phn cng v phn mm.
V gii php phn cng : thay v mc on gin nh kit th nghim ny (xem lai so ), ta c
th dng thm tu in han ch vic thay i in p t ngt, so nguyn l nh sau:

Hnh 4.2 : Chng rung bng phn cng
48

so trn, khi khng nhn l mc 1, khi nhn l mc 0. Phm nhn trn tch cuc mc 0.
Mach trn cn goi l mach RC.
Nu nt nhn c 2 cuc (3 chn), ta c th chon gii php dng mach RS flip flop, y l mach
phn cng chng rung tt nht, so nguyn l nh sau:

Hnh 4.3 : Chng rung bng phn cng (tt)

V gii php phn mm : Ta s inh k oc tn hiu t nt nhn, cho n khi no chng trng
nhau n ln th mi x l. Hnh di y minh hoa trong trng hp 2 ln l 0 th mi xc nhn
l phm c nhn v mi x l tc vu m ta mong mun.

Hnh 4.4 : Chng rung bng phn mm

Khong thi gian gia 2 ln oc l khong 10ms, ta s hin thuc hm oc ny v goi n trong
timer. Gii thut on gin x l chng rung c th hin thuc nh sau:
Code:

previous_key = current_key;
current_key = Port_key;
If(previous_key == current_key)
effective_key = current_key;
Trong :
previous_key : bin lu gi tri phm trc .
current_key : bin lu gi tri phm hin tai.
Port_key : Port ca vi iu khin kt ni vi phm. y chng ta goi hm oc ma trn phm
tr v gi tri ca phm c nhn.
effective_key : gi tri phm hp l (gi tri trong giai oan n inh)
tng tnh chnh xc, ta c th dng nhiu bin previous_key lu lai cc gi tri v so snh
nhiu ln. oan code trn ch so snh trng nhau 2 ln.
4.2 :9t ';i phD' cM'?
49

So nguyn l ca phm trong kit ny nh sau :

Hnh 4.5 : So kt ni nt nhn

Phm nhn ny tnh cuc mc 0, c kt ni kh on gin, nn ta s dng phn mm chng
rung. Ta s dng 3 bin so snh 2 ln trng nhau, 2 ln lin tip cch nhau 10ms.

Trong trng hp nhn 1 phm, ta s dng bin TimeOutForKeyPress xc inh thi gian
tch cuc tip theo. Bin ny s quan trong trong trng hp ta vit 1 ng dung chng han nh
soan tho vn bn. Nu khng c bin ny qun l, nu ta th trong 1s c ti 100 ln
tch cuc.
4.3 8i9t ch%L'? t"0'h
Module ny c 2 hm nh sau :

void initKey() : Khi ng cc thng s ban u
void getKey() : Hm ny c goi trong timer0, dng qut phm.
void SubKeyProcess() : Hm ny hin thuc tc vu ban cn thuc hin khi nhn phm.

kit th nghim ny, cc nt nhn c ni thnh dang ma trn v c ni vi PORTC nn ta
inh ngha thm u file Key.c :
Code:
#define KEY_PORT PORTC

4.3.1 H ini!'#(23

Code:
void initKey()
{
KeyReg0 = 0x00;
KeyReg1 = 0x00;
KeyReg2 = 0x00;
KeyReg3 = 0x00;
}
Trong KeyReg0, KeyReg1, KeyReg2 dng lu 3 ln lin tip. Khi 3 bin ny bng nhau,
bin KeyReg3 mi c cp nht. Bin KeyReg3 l gi tri hp l ca phm nhn.
4.3.2 H g#!*#(23
Hm ny c chia lm 2 phn, phn u l chng rung phm dng 2 ln so snh trng
nhau. Phn th 2 x l khi 1 phm c , phi sau 1 khong thi gian TimeOutForKeyPress
mi c tch cuc.
Code:
50

void getKey(){
KeyReg2 = KeyReg1;
KeyReg1 = KeyReg0;
KeyReg0 = read_matrix_key();// Cho phep nut nhan nao duoc tich cuc.
if ((KeyReg1 == KeyReg0) && (KeyReg1 == KeyReg2)) {
TimeOutForKeyPress --;
if (TimeOutForKeyPress == 0) {
KeyReg3 = 0x00;
}
if (KeyReg2 != KeyReg3) {
KeyReg3 = KeyReg2;
If (FlagFirstTimeKeyPress == 1)//Day la lan dau phim duoc
nhan.
{
TimeOutForKeyPress = 100;
SubKeyProcess();
FlagFirstTimeKeyPress = 0;
}
else
{
if (KeyReg2 == 0x00)
FlagFirstTimeKeyPress = 1;
else
{
TimeOutForKeyPress = 100;
SubKeyProcess();
}
}
}
}
}
4.4. Co3! mNu

Download code mu tai y

51

Bi 8 : LCD 16B2 ) $' phJm i' tho-i

7.1 ChMc 'O'? c#c chP' cQ2 LCD

Hnh 5.1 : LCD 16x2

LCD thng s dung 14 chn, ch 16 chn khi cn iu khin n nn. Chc nng ca cc
chn nh sau:

52

7.2 :9t ';i m' h0'h LCD

Hnh 5.2 : Kt ni mn hnh LCD

Hnh trn m t kt ni LCD vi ch 16 chn, 2 chn K v A dng kt ni vi n nn.

7.3 C#c )R'? 'h cQ2 LCD
5.3.1 4i%-5a( 4a!a 6a 24467M3
Lu tr m k tu hin thi ra mn hnh. M ny ging vi m ASCII. C tt c 80 nh DDRAM.
Vng hin thi tong ng vi ca s gm 16 nh hng u tin v 16 nh hng th hai.
Chng ta c th tao hiu ng dich ch bng cch s dung lnh dich , khi ca s hin thi s
dich em lai hiu ng dich ch.

Hnh 5.3 : Vng nh DDRAM
5.3.2 8ha$ac!#$ 9#n#$a!o$ 6a 28967M3
Lu tr tm mu k tu do ngi dng inh ngha. Tm mu k tu ny tong ng vi cc m k
tu D7-D0 0000D2D1D0 ( mang gi tri ty inh 0 hay 1).
53

Hnh 5.4 : Vng nh CGRAM
5.3.3 B nh 896:M
B nh dng lu tr cc k tu hin thi trn LCD. Cc gi tri lu trong b nh ny nh sau:
54

Hnh 5.5 : Vng nh CGROM
Chng ta mun hin thi ch CE gia hng u tin, gi s ca s hin thi ang bt u t
vi tr u tin (hng th nht hin thi d liu ca nh t 0x00 n 0x0f, hng th hai hin
thi d liu ca nh t 0x40 n 0x4f, y l vi tr home). Gi tri ca nh 0x07 l 0x43 (k
tu C), ca nh 0x08 l 0x45 (k tu E).

Chng ta mun hin thi ch gi hng th hai, gi s c s hin thi ang vi tr home.
Trong bng mu k tu chng ta thy khng c mu . Lc ny chng ta phi inh ngha
mu 5x8 im, gm c 8 byte, sau lu vo vi tr ca mu k tu CGRAM th nht. Lc
ny gi tri ca nh 0x47 l 0x00 hoc 0x08 (vi tr ca mu k tu CGRAM th nht ).

7.4 C#c 'h cL $=' cQ2 LCD
truyn lnh cho LCD th chn RS 0, khi cc tn hin trn D0-D7 c xem l lnh.
ngha ca cc lnh iu khin LCD nh sau:
55

I/D
1 = Increment (by 1)
0 = Decrement (by 1)
RL
1 = Shift right
0 = Shift left
S
1 = Display shift on
0 = Display shift off
DL
1 = 8-bit interface
0 = 4-bit interface
D
1 = Display on
0 = Display off
N
1 = Display in two lines
0 = Display in one line
U
1 = Cursor on
0 = Cursor off
56

F
1 = Character format 5x10 dots
0 = Character format 5x7 dots
B
1 = Cursor blink on
0 = Cursor blink off
D/C

1 = Display shift
0 = Cursor shift

7.7 :9t ';i LCD )i )i iSu ChiT'
LCD c 2 ch 8 bit v 4 bit. ch 8 bit, ta dng ton b 8 chn D0-D7 giao tip.
ch 4 bit, ta ch dng 4 bit cao D4-D7 giao tip vi LCD. D liu gi cho LCD ch
ny bao gm 4bit cao gi trc, sau s n 4bit thp. So kt ni 2 ch nh sau:

Hnh 5.6 : Kt ni LCD vi vi iu khin

Nu mun tit kim chn, R/W c th ni xung GND. ch 4bit th 4 bit thp ca LCD c
th ni xung GND.
7.6 :hUi t-o LCD
u trnh khi tao LCD ch 8 bit nh sau:
57

Hnh 5.7 : Khi tao LCD 8 bit

u trnh khi tao ch 4 bit nh sau:
58

Hnh 5.8 : Khi tao LCD 4 bit
7.< :9t ';i phD' cM'?
LCD c kt ni vi Port B ca vi iu khin PIC nh sau:
Trch:
LED_BACKLIGHT PortB.0
PIN_RS : PortB.1
PIN_RW : PortB.2
PIN_EN : PortB.3
D4 : PortB.4
59

D5 : PortB.5
D6 : PortB.6
D7 : PortB.7
7.8 8i9t ch%L'? t"0'h V 7.W C#c hm cL $='
qu trnh iu khin LCD hiu qu, ta inh ngha 1 s hm co bn nh sau:
Hm delay: trung bnh PIC thuc hin 5 lnh mt 1us vi thach anh 20Mhz.
Code:
void lcd_delay(int time)
{
while(--time);
}
Hm ghi d liu ra LCD:
Code:
//Ghi 4 bit
void lcd_write_4bits(unsigned char dat)
{
RW(WRITE); //ko chn RW xung 0
EN(SET); //set chn Enable ln 1
LCD_DATA_OUT(dat & 0xF0); //Gi data ra
lcd_delay(10);
EN(CLR); //ko chn Enable xung 0
lcd_delay(10);
}
//Ghi 1 byte : ghi 4 bit 2 ln
void lcd_write_cmd(unsigned char cmd){
lcd_wait_busy();

RS(CMD);
lcd_write_4bits(cmd);
lcd_write_4bits(cmd << 4);
}
Mt s macro trong file lcd.h, v du nh:
Code:
#define RS(x) ( (x) ? ( LCD_PORT |= 0x02 ) : ( LCD_PORT &= 0xFD ) )
//Nu x = 1 th thc hin lnh LCD_PORT |=0x02, x=0 th thc hin
LCD_PORT &=0xFD
.
7.1+ :hUi t-o LCD ch9 > 4 $it
Code:
60

void init_lcd() {
lcd_delay(15000); //1
RS(CMD); //2
lcd_write_4bits(0x03 << 4); //3
lcd_delay(4100); //4
lcd_delay(100); //6
lcd_write_cmd(0x28) ; //9
lcd_write_cmd(0x0C); //10
lcd_write_cmd(0x06); //11
}
ngha cc lnh trn nh sau:
Lnh 1 : goi hm lcd_delay(15000) delay 15ms.
Lnh 2 : ko chn RS (ni vi LCD_PORT tai bit 1) xung 0. Lnh ny c inh ngha
l 1 macro trong file lcd.h:
#define RS(x) ( (x) ? ( LCD_PORT |= 0x02 ) : ( LCD_PORT &= 0xFD ) )
CMD c define l 0 nn lnh RS(CMD) s c iu kin (x) l false v s thuc hin
phn th 2 ca lnh trn : LCD_PORT 0xFD (ko bit 1 xung 0 : 1111 1101).
Lnh 3 : thuc hin trang thi u tin sau khi ch 15ms, ghi D7 D6 D5 D4 0011. Cc
chn ny c ni vi 4 bit cao ca vi iu khin nn ta phi dich tri gi tri 0x03 4 bit.
Lnh 4 : delay khong 41ms.
Lnh 5,6,7,8 : Thuc hin cc trang thi 2,3 v 4. Sau lnh 7 th LCD chuyn sang
ch 4 bit, v gi 1 byte, ta s gi 2 ln 4 bit cao trc ri ti 4 bit thp.
Lnh 9 : goi hm lcd_write_cmd ghi 4 bit 2 ln, gi tri 0x28 tong ng vi N 1
(hin thi trn 2 hng ca LCD) v B 0 (font inh dang 5x7 im).
Lnh 10 : thuc hin lnh display on (xem thm trong bng lnh), D 1.
Lnh 11 : thuc hin lnh entry set mode, 0x06 tong ng vi ch dich phi tng
dn.
7.11 Xo# m' h0'h
Hm ny ch on gin l gi lnh clear mn hnh lcd (xem thm trong bng lnh ca LCD).
Code:
void lcd_clear()
{
lcd_write_cmd(0x01);
lcd_goto_xy(0, 0);
}

7.12 ,hi9t &p )6 t"J co' t"Y
Hm ny thit lp vi tr bt u xut d liu trn mn hnh LCD 2 hng 16 ct. hin thuc
hm ny ta phi tnh c ia ch tong ng vi toa (row,col) v dng lnh SET DDRAM
ADDRESS (bit 7 ca lnh ny bng 1).
Code:
61

char lcd_goto_xy(unsigned char row, unsigned char col) {
unsigned char addr = 0x00;
if(col >= 20 || row >= 4)
return FALSE;
if(row < 2) {
addr = (row * 0x40) + col;
addr = 0x80 | (addr & 0x7F);
}
else {
addr = (row * 0x40) + col;
addr = 0x94 | (addr & 0x7F);
}
lcd_write_cmd(addr);
current_row = row;
current_col = col;
return TRUE;
}

7.13 I' CJ tZ "2 m' h0'h
Hm ny nhn thng s l 1 k tu v hin thi k tu ra mn hnh LCD. Vic hin thuc hm
ny kh on gin, ta ch cn ko chn RS xung 0 l LCD s hiu cc bit D7-D4 l d liu.
Code:
void lcd_print_char(unsigned char dat)
{
lcd_wait_busy();
//find next position
if(current_row == 0 && current_col == 16)
lcd_goto_xy(1,0);

if(current_row == 1 && current_col ==16)
lcd_goto_xy(0,0);
RS(DAT); //RS = 0
lcd_write_4bits(dat);
lcd_write_4bits(dat << 4);
current_col ++; //update new position
}
T nhng hm co bn ny, ban c th hin thuc thm cc hm xut 1 string hay 1 gi tri s
ra mn hnh LCD. Code chi tit c th xem thm file nh km.

7.14 ,hi9t &p $' phJm i' tho-i
Tm tt : bn phm 4x4 c nh cc k tu s (0-9) v ch (A,B,C,D,,) s l cc phm chc
nng m phng theo bn phm in thoai. Cc trang thi cng nh thng tin s c hin thi
trn mn hnh LCD. lm c bi ny cc ban cn c nhng hm v qut ma trn phm
(trong th muc button_matrix) cng nh xut ra LCD (trong th muc lcd).

Trc ht ban cn phi bit qua bi qut ma trn phm. Trong Button.c chng ta c hm
button_process(void) Hm ny c goi inh k trong timer kim tra xem c nt no c
nhn khng.Hm read_matrix_key(void) khi khng c nt no c nhn, n s tr v gi tri
0. Khi c nt nhn n s tr v gi tri t 1-16 ty theo vi tr ca nt nhn. Vic kim tra ny
c thuc hin nhiu ln v chng ta s ch x l n khi c t nht 3 ln oc gi tri ging nhau
(theo nguyn l chng rung, oc thm bi chng rung cho phm).

Bi th 2 cn bit l bi v xut lcd. Trong lcd.c h tr cho ban sn cc hm ghi ln lcd
(Tham kho thm trong lcd.h).

Chng ta bt u bng vic tao mt project mi vi nhng thit lp ph hp. copy th muc
button_matrix, lcd, timer, interrupt vo noi cha chong trnh hon chnh project mi.
Thm nhng file .h trong cc th muc ny vo main.c. Tao th muc Phone v cha cc file
phone.c, phone.h . add vo project. Cc su kin v trang thi ca chic in thoai ca chng
ta s c x l chnh trong file phone.c ny. Include file .h ca button_matrix v lcd.
62

inh hnh: trc ht chng ta inh hnh lai vi tr v chc nng ca tng nt. V thuc hin
c chc nng nhn tin cng nh goi in nn mi nt t 0-9 c thm cc chc nng
ring. Ta khai bo mt mng lu gi nhng gi tri m ta mun nt nhn c th thuc hin.
Code:
unsigned char key[16][5] = {
'0',' ',0,0,0,
'1','.',',',0,0,
'2','a','b','c',0,
'3','d','e','f',0,
'4','g','h','i',0,
'5','j','k','l',0,
'6','m','n','o',0,
'7','p','q','r','s',
'8','t','u','v',0,
'9','w','x','y','z',
'*',0,0,0,0,
'#',0,0,0,0,
'A',0,0,0,0,
'B',0,0,0,0,
'C',0,0,0,0,
'D',0,0,0,0};
y c cc nt c nhiu k tu (7-p-q-r-s) cng c nt c t k tu (1-.) nn thun tin ta
tao thm mt mng cha gi tri l s k tu c s dung ca nt :
Code:
unsigned char limit_key[16]={2,3,4,4,4,4,4,5,4,5,1,1,1,1,1,1};
By gi coi lai trong button.c c hm qut ma trn phm. Tuy nhin, gi tri tr v ca hm ny
l vi tr ca cc nt trn bn phm (vd:11,22,33,A4.). Ta s cn phi chuyn i sang
mt h khc thun tin trong vic lp trnh thng qua mt mng sau:
Code:
unsigned char convert_key[16]={1,2,3,12,4,5,6,13,7,8,9,14,10,0,11,15};

Chong trnh chnh ca chng ta l hm Phone() c goi lin tuc trong hm main(). Hm
ny u tin s xt bin ActiveKey xem c nt nhn no c nhn khng . Khi c nt nhn
th s c mt chuyn i nh
Code:
KeyPress = convert_key[ActiveKey-1];
V bin KeyPress ny chnh l gi tri chng ta x l chnh.

Bin PhoneStatus cha gi tri ca ca cc trang thi ca in thoai. Cc trang thi chnh l
i (WAIT_STATUS), goi in (ENTERING_NUMBER_STATUS, CALLING_STATUS,ENDCALL_STATUS),
nhn tin (MESS_STATUS, TYPING_MESS_STATUS, SENDING_STATUS, ENDSEND_STATUS). Vi mi
trang thi ta x l nt C l quay lai, D l xa k tu, A l enter. ty theo quy inh mi ngi.

Tip theo chng ta x l nt nhn tai mi trang thi. Tai trang thi i, nu nhp vo l s th
s ch hin s keyKeyPress0. Cn nu trong ch nhn tin th nu nh phm c nhn
lp lai trong khong thi gian timeout th coi nh s chuyn k tu ngay tai nt :
Code:
KeyMessIndex = (KeyMessIndex +1)%(limit_key[KeyPress]);
lcd_putChar(key[KeyPress][KeyMessIndex]);
, nu khng th in k tu mi.:
Code:
KeyMessIndex = 1;
lcd_putChar(key[KeyPress][KeyMessIndex]);
Do['o23 co3! mNu
Tai y

63

Bi W : \u]t !3 < o-' ) !3 m2 t"&'

6.1 îSu ChiT' !3 < o-' ) !3 m2 t"&'.
6.1.1 8;0 !o L#) 7 <on
LED 7 oan gm c 7 oan c nh du: a, b, c, d, e, f, g v mt im dp. Mi oan l mt
led, kt hp tt/sng ca cc led ny hin thi s m chng ta hiu c.

Hnh 6 1 Led 7 oan
LED 7 oan c hai loai l Common Anode v Common Cathode, tong ng cc LED ni chung
Anode hay ni chung Cathode. Mach th nghim BKIT PIC s dung loai Common Anode.

Hnh 6.1 : So nguyn l led 7 oan
6.1.2 8;0 !o 5#) a !$,n
LED ma trn 8x8 hai mu c b tr thnh 8 hng v 8 ct.

Hnh 6 3. Led ma trn
Mi im c hai LED tong ng vi hai mu. Cc LED trn cng mt hng ni chung Anode,
cc LED cng mu trn cng mt ct ni chung Cathode.
64

Hnh 6 4 So nguyn l led ma trn
6.1.3 =g0(>n 5? @01! LA4
hin thi 1 led 7 oan, ta cn 8 ng tn hiu gi d liu cho n. Nh vy, vi 8 led 7
oan, theo kt ni bnh thng, ta cn tng cng 64 ng tn hiu thp sng 8 led cng
lc. Vic ny rt tn ti nguyn v phn cng. khc phuc, ngi ta dng k thut qut led.
Cc ng d liu ca cc led s c ni vi nhau.

Hnh 6 5 Kt ni khi qut led 7 oan
Vi k thut qut led ny, tai 1 thi im, ch c 1 led sng. Tai thi im t1 ch c led 1 sng,
tai thi im t2 t1 t0 ch c led 2 sng, khi t0 rt nh, mt ngi khng th nhn bit
c nhp nhy gia 2 ln lun chuyn, v s c cm gic l 2 n sng cng lc. Thng
th t0 ny phi nh hon 1/24 giy, tc l trong mt giy s c nhiu hon 24 ln lun chuyn
gia cc led.

Bng m t qu trnh qut Led 7 oan:
65

Tong tu i vi led ma trn, ta dng 16 ng tn hiu iu khin hai mu led v 8 ng
tn hiu tch cuc dng (ROW). Tai mi thi im ch c mt dng led ma trn c hin thi
d liu.

Hnh 6 6 Nguyn l qut led ma trn
6.2 HL _ C9t ';i m-ch

66

Hnh 6-7 So kt ni led 7 oan v led ma trn
Muc ch ca bi ny l moi ngi lm quen vi led 7 oan v led ma trn cho nn cc led 7
oan v led ma trn c kt ni theo kiu song song, cc chn d liu v iu khin led c
gn truc tip vi chn vi iu khin PIC, v vy chong trnh s on gin v d thuc hin hon.

6.3 XP@ 3Z'? ch%L'? t"0'h
6.3.1 B !+ng hiCn !hDc
c th hin thuc gii thut qut led chng ta cn s dung ti b inh thi(timer) v ngt
qung thit lp thi gian qut. V du chng ta qut 1 led vi tn s 50Hz(ngha l led sng
50 ln/giy) nh vy ta cn cu hnh cho timer l c sau 1000ms/50 20ms th ngt 1 ln v
trong hm x l ngt ta s a d liu ra cho led. Nu s led nhiu hon th ta ch cn ly tn
s chun cho mi led nhn vi s lng led. V du nu qut cng luc 8 led 7 oan vi tn s
mi led l 50Hz th tn s ngt ca timer l 850 400Hz.
6.3.2 8Ec h -hFc vF @01! 5#)
2.6.3.1 Hm qut led 7 on
Code:
void display_led7(void)
{
PORTE = 0;
PORTD = led7_buffer[index_led7];
PORTE = 1 << index_led7;
index_led7 = (index_led7 + 1) % 3;
}
Theo so nguyn l PORTD l port a d liu ra led 7 oan v PORTE l port chon led( y
chng ta c 3 led 7 oan).Trc mi ln xut led, ta cn phi tt tt c cc led trnh trng
hp d liu c c a vo led c chon tip theo,hay ngc lai d liu mi c a vo
led trc .

2.6.3.2 Hm qut led ma trn
Code:
67

void display_ledmatrix(void)
{
PORTA = 0;
PORTB = green_buffer[index_matrix];
PORTC = red_buffer[index_matrix];
PORTA = 1 << index_matrix;
index_matrix = (index_matrix + 1) % 8;
}
Theo so nguyn l, PORTA l port lua chon led, PORTB v PORTC tong ng l cc d liu
xanh v ca led ma trn, cch qut vn ging vi vic qut led 7 oan.
i vi vic qut led ta nn tao ra nhng mng buffer tin cho vic xut d liu v cp
nhp chng, cng vi vic hin thuc 1 s hm cp nhp buffer nh update_led7_buffer(),
update_green_bugffer(), update_red_buffer() chong trnh ca chng ta tr nn thn thin,
trong sng, on gin hon rt nhiu v ph hp vi vic pht trin ln thnh nhng bi kh hon
nh chay ch hay cc hiu ng led river.

68

Bi 1+ : Gi2o ti9p ';i ti9p HPI

<.1 Gii thiu )S HPI
SPI (Serial Peripheral Interface) l mt dang giao thc truyn ni tip c dng giao tip
vi cc thit bi ngoai vi(EEPROM,SDcard.) v cc vi iu khin khc.
<.2 Ch9 > HPI t"o'? )i iSu ChiT' PIC
Giao tip SPI c hin thuc qua 4 chn ca vi iu khin:
G4H( Serial Data In ): Tn hiu ni tip c a vo vi iu khin
G4:( Serial Data Out): Tn hiu ni tip t vi iu khin i ra
8L*(Clock): xung clock tao ra bi master
GG(Slave Select): tch cuc mc thp, dng chon slave truyn d liu

Hnh 7-1 So khi ca SPI

7.2.1 8Ec !hanh ghi <iI0 'hiJn GPH
Ch SPI c iu khin bng 4 thanh ghi sau

MSSP Control Register 1 (SSPCON1)
MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer Register(SSPBUF)
MSSP Shift Register(SSPSR) thanh ghi ny khng c truy xut bi ngi dng

69

Hai thanh ghi SSPCON1 v SSPSTAT l hai thanh ghi iu khin, cn than ghi SSPSR l thanh
ghi dng dich d liu ra/vo vi iu khin, SSPBUF l thanh ghi dng oc d liu t
ngoi vo hoc ghi d liu truyn ra ngoi. ch nhn, 2 thanh SSPBUF v SSPSR l 1
b buffer i, khi d liu t ngoi truyn vo c lu y trong SSPSR(8 bits) th d liu
ny c truyn ti thanh ghi SSPBUF ngi dng ly ra. Cn ch truyn th khi d
liu c ghi vo thanh ghi SSPBUF th cng lc d liu cng c ghi vo thanh ghi SSPSR
dich ra ngoi.

2.7.2.1 Thanh ghi GGPGT7T

Bit 7:
SMP Sample bit
SPI Master mode
1 d liu vo s c ly cui chu k xung clock
0 d liu vo s c ly gia chu k cung clock
SPI Slave mode
SMP phi c gn bng 0
Bit 6:
CKE SPI Clock Select bit
Bit 0:
BF BuFffer Full Status bit(dnh cho qu trnh nhn)
1 qu trnh nhn hon thnh, SSPBUF y
0 qu trnh nhn ang thuc hin, SSPBUF trng

2.7.2.1 Thanh ghi GGP8:=1

Bit 7:
WCOL Write Collision Detect bit(ch dng ch truyn tn hiu)
1 thanh ghi SSPBUF c ghi d liu trong khi d liu c truyn cha ht
0 khng c ung
Bit 6:
SSPOV Receive Overflow Indicator bit(dng ch nhn tn hiu)
1 c d liu mi nhn v ghi ln thanh ghi SSPBUF trong khi d liu trc
cha c oc.
0 d liu khng bi ghi
Bit 5:
SSPEN Synchronous Serial Port Enable bit
1 bt ch SPI v cc chn SDI, SDO, SCK, SS c cu hnh tong ng.
0 tt ch SPI
Bit 4:
CKP Clock Polarity Select bit
1 thit lp trang thi rnh khi xung clock mc cao
0 thit lp trang thi rnh khi xung clock mc thp
Bit 3-0:
SSPM3:SSPM0 Synchronous Serial Port Mode Select bit
0101 ch slave, clock chn SCK, tt chc nng ca chn SS
0100 ch slave, clock chn SCK, bt chc nng ca chn SS
70

0011 ch master, clock tn s ca timer 2 /2
0010 ch master, clock Fosc / 64

7.2.2 8;0 hKnh GPH
cu hnh ch SPI cho vi iu khin PIC ta s dung cc
bit HHPCFG1`7:+a v HHPH,A,`<:6a, khi cu hnh cc bit ny SPI ca PIC s c cu
hnh ch master hoc slave, cung clock cho SPI, v thit lp vic nhn d liu xy ra
canh ln hoc xung ca xung clock. Thanh ghi HHPHA c chc nng dich d liu ra v vo vi
iu khin v lun l bit trong s cao trc. trong ch truyn, thanh ghi HHPBbI s ch
cho n khi thanh ghi HHPHA sn sng nhn d liu ri mi ghi d liu ln thanh ghi HHPHA,
nu c hnh ng ghi d liu vo thanh ghi HHPBbI trong lc d liu truyn cha xong th
hnh ng c b qua v bitcCFL c bt ln bo hiu c xy ra ung . trong ch
nhn, sau khi HHPHA nhn 8 bit d liu s c chuyn n thanh ghi HHPBbI v
bit BI c bt ln bo hiu, nu d liu trc c lu trong thanh ghi HHPBbI cha
c oc m lai c thm d liu mi th d liu mi s ghi ln d liu c v bitHHPF8 c
bt ln.

Hnh 7-2 Kt ni SPI master/slave

Hm cu hnh ch SPI master cho vi iu khin PIC
Code:
void init_spi_master(void)
{
SSPSTATbits.CKE = 1; // when CKP = 0,CKE = 0
transmit data on falling
clock,CKE = 1 transmit data
on rising clock
// when CKP = 1,CKE = 1
transmit data on rising
clock,CKE = 1 transmit data
on falling clock
SSPCON1bits.CKP = 1; // CKP=0 data first,second is
clock; CKP=1 clock
SSPCON1bits.SSPEN = 1; // enable SPI master
SSPCON1bits.SSPM0 = 0; //
SSPCON1bits.SSPM3 = 0; // preacaler 1:4
}

71

Bi 11 : îSu ChiT' !3 < o-' ) mP t"' $d'? HPI

8.1 :9t ';i phD' cM'?

Hnh 8-1 So kt ni led 7 v led ma trn

bi ny chng ta s s dung mach ri s1, mach bao gm 8 led 7 oan v 1 led ma trn
c s dung giao tip vi vi iu khin thng qua giao thc SPI. Trong mach ny vi iu
khin PIC ng vai tr l master v cc IC TPIC595, 74HC595 ng vai tr l slave vi chc
nng dich bit, ngoi chc nng dich bit IC TPIC595 cn c tc dung m v o tn hiu u
vo, IC ny c s dung ph hp vi nguyn l hoat ng ca led 7 oan v led ma trn.
Cch thc hoat ng ca mach l vi iu khin s dich d liu cn xut ra ngoi n cc con
IC dich, v khi no dich d liu cn xut ra ngoi vi iu khin s kha d liu lai bng cch
tao mt xung t thp ln cao trn chn LATCH ca cc IC dich ny, lc ny cc IC dich s ly
d liu c ct trong b m trong qu trnh dich d liu ca vi iu khin v xut ra ngoi.
8.2 XP@ 3Z'? ch%L'? t"0'h
Ngoi hm cu hnh ch SPI cho PIC nhu bi trn, chng ta cn hin thuc thm hm tao
tn hiu LATCH, hm qut led 7 oan v led ma trn, hm xa led 7 oan v led ma trn.
72

Ngoi ra chng ta cng cn b sung thm cc hm tin ch trong vic xut led 7 oan v led
ma trn, chi tit cc ban c th tham kho trong th vin source code.
8.2.1 H !o !.n hiC0 L7T8H
Code:
void latch_spi(void)
{
unsigned char j;
LATCH = 0;// create a rising clock to push data into output register
for (j = 0; j <10;j++);
LATCH = 1;
for (j = 0; j< 10; j++);
}
8.2.2 H L0;! 5#) 7 <on v 5#) a !$,n
Vi cng gii thut qut led nh bi trn ch khc l trong chong trnh ngt ca timer ta goi
hm xut truc tip d liu ra cc port ca vi iu khin th ra goi hm dich d liu t vi iu
khin ra cc IC ngoai vi.Chi tit hm dich nh sau:
Code:
void scan_led7_matrix(void)
{
SSPBUF = 0x00; // select column for led matrix
while (!SSPSTATbits.BF);
SSPBUF = 0x00; // green matrix's data
SSPBUF = 0x00; // red matrix's data
SSPBUF = column[index]; // select column for led 7 segment
SSPBUF = code[buffer[index]]; // led7's data
latch_spi();
index = (index+1) % 8;
}
8.2.3 H LMa )N 5iC0 !$>n 5#) 7 <on v 5#) a !$,n
Code:
void clear_spi(void)
{
unsigned char i;
for (i =0; i< 5; i++)
{
SSPBUF = 0xff;
}
latch_spi();
}

73

Bi 12 : \u]t 2 !3 m2 t"&' $d'? HPI

W.1 :9t ';i phD' cM'?

Hnh 9 1 So kt ni 2 led ma trn
trong bi ny chng ta s dung mach ri c 2 led ma trn. Trong so ny ng d
liu(16 bits) c truyn theo giao thc SPI, dich tng bit d liu ra cho con IC TPIC595 cn
ng chon hng ca led ma trn(8 bits) c kt ni truc tip vi PORTD ca vi iu khin
PIC,nn co ch truyn y l truyn theo kiu song song.
W.2 XP@ 3Z'? ch%L'? t"0'h
Tong tu i vi nhng bi qut led trn, ch khc y chng ta kt hp c phong php
truyn song song v phong php truyn ni tip SPI.Vi mach ri c thit k 2 led ma trn
s tao thm iu kin thuc hin nhng hiu ng chay ch a dang p mt, nh nhng
bng quang bo hay thy thuc t.
Code:
void scan_2_led_matrix(void)
{
PORTD = 0;
SSPBUF = green_buffer[index]; // high byte green color
SSPBUF = green_buffer[MAX + index]; // low byte green color
SSPBUF = red_buffer[index]; // low byte red color
SSPBUF = red_buffer[MAX + index]; // high byte red color
latch_spi();
PORTD = 1 << index;
index = (index+1) % 8;
}
Trong th vin source code, chng ti co demo mu hiu ng ch chay vi hai mu xanh v
, cc ban c th tham kho trong ti liu nh km.
W.3 Co3! mNu
Download tai y
74

Bi 13 : Gi2o ti9p ';i ti9p I2C ) DH13+<
MFc <.ch&
Tm hiu chun giao tip I2C v module I2C ca PIC18F.
Tm hiu IC thi gian thuc DS1307.
O>0 cP0&
Vit chong trnh hin thi thng tin ngy gi ln LCD.
1+.1 Gii thiu I2C
I2C l 1 chun truyn ni tip theo m hnh Master Slave. Mt Master c th giao tip vi
nhiu Slave. Mun giao tip vi slave no, master phi gi ng ia ch tch cuc slave ri
mi c php ghi hoc oc d liu t slave.

Hnh 10.1 : I2C interface

Bus I2C gm 2 dy tn hiu SCL (Serial Clock Line) v SDA (Serial Data Line) u c ko ln
ngun. D liu c truyn tng bit SDA theo tng clock ca SCL.

Hnh 10.2 : I2C Protocol

Hnh 11.2 l giao thc I2C. Trc khi truyn d liu, ta cn khi ng I2C bng cch ko ln
lt SDA v SCL xung mc thp. Sau 8 bit d liu s c ra tun tu theo tng canh
xung chn SCL. Clock th 9 s dnh cho bit ACK. Bit ACK ny c th l do master gi xung
hoc do slave gi v. Khi kt thc giao tip I2C, ta phi stop n bng cch ko 2 chn SCL v
SDA ln mc cao.
1+.2 I2C t"o'? PIC18I472+
Module I2C trong PIC18F4520 h tr mode master v c slave (7bit ia ch v 10bit ia ch).
Trong ti liu ny chng ti ch gii thiu chnh mode master ca PIC18F4520 giao tip vi
75

IC real time clock DS1307. File i2c.h inh ngha 1 s hng s v 4 hm co bn ca giao tip
I2C.
Code:
#ifndef __I2C_H
#define __I2C_H
/* PIC18 I2C peripheral library header */
/* SSPCON1 REGISTER */
#define SSPENB 0x20 // Enable serial I2C port
#define SLAVE_7 6 // I2C Slave 7bit mode
#define SLAVE_10 7 // I2C Slave 10bit mode
#define MASTER 8 // I2C Master mode
/*I2C interface*/
void i2c_init(unsigned char sync_mode,unsigned char slew, unsigned char baudrate
); //open I2C port
void i2c_start(); //start condition
void i2c_stop(); //stop condition
void i2c_write_byte(unsigned char abyte);
unsigned char i2c_read_byte(unsigned char ACK);
#endif
10.2.1 H i2c"ini!
u tin ta phi thit lp chiu input cho 2 chn SCL v SDA bng cch thit lp 2 bit tong
ng trong thanh ghi TRISC l 1.

PIC18F4520 s ng vai tr l master gi clock, ni dung trong thanh ghi SSPADD s c
dng cho b sinh clock. Tn s cho giao tip I2C s c tnh theo cng thc sau y
Code:
f = Fosc/4*(SSPADD + 1)
Ta s chon tn s cho SCL l 100kHz v phi nap vo thanh ghi ny gi tri 49 (0x31) cho
thanh anh 20MHz.

Tip theo l chon mode master cho PIC18F4520, thit lp SSPM3:SSPM0 1000 v enable
bit SSPEN trong thanh ghi SSPCON1.
Code:
void i2c_init(unsigned char sync_mode,unsigned char baudrate )
{
SSPSTAT &= 0x3F; // power on state
SSPCON1 = 0x00; // power on state
SSPCON2 = 0x00; // power on state
SSPCON1 |= sync_mode; // select serial mode
DDRCbits.RC3 = 1; //Set SCL to input
DDRCbits.RC4 = 1; //Set SDA to input
SSPADD = baudrate;
SSPCON1 |= SSPENB;//enable I2C
}
10.2.2 H i2c"%!a$!
khi ng I2C (Start condition) ta ch cn set bit Start Enable, SEN (SSPCON20) v ch
cho n khi qu trnh ny kt thc. u trnh khi ng I2C gm nhiu gian oan, kt thc
mi giai oan s c cc c bo hiu.
76

Hnh 10.3 : Khi ng I2C

Ban u 2 chn SDA v SCL mc cao. Khi SEN 1, b sinh baudrate bt u m v khi ht
time out, chn SDA ko xung mc thp, bit S (SSPSTAT3) bt ln 1 bo hiu giai oan 1
ca qu trnh khi ng I2C kt thc. Sau b sinh baudrate c load lai v bt u m.
Khi ht time out, chn SCL s c ko xung thp, kt thc qu trnh khi ng I2C. Lc ny
bit SEN c xa bng phn cng v bit SSPIF c bt ln 1.

Khi hin thuc code nu vit k ta c th ch tng giai oan, tuy nhin module I2C c tch
hp sn trong PIC nn xc sut li cng rt thp. Ta c th lm on gin hon bng cch set bit
SEN ln v ch cho n khi SSPIF bt ln 1. Ta cn phi xa SSPIF cho ln kim tra tip theo
v bit ny khng c tu ng xa bng phn cng.
Code:
void i2c_wait()
{
while(PIR1bits.SSPIF != 1){}; //wait SSPIF set
PIR1bits.SSPIF = 0; //clear SSPIF
}
void i2c_start()
{
SSPCON2bits.SEN = 1; //set start enable bit
i2c_wait(); //wait SSPIF set
}
10.2.3 H i2c"%!o-

77

Hnh 10.4 : Stop I2C

u trnh kt thc I2C c bt u bng cch set bit PEN (SSPCON22). Cng ging nh
qu trnh khi ng, qu trnh kt thc gm 2 giai oan chnh v mi giai oan u c bit
bo hiu nhng ta c th lp trnh on gin bng cch set bit PEN v ch cho n khi SSPIF
c set ln 1.
Code:
void i2c_stop()
{
SSPCON2bits.PEN = 1; //set stop enable bit
i2c_wait(); //wait SSPIF is set
}
10.2.4 H i2c"Q$i!#"R(!#
Vic gi 1 byte d liu t master xung slave c bt u khi c lnh gn vo thanh ghi
SSPBUF. Ngay lc ny c BF (Buffer Full) s bt ln 1. u trnh gi d liu bt u theo tng
xung clock chn SCL.
Sau 8 clock, 8 bit d liu trong thanh ghi SSPBUF c shift ht v c BF bt xung 0. Master
s th chn SDA slave c th gi tn hiu ACK v master. Nu nhn c ACK, bit ACKSTAT
s c xa, ngc lai bit ny s c bt ln 1. Gi tri ACK c lu trong bit ACKDT.
u trnh gi ACK t slave ln master c thuc hin trong clock th 9 ca SCL v sau bit
SSPIF c set ln 1.
Ngi lp trnh c th check qua cc c BF, ACKSTAT v sau cng l SSPIF kim tra li.
oan code di y ch kim tra c nhn c ACK hay khng ch cha kim tra ACK ng
hay sai.
Code:
void i2c_write_byte(unsigned char abyte)
{
SSPBUF = abyte;
//wait BF is set
while(SSPSTATbits.BF != 0){}
//wait ACK received, ACKSTAT is set

while(SSPCON2bits.ACKSTAT != 0){}
i2c_wait();
}
Tuy nhin trong 1 vi ng dung on gin ta c th vit nh sau:
Code:
78

void i2c_write_byte(unsigned char abyte)
{
SSPBUF = abyte; //byte to send
}
10.2.5 H i2c"$#a)"R(!#
Hm ny dng oc 1 byte d liu t slave v. Khi bit RCEN (SSPCON23) c set ln 1,
d liu t slave bt u gi vo thanh ghi SSPBUF. Sau 8 clock d liu s c shift vo
thanh ghi SSPBUF v c BF s c bt ln 1. ng thi c SSPIF cng c set v RCEN c
clear bng phn cng.
Khi oc xong, c SSPIF s c xa, ta cn set ACKEN ln 1 (SSPCON24) gi ACK v
cho slave. Bit ACK l 0 hay 1 c quy inh trong bit ACKDT (SSPCON25). Khi gi xong
ACK clock th 9, c SSPIF s c bt ln lai.
Code:
unsigned char i2c_read_byte(unsigned char ack)
{
SSPCON2bits.RCEN = 1; //enable receive

SSPCON2bits.ACKDT = ack; //set ACK value
SSPCON2bits.ACKEN = 1; //enable ACK feedback
return SSPBUF;
}
1+.3 A!2 ,im! CocC DH13+<
DS1307 l IC thi gian thuc (Real time clock) m gi, pht, giy, thng, ngy ca thng,
ngy ca tun, nm k c nm nhun (n nm 2100).

56 byte Ram lu tr d liu, nhng d liu khng bi mt khi tt ngun.
S dung 2 dy tn hiu truyn d liu theo giao thc I2C.

C th lp trnh c xut tn hiu xung vung. Tu ng pht hin ra ngun cung cp bi li
(ngt ngun) v chuyn qua mach bo v s dng ngun pin du tr.

10.3.1 =g0(>n 5? ho! <ng
DS1307 hoat ng nh mt slaver trn bus d liu ni tip. truy xut ni dung ta phi thit
lp mt iu kin Start v cung cp m nhn dang ca IC (Device Identification Code) theo
sau bi thanh ghi ia ch. Cc thanh ghi theo sau c truy xut tun tu cho n khi gp tn
hiu Stop.
Khi VCC 1.25Vbat th DS1307 s kt thc vic truy xut v reset lai b m ia ch. Cc
Input s khng c nhn ra tai thi im ny ngn nga mt s lng ln d liu c ghi
ti DS1307 t h thng bn ngoi. Khi VCC Vbat th ic ny s chuyn sang mode s dung
pin du tr. Khi ngun chnh c bt ln th IC ny s chuyn t dng ngun pin sang dng
ngun chnh. Hnh sau m t nhng phn chnh ca DS1307.
79

Hnh 10.5 : So khi DS1307
10.3.2 8Ec !.n hiC0 Hn-0! v :0!-0!
VCC, GND : Ngun DC c cung cp cho IC qua nhng chn ny. Khi gn vo ngun 5V th IC
ny c th oc ghi bnh thng. Nhng khi ngun gim xung cn 3V th vic oc ghi s khng
c php. Tuy nhin, cc chc nng ca timer vn tip tuc vi ngun cung cp thp. Khi Vcc
gim xung di VBAT th RAM v timekeeper c chuyn qua s dung ngun cung cp tai
VBAT.

VBAT : Cung cp ngun d tr 3V. hoat ng ch s dung ngun Vbat th 2.0V Vbat
3.5V. Khi VCC gn bng 1.25VBAT th chng ta s khng c php truy xut vo RTC (Real
time clock) v Ram bn trong ca IC.

SCL (Serial Clock Input) : SCL c dng ng b d liu trn ng truyn ni tip.

SDA (Serial Data Input/Output) : SDA l chn I/O. SDA l chn Open drain nn cn c in tr
ko ln bn ngoi.

SW/OUT (Square Wave/Output Driver) : Khi c bt ln, th bit SWE set ln 1, v chn
ny s output ra 1 trong 4 tn s sng vung l 1hz, 4khz, 8khz, 32khz. Chn ny cng l
chn Open drain nn cng yu cu c in tr ko ln ngun bn ngoi. SW/OUT s hoat
ng khi c ngun cung cp vo cho d l ngun VCC hay l VBAT.

X1, X2 : Kt ni vi thach anh 32.768Khz. Mach tao xung bn trong c thit k hoat
ng vi thach anh v tu CL 12.5 pF.

80

10.3.3 6T8 v %S <T <Ua chV 6a
So ia ch ca RTC v cc thanh ghi Ram ca DS1307 nh hnh di. Cc thanh ghi RTC
c inh ia ch t 00h n 07h. Cc thanh ghi Ram c inh ia ch tip theo sau v t
08h n 3fh. Trong khi truy sut nhiu byte v khi con tr ia ch ch ti 3fh, vi tr cui ca
vng nh Ram, th n s quay lai ia ch 00h truy xut tip.

Hnh 10.6 : RTC v so RAM
10.3.4 ThWng !in !hXi gian v 5Uch
Thng tin thi gian v lich c cha trong trong cc thanh ghi tong ng. Cc thanh ghi RTC
nh hnh trn. Thi gian v lich c set hoc khi tao bng cch ghi ra cc byte thanh khi
tong ng. Ni dung ca cc thanh ghi thi gian v lich c inh dang theo kiu BCD. Bit 7
ca thanh ghi 0 l clock halt bit (CH). Khi bt ny c set ln 1 th mach dao ng s bi n
khng c s dung na, khi clear xung 0 th mach dao ng s c kch hoat tr lai.

DS1307 c th chay ch 12h hay 24h. Bt th 6 ca thanh ghi hours c inh ngha
set xem s dung IC ny ch no. Khi bit ny bng 1 th ch 12h c chon. Trong ch
12h th bit 5 ch AM/PM (PM khi bit ny l 1). Trong ch 24h, th bt 5 l bt th 2 ca
10hour (20:23).

Hnh 10.7 : inh dang d liu
10.3.5 9hi )N 5iC0 vo 4G1307
81

Hnh 10.8 : Ghi d liu vo DS1307
y l qu trnh truyn d liu t master xung slave. Khi master gi xong 1 byte, slave s
gi lai bit ACK. u trnh giao tip nh sau:
Master gi tn hiu Start.
Master gi ia ch ca DS1307 (1101 000) v bit R/W, trong trng hp ny l 0. Byte
u tin m master gi xung sau khi start l D0.
Master gi ia ch pointer d liu cn ghi, chng han l 0x00 (register pointer, word
address)
Master gi cc byte data cn ghi.
Master gi tn hin stop.
Code hin thuc cho qu trnh ny nh sau
Code:
void rtc_write(unsigned char *buff)
{
i2c_start();
i2c_write_byte(0xD0); //Address + Write bit
i2c_write_byte(0x00); //Pointer
i2c_write_byte (*(buff+0)); //Second
i2c_write_byte (*(buff+1)); //Minute
i2c_write_byte (*(buff+2)); //Hour
i2c_write_byte (*(buff+3)); //Day
i2c_write_byte (*(buff+4)); //Date
i2c_write_byte (*(buff+5)); //Month
i2c_write_byte (*(buff+6)); //Year
i2c_stop();
}
buff l 1 mng c 7 phn t, tong ng vi cc gi tri giy, pht, gi, th, ngy, thng v
nm.

10.3.6 YZc )N 5iC0 ![ 4G1307

Hnh 10.9 : oc d liu t DS1307
y l qu trnh truyn d liu t slave ln master. Nh trnh by phn trc, khi gi
nhn tng byte, s c bit ACK i km ngoai tr byte cui cng trc khi stop.
c th oc chnh xc gi tri mong mun, thng thng ta phi ghi vo thanh ghi ia con tr
d liu (register pointer). u trnh ny chnh l trnh truyn d liu t master xung slave
nn R/W bit s l 0. Sau khi ghi d liu v register pointer xong, qu trnh oc d liu mi bt
u, v bit R/W s l 1.
Tng bc oc d liu t DS1307 nh sau:
82

Master gi tn hiu start.
Master gi ia ch DS1307 R/W 0 : 0xD0.
Master gi byte ghi vo register pointer : 0x00.
Master gi tn hiu start
Master gi ia ch DS1307 R/W 1 : 0xD1.
Master oc cc byte d liu v gi bit ACK. Byte cui cng trc khi stop, master gi bit
NACK.
Master gi tn hin stop.
Code hin thuc cho qu trnh ny nh sau
Code:
void rtc_read(unsigned char * buff)
{
//send address to slave and reset pointer
i2c_start();
i2c_write_byte(0xD0); //Address + Write bit
i2c_write_byte(0x00); //Pointer
i2c_start(); //Restart
i2c_write_byte(0xD0); //Address + Read bit
*(buff+0)=i2c_read_byte(ACK); // Second
*(buff+1)= i2c_read_byte(ACK); // Minute
*(buff+2)= i2c_read_byte(ACK); // Hour
*(buff+3)= i2c_read_byte(ACK); // Day
*(buff+4)= i2c_read_byte(ACK); // Date
*(buff+5)= i2c_read_byte(ACK); // Month
*(buff+6)= i2c_read_byte(ACK); // Year
i2c_stop();
}
1+.4 XP@ 3Z'? ch%L'? t"0'h
y s gii thiu cu trc chong trnh hin thi thng tin ngy thng nm, gi pht giy ca
DS1307 ln LCD. Chong trnh gm 3 module 9 l I2C, RTC v LCD.

Hnh 10.10 : Cu trc chong trnh
Chi tit chong trnh c hin thuc trong th muc Bai11_I2C. chay c chong trnh ban
cn bt 2 switch ca RTC (SW4) ln ON, bt ngun ca LCD (SW3) v tt led PortB (SW1).
83

Hnh 10.11 : Chong trnh DS1307 trn BKIT PIC
1+.7 Co3! mNu

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84

Bi 14 : A'2o? to Di?it2 Co')!"t!" ADC

MFc <.ch&
Tm hiu module ADC ca PIC18F.
O>0 cP0&
Vit chong trnh hin thi gi tri ADC chn AN0 ln LCD.
11.1 Gii thiu
Vi iu khin ch c th x l c tn hiu s ri rac (digital signal), chng khng th x l
c cc tn hiu tong tu (analog signal). B chuyn i tn hiu tong tu sang s (analog to
digital converter) hay cn goi l ADC, s chuyn in p tong tu (analog voltage hay analog
signal) sang dang s ri rac (digital number). Vi x l s biu din tn hiu in p tong tu
thnh 1 s nguyn (non-fractional number) v s x l trn s nguyn ny.

Hnh 11.1: Analog to Digital Converter
Theo v du trn, in p 2.343volt s c chuyn i thnh s nguyn 87. Ngi lp trnh
c th dng s 87 ny biu din cho gi tri in p ng vo 2.343 volt. Vic vi iu khin
x l trn s 87 s at hiu qu cao hon, v n l 1 s nguyn.
11.2 G?u@(' e chu@T' fi ADC

Hnh 11.2 : Chuyn i ADC
u trnh chuyn i ADC gm 3 giai oan:
Giai oan 1 : Nap in cho tu chn ADC (Holding Capacitor). Giai oan ny tn 1
khong thi gian c goi l Acquisition time (TAC). Trong vi iu khin PIC, thi gian
ny c th c cu hnh bng tay hoc tu ng. Khi chon cu hnh bng tay, ngi lp
trnh phi tu tnh ton thi gian delay c th nap y tu trc khi ban hnh lnh
chuyn i. Khi chon cu hnh tu ng, vi iu khin s m bo l sau khi ban hnh
lnh chuyn i 1 khong TAC, qu trnh chuyn i mi bt u. Thi gian ny l 1
hng s v ty thuc vo vi iu khin. Chng ta cn oc k datasheet ca n xc
inh cho ng.
Giai oan 2 : Ngt kt ni vi tu Holding Capacitor bng 1 lnh SLEEP. u trnh ny
c thuc hin tu ng bi vi iu khin, ngi lp trnh khng cn phi quan tm. Thi
gian chuyn i phu thuc vo phn gii ca gi tri ADC (8bit, 10bit hay 13 bit) v
clock cp cho module ADC. Khi lp trnh, chng ta thng khng quan tm n thi
gian ny v khi chuyn i xong, vi iu khin s set c bo hiu. Ngi lp trnh ch
cn polling xt c ny hoc s dung ngt ly gi tri chuyn i.
Giai oan 3 : X tu Holding Capacitor. Giai oan ny ch chim 1 khong thi gian nh
v n c thuc hin tu ng bi vi iu khin. Giai oan ny xy ra sau khi c bo
hiu chuyn i hon tt.
c th bt u tip vic chuyn i ln th 2, vi iu khin s cn phi ch thm 1
khong thi gian x tu v acquisition time. Nu khng ch ng thi gian ny, qu trnh
chuyn i bt u sm hon, kt qu thu c c th khng cn chnh xc na.
11.3 ADC t"o'? PIC18I
i vi dng chip PIC 40/44 chn c 13 knh ADC, dng 28 chn th c 10 knh ADC. Module
ADC s chuyn i tn hiu tong tu thnh tn hiu s 10 bit. Module ADC trong PIC c 5 thanh
ghi:
85

ADRESH : Thanh ghi kt qu, cha phn bit cao.
ADRESL: Thanh ghi kt qu, cha phn bit thp.
ADCON0, ADCON1, ADCON2 : Cc thanh ghi iu khin.

,h2'h ?hi ADCFG+

Hnh 11.3 : Thanh ghi ADCON0

Bit <g6 : Khng s dung.
Bit 7g2 ChH3gChH+ : Lua chon knh Analog.
0000 : Knh 0 (AN0)
0001 : Knh 1 (AN1)
0010 : Knh 2 (AN2)
1101 : Knh 11 (AN11)
1100 : Knh 12 (AN12)
1101,1110,1111 : Khng s dung.
Bit 1 GFiDFGE : Bit trang thi ca qu trnh chuyn i khi ADON 1.
1 : ang chuyn i A/D.
0 : Chuyn i hon tt.
Bit + ADFG : A/D On bit
1 : Cho php chuyn i.
0 : Tt chc nng chuyn i.
,h2'h ?hi ADCFG1

Bit < j 6 : Khng s dung.
Bit 7 : VCFG1 Voltage Reference Configuration bit (bit cu hnh in p tham kho VREF-)
1 : in p tham kho VREF- l in p chn AN2
0 : in p thao kho VREF- VSS
Bit 4 : VCFG0 Voltage Reference Configuration bit (bit cn hnh in p tham kho VREF)
1 : in p tham kho VREF l in p chn AN3
0 : in p tham kho VREF l VDD
Bit 3g+ A/D Port Configuration Control bits : Cu hnh chn l Analog hay Digital

,h2'h ?hi ADCFG2

Bit < ADIM : inh dang kt qu trong 2 thanh ghi ADRESH v ADRESL
1 : Canh phi

0 : Canh tri

Bit 6 : Khng s dung
Bit 7g3 : A/D Acquisition Time Select bit : Bit chon thi gian nap cho tu Holding Capacitor.
86

111 : 20 TAD 110 : 16 TAD 101 : 12 TAD 100 : 8 TAD
011 : 6 TAD 010 : 4 TAD 001 : 2 TAD 000 : 0 TAD
TAD l thi gian chuyn i 1 bit ADC, phu thuc vo clock c lua chon bn di. Thi
gian nap cho tu Holding Capacitor c inh l 2.4us, sau khi chon clock cho module ADC, ta
s phi tnh ton chon h s nhn vi TAD

Lu trong trng hp 000, y l ch lp trnh bng tay cho thi gian Acquisition Time,
ngi lp trnh phi tu tao 1 khong thi gian delay cho qu trnh nap tu Holding Capacitor.

Bit 2g+ : A/D Conversion Clock Selection bit : Bit chon clock cho b chuyn i A/D
111 : FRC 110 : FOSC/64 101 : FOSC/16 100 : FOSC/4
011 : FRC 010 : FOSC/32 001 : FOSC/8 000 : FOSC/2
Nu ta chon l 000 th TAD 2 TOSC 2/FOSC, FOSC l chu k lnh, bng tn s dao
ng.

11.4 C/u h0'h ADC t"o'? PIC18I
Vic cu hnh module ADC trong PIC18F i theo trnh tu sau:
Cu hnh chn A/D (s knh AD, chiu ca chn AD l input), in p tham kho
(ADCON1)
Chon knh A/D (ADCON0)
Chon thi gian acquisition time (ADCON2)
Chon clock.
Bt ch AD (bit ADON trong ADCON0).
Nu chon lua ch acquisition time l tu ng, ban ch cn set bit GO_DONE bt u qu
trnh chuyn i v polling bit ny ch cho n khi qu trnh chuyn i hon tt.

Nu acquisition time c chon l ch chnh bng tay (manual mode), ban phi tu vit
delay ch, sau mi c php set bit GO_DONE.
11.7 hi' thZc ch%L'? t"0'h

Hnh 11.6 : Kin trc chong trnh ADC

11.5.1 H ini!"a)c23
Hm ny dng khi tao ban u cho module ADC, c hin thuc ng theo trnh tu cu
hnh ADC trong PIC 18F. mach BKIT PIC, ch c 1 knh ADC ni vi chn AN0, bit 0 ca
PortA.

thanh ghi ADCON1, ta s ln lt chon in p tham kho l VSS v VDD, cc bit 5,4 set l
0.

Cu hnh ch dng 1 knh AD chn AN0, bit 3:0 PCFG3:PCFG0 1110, ADCON1 0x0E. Cu
hnh chiu input cho chn ADC ny.

Chon knh AD0 chuyn i bng cch thit lp CHS3:CHS0 0000, ADCON0 0x00.

Chon clock l FOSC /2 (ADCS2:ADCS0 000), lc TAD 2TOSC 2/(5MHz) 2/(5106)
(s).
87

Thi gian acquisition time l hng s 2.4us 2.4 10-6 (s).
Ta phi tha mn c 2.4 10-6 2k/(5106) k 1.2
Ta s chon k 2 ACT2:ACT0 001.
Nh vy ADCON2 0x04.
Bt bit ADON thanh ghi ADCON0.
Code:
void init_adc()
{
TRISA = 0x01; //input for analog pin
ADCON1 = 0x0E; //config ADC pins
ADCON0 = 0x00; //select AN0
ADCON2 = 0x04; //select acquisition time
ADCON0bits.ADON = 1; //enable ADC
}

11.5.2 H g#!"a)c"va50#
Sau khi khi tao xong module ADC, ta c th ly kt qu bt c lc no. Trc tin ta s set
bit GO_DONE ln 1 bt u qu trnh chuyn i v ch cho n xung 0, vic chuyn i
hon tt, kt qu s c lu trong 2 thanh ghi ADRESH:ADRESL (ch canh tri).
Code:
int get_adc_value()
{
int result = 0;
ADCON0bits.GO_DONE = 1; //start conversion
while(ADCON0bits.GO_DONE == 1){} //polling
result = ADRESH;
result = (result<<2) + (ADRESL>>6);
return result;
}
Nu ngi dng ch cn 8 bit th c th s dung gi tri trong thanh ghi ADRESH l .

Hnh 11.7 : Chong trnh ADC trn BKIT PIC
11.6 Co3! mNu

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Bi 17 : îSu ch9 Bu'? PcM

MFc <.ch&
Tm hiu module CCP1 ca PIC18F, thit lp ch hoat ng PWM.
O>0 cP0&
Vit chong trnh iu khin tc ng co, hin thi tc ra mn hnh LCD.
12.1 :h#i 'im PcM
PWM vit tt ca t Pulse Width Modulation. PWM c s dung nhiu trong h thng iu
khin tu ng ngy nay. N c ng dung trong iu khin tc ng co, sng ti ca
led, mn hnh LCD, pha mu cho bang quang bo, s dung trong cc thut ton iu khin vn
tc cho Robot nh PI, PD, PID .

Hiu on gin PWM hoat ng nh mt cng tc ng m rt nhiu ln trong 1 giy. Nu tn
s ng m cng nhanh th in p cp trung bnh cng ln.

Mt s khi nim co bn ca PWM :
Tn s (Hz, Khz.).
Chu k T, thi gian xung mc cao TH thi gian xung mc thp TL.
Duty Cycle: t l thi gian xung mc v thi gian xung mc thp.

Nh hnh trn ta c Duty Cycle ln lt l 0, 25, 50, 75, 100.
Mt s cng thc :
89

Khi nu TOn 0 th VoltOutput 0 (V) cn TOn TTotal th VoltOutput VoltInput .

12.2 PcM t"o'? PIC18I472+
PIC18F4520 c 2 module CCP. y chng ti gii thiu module CCP1. Module ny ngoi chc
nng PWM thng thng, n cn c chc nng Enhanced PWM dng iu khin mt s loai
mach cu H thng dung.

Nguyn l hoat ng chung ca cc module PWM tch hp sn trong vi iu khin l n s s
dung 1 b timer m. Khi gi tri m ca timer bng vi Chu k hoc Duty Cycle th ng ra
s thay i. Hnh di y minh hoa cch hoat ng ca module PWM trong PIC18F4520, n
s dung timer2 cho b m.

Hnh 12.1 : Nguyn l hot ng ca PWM

Trnh tu thit lp PWM trong PIC18F4520 nh sau:

12.2.1 Thi\! 5,- ch0 'K P]M
Chu k ca module CCP1 c tnh nh sau :

PWM Period (PR2 1)4TOSC(TMR2 Prescaller)

Trong TOSC 1/FOSC, FOSC 20MHz nu s dung thach anh ngoi.

TMR2 Prescaller c xc inh trong thanh ghi T2CON. ch mc inh ban u, TMR2
Prescaller1.

Trn thuc t, ngi ta dng thut ng tn s PWM, l nghich o ca chu k :
90

PWM Frequence FOSC/ (PR21) 4 (TMR2 Prescaller)

Tn s iu khin PWM ty thuc vo tng loai thit bi. i vi ng co, tn s PWM phi
ph hp vi p ng ca driver iu khin ng co.

Trong mach BKIT PIC, chng ti chon tn s l 2 kHz. Gi s ta chon TMR2 Prescaller l 16
(T2CKPS1 1), th gi tri ca PR2 l

PR2 20MHz/ (4 16 2KHz) - 1 155

12.2.2 Thi\! 5,- P]M 40!( 8(c5#
Duty Cycle ca CCP1 c thit lp trong 2 thanh ghi CCPR1L (8bit) v 2 bit DC1B1:0 trong
thanh ghi CCP1CON. Tuy nhin i vi ng co nh th vi 8 bit l , ta c th mc inh
DC1B1:0 00 ngay khi khi tao. Gi tri ca CCPR1L cng cao th duty cycle cng ln, v nh
vy in p ng ra ca CCP1 (RC2) cng cao.

Sau khi thit lp xong 2 thng s trn, cc bc cn lai l thit lp chiu output cho chn
RC2, cho php timer2 m bng cch set bit TMR2ON ln 1, v cu hnh CCP1CON l ch
Single PWM.

12.3 XP@ 3Z'? ch%L'? t"0'h
Kin trc chong trnh gm c 2 module chnh PWM v LCD.

Hnh 12.2 : Kin trc chong trnh PWM

Module PWM gm c 2 file pwm.h khai bo cc interface v pwm.c hin thuc cc interface
. Interface trong pwm.h nh sau:
Code:
#ifndef _PWM_H_
#define _PWM_H_
#include <P18F4520.h>
void init_pwm();
void set_DC(unsigned char duty_cycle);
#endif
12.3.1 H ini!"-Q
Hm ny hin thuc qu trnh khi ng cho module PWM. Trc tin l cu hnh prescaller cho
timer2, nap gi tri PWM Period v chon ch PWM trong thanh ghi CCP1CON.
Code:
91

void init_pwm()
{
T2CONbits.TMR2ON = 0; //turn off timer2

T2CONbits.T2CKPS1 = 1; //prescaler 1:16
PR2 = 155; //PWM period
CCP1CONbits.DC1B0 = 0; //PWM duty cycle
CCP1CONbits.DC1B1 = 0; //2 bits LSB
CCPR1L = 0x00; //8bits MSB
CCP1CONbits.P1M0 = 0; //PWM single mode
CCP1CONbits.P1M1 = 0;
CCP1CONbits.CCP1M0 = 0;//select PWM function
CCP1CONbits.CCP1M1 = 0;
TRISCbits.TRISC2 = 0; //config RC2 output
T2CONbits.TMR2ON = 1; //start timer2
}
12.3.2 H %#!"48
Hm ny ch on gin l thit lp duty cycle trong thanh ghi CCPR1L. Gi tri trong thanh ghi
ny cng cao th p ra chn RC2 cng cao, gi tri ti a l 255 tong ng vi khong 5V.
Code:
void set_DC(unsigned char duty_cycle)
{
CCPR1L = duty_cycle;
}
Chong trnh demo cho phn ny c hin thuc trong th muc Bai13_PWM. Hm main s
tng dn duty cycle ln v ng co s quay nhanh dn. Gi tri ca duty cycle (hay tc ca
ng co) s c hin thi ra LCD.

12.4 Co3! mNu
Download tai y

92

Bi 16 : Gi2o ti9p bAA, AH232
13.1 G?u@(' e ?i2o ti9p bAA,
Uart RS232 l chun giao tip kh ph bin v c h tr hu ht cc dng vi iu khin v
khong cch xa v chi ph thp. Dng 8051 h tr 1 knh giao tip uart.
D liu c truyn i trn chn TX gm 1 start bit (mc 0), data v 1 stop bit (mc 1).

Tc truyn : on vi bit per second (bps) cn goi l Baud (s ln thay i tn hiu trong 1
giy thng s dung cho modem). i vi ng truyn th Baud v bps l nh nhau.
UART l phong thc truyn nhn bt ng b. ngha l bn nhn v bn pht khng cn phi
c chung tc xung clock (v du : xung clock ca vi iu khin khc xung clock ca my tnh)
. Khi bn truyn mun truyn d liu s gi start bit (bit 0) bo cho bn thu bit bt
u nhn d liu v khi truyn xong d liu th stop bit (bit 1) s c gi bo cho bn thu
bit kt thc qu trnh truyn.
Khi c start bit th c hai bn s dng chung 1 xung clock (c th sai khc mt t) vi rng
1 tn hiu (0 hoc 1) c quy inh bi baud rate, v du baud rate 9600bps ngha l rng
ca tn hiu 0(hoc 1) l 1/9600 104 ms v khi pht th bn pht s dng baud rate chnh
xc (v du 9600bps) cn bn thu c th dng baud rate sai lch 1 t(9800bps chng han).
Truyn bt ng b s truyn theo tng frame v mi frame c cu trc nh sau:

Ngoi ra trong frame truyn c th c thm bit odd parity (bit l) hoc even parity (bit chn)
kim tra li trong qu trnh truyn. Bit parity ny c c im nu s dung odd parity th s
cc bit 1 odd parity bit s ra 1 s l cn nu s dung even parity th s cc bit 1 even
parity bit s ra 1 s chn.
13.2 Gi2o ti9p bAA, )i m#@ tJ'h
giao tip COM gia vi iu khin v my tnh, ta kt ni mach theo so nh sau:
93

Hnh 13.1 : Kt ni my tnh v vi iu khin
Do mc in p ca tn hiu logic 1/0 cng COM ca my tnh khc vi vi iu khin, nn
MAX 232 c tc dung chun ho mc in p gia my tnh v iu khin trong qu trnh
truyn nhn d liu. Nu giao tip truc tip gia 2 vi iu khin, ta khng cn phi s dung
MAX 232.

13.3 bAA, t"o'? PIC18I
Trong phn ny xin gii thiu cc bc thit lp vic truyn 1 byte UART, vic cu hnh nhn
UART cng tong tu nh truyn. Trnh tu cc bc nh sau :
Nap gi tri vo 2 thanh ghi BRGH: BRG thit lp tc truyn theo cng thc
Baudrate Fosc/ (64 (BRGH : BRG 1)).
Enable serial port bng cch clear bit SNC v set bit SPEN
Nu mun thit lp interrupt, th set thm TXIE, GIE v PEIE.
Set bit TXEN cho php truyn.
Nap d liu vo thanh ghi TXREG.
Khi truyn xong c TXIF s bt ln 1, ta s kim tra c ny trc khi truyn d liu
mi.
Hin thuc bng code nh sau :
94

Code:
void init_uart_transmit()
{
//step 1 : Select baurate
TXSTAbits.BRGH = 0;
BAUDCONbits.BRG16 = 1;
SPBRGH = 0;
SPBRG = 25; //9600
//step 2 : enable ASYN
TXSTAbits.SYNC = 0;
RCSTAbits.SPEN = 1;

//step 3 : enable uart transmission interrupt
PIE1bits.TXIE = 1;
PIR1bits.TXIF = 0;
INTCONbits.GIE = 1;
INTCONbits.PEIE = 1;

//step 4 : disable bit 9
TXSTAbits.TX9 = 0;
//step 5 : enable transmission
TXSTAbits.TXEN = 1;
}
Sau khi enable vic truyn, ta ch cn ghi d liu v thanh ghi TXREG v kim tra c TXIF bt
ln:
Code:
void uart_transmit(unsigned char data)
{
TXREG = data;
while(PIR1bits.TXIF == 1){}
}
13.4 :iTm t"2 t"u@S' 'h&' bAA,
kim tra vic truyn nhn uart c ng hay khng ta thng dng 1 s ng dung hyper
terminal kim tra. Lc ny my tnh ca chng ta s l i tng dng giao tip vi BKIT
PIC. Trong a CD ny c phn mm hyper terminal kh thng dung cha trong th muc
Terminal, ban ch cn double click vo file Terminal.exe l khi ng c chong trnh.
95

Hnh 13.2 : Hyper Terminal
Cng vic cn lai l cu hnh cho cng COM truyn nhn uart cho tong thch vi giao thc
truyn nhn ca board 89. Cc thng s thng thng l Baud rate 9600, Data bit 8bit, khng
c Parity (chon none) v 1 Stop bit. Nhn nt Connect kt ni. K t y nu board 89 c
gi d liu ln, d liu ny s nm trong phn Receive. Ngc lai, mun gi d liu xung
board 89 ta g vo textbox v n Send.
13.7 Do['o23
Code mu
Phn mm Terminal

96

Bi 1< : Gi2o ti9p )i $' phJm PH2
13.6 G?Et '?oi
13.6.1 9ii !hiC0 ng^! ngoi
Ngt ngoi trn vi iu khin thng l mt chn vo c kh nng pht hin su thay i tn
hiu bn ngoi. C th chia ngt thnh hai loai : Ngt canh v ngt mc.
Ngt canh c hai loai: ngt canh ln xy ra khi c su chuyn tn hiu t mc thp ln mc cao
chn ngt ngoi. Tong tu ngt canh xung xy ra khi c su chuyn tn hiu t mc cao
xung mc thp.
Ngt mc cng c hai loai: ngt mc cao v mc thp. Ngt mc cao (thp) xy ra khi tn hiu
tai chn ngt ngoi mc cao (thp) trong ti thiu 1 chu k.
Trong vi iu khin PIC ch c ch ngt canh(ln/xung) khng tn tai ch ngt mc.
13.6.2 =g^! ngoi !$ong vi <iI0 'hiJn PH8
Trong vi iu khin PIC, c 3 ngt ngoi INT0, INT1, INT2 nm tong ng vi cc chn RB0,
RB1, RB2. V trong vi iu khin PIC ch c hai loai ngt l ngt canh ln v ngt canh xung.
i vi ngt ngoi INT1 v INT2 c hai mc u tin ngt l ngt c u tin cao v u
tin thp, cn i vi ngt ngoi INT0 th lun c inh l ngt c u tin cao. Cc chn ngt
ngoi khi s dung phi c cu hnh ch input.
13.6.3 8Ec !hanh ghi <J c;0 hKnh ng^! ngoi cho PH8
Ngt trong ci iu khin PIC c cu hnh qua cc thanh ghi INTCON, INTCON2, INTCON3.
,h2'h ?hi IG,CFG

Code:
Bit 7 GIE Global Interrupt Enable
Nu IPEN = 0
1 = cho php ngt
0 = cm tt c cc ngt
Nu IPEN = 1
1 = cho php ngt mc cao
0 = cm tt c cc ngt
Bit 6 PEIE Peripheral Interrupr Enable
Nu IPEN = 0
1 = cho php ngt ngoi vi
0 = cm cc ngt ngoi vi
Nu IPEN = 0
1 = cho php ngt mc thp
0 = cm ngt mc thp
Bit 4 INT0IE External Interrupt 0 Enable
1 = cho php ngt ngoi 0
0 = tt ngt ngoi 0
Bit 0 INT0IF External Interrupt Flag
97

1 = c bo ngt ca ngt ngoi 0
0 = khng c tn hiu ngt ngoi 0
,h2'h ?hi IG,CFG2

Code:
Bit 6 INTEDG0 External Interrupr 0 Edge Select
1 = ngt ngoi 0 khi c cnh ln
0 = ngt ngoi 0 khi c cnh xung
Bit 5 INTEDG1 External Interrupr 1 Edge Select
Bit 4 INTEDEG2 External Interrupt 2 Edge Select
,h2'h ?hi IG,CFG3

Code:
Bit 7 INT2IP External Interrupt 2 Priority
1 = u tin cao
0 = u tin thp
Bit 6 INT1IP External Interrupt 1 Priority
1 = u tin cao
0 = u tin thp
0 = tt ngt ngoi 2
0 = tt ngt ngoi 1
Bit 1 INT2IF External Interrupt 1 Flag
Bit 0 INT1IF External Interrupt 1 Flag
Cc c ngt ngoi INT0IF, INT1IF, INT2IF phi c xa bng chong trnh trong hm x l
ngt ca chng.
13.< Gi2o ti9p PHi2
D liu trong giao tip PS/2 c truyn ni tip tng bit. Khi mt phm c nhn, 11 bit bao
gm Start bit, 8 bit d liu (bit trong s thp truyn trc), 1 bit parity v 1 stop bit s c
gi i:
98

Hnh 14.1 Dang sng ca giao tip PS/2
Ta s ly d liu tai canh xung ca clock, chn ca clock c ni vo chn ngt ngoi INT0
ca vi iu khin Atmega32 (PD2) nh sau:

Hnh 14 14.2 So kt ni PS/2
Khi 1 phm c nhn xung, m make_code s c gi ln. Trong khong thi gian phm
c xung th m make_code vn c inh k gi ln. Khi th phm ra th bn phm gi
ln m break_code v make_code.
Bng m make_code v break_code ca cc phm nh sau:
99

D dng nhn ra m break_code ca 1 phm gm 0xF0 v m make_code ca phm .
13.8 XP@ 3Z'? ch%L'? t"0'h
Gat bit 2 ca Switch3 ln ON gn in tr ko ln cho chn CLOCK v DATA ca bn phm
PS/2
13.8.1 *h+i !o ng^! ngoi
Code:
void init_ext_int0(void)
{
INTCONbits.INT0IE = 1; // set external interrupt0
INTCONbits.INT0IF = 0; // clear external interrupt0 flag
INTCON2bits.INTEDG0 = 0;// interrupt when appear an falling edge on
RB0/INT0
TRISBbits.TRISB0 = 1; // set input for CLOCK pin
TRISBbits.TRISB1 = 1; // set input for DATA pin
}
100

13.8.2 _` 5? ng^!
Phn chnh ca bi thuc hnh ny l ly cho c d liu truyn ln t bn phm. u trnh
dich tng bit ly d liu 8 bit trong chui 10 bit c hin thuc trong hm phuc vu ngt
ngoi INT0.
Code:
#pragma code
#pragma interrupt high_isr
void high_isr(void)
{
if (INTCONbits.INT0IF)
{
INTCONbits.INT0IF = 0;
count_bits ++;
if (count_bits == 1)
ps2_scan_code = 0;
if (count_bits >1 && count_bits < 10)
{
ps2_scan_code = ps2_scan_code >> 1;
if (PS2_DATA == 1)
ps2_scan_code |= 0x80;
parity ^= PS2_DATA;
}
if (count_bits == 12)
{
scan_code = ps2_scan_code;
ps2_scan_code = 0;
parity = 0;
}
}
}
Bin count_bits dng m s bit gi v, khi count_bit_input 11 ta s c c d liu
scan_code t bn phm truyn ln. Ban s phi x l phn loai y l m make_code hay
break_code, c c nhn km vi phm Shift hay Caps Lock hay khng chuyn sang m
ASCII cho k tu c nhn.
13.W Do['o23
Code mu

101

Bi 18 : G"2phic* LCD 128B64
14.1 Gii thiu GLCD 128B64
Graphic LCD c s dung trn mach BKIT PIC l loai LCD chm, khng mu, c phn gii
128x64 tc 8192 chm. GLCD c thit k iu khin c tng chm, nn c th dng
hin thi bt k k tu hay hnh nh no. Vi mi chm tong ng mt bit d liu, GLCD
128x64 cn 8192 bits RAM hay 1024 bytes RAM hin thi ton mn hnh.
Loai GLCD M12864 s dung 2 chip iu khin KS0108 rt ph bin ca Samsung, mi chip
c 512 bytes RAM. Do , n tong tu nh 2 LCD 64x64 ghp lai vi nhau.

Hnh 15 1 GLCD 128x64

14.1.1 8hac nbng cEc chcn cda 9L84 128L64
Chc nng cc chn:

102

Cc chn t 4 n 17 c kt ni truc tip n vi iu khin. Cc chn cn lai c kt ni
ty theo chc nng tong ng ca n.
8hcn A=
Khi thuc hin mt qu trnh giao tip vi GLCD, ban u, chn EN c ko xung thp. Trong
khi , cc chn iu khin khc c thit lp. Sau khi thit lp xong, chn EN c kch ln
mc cao cho php tn hiu. Sau khong thi gian cn thit cho qu trnh hon tt, chn EN
lai c ko xung thp sn sng cho mt qu trnh khc.
8hcn 6G v 6]
Hai chn ny c kt hp thit lp cho cc thanh ghi ca GLCD theo bng sau:

8hcn 8G1 v 8G2
Chon chip iu khin GLCD KS0108 giao tip, tch cuc mc cao.
14.1.2 Te chac R nh 67M
Chip iu khin GLCD KS0108 ch c mt loai b nh l RAM, khng c b nh cha b font
CGROM hay cha m font tu tao CGRAM nh ca Text LCD. D liu ghi vo RAM s c hin
thi truc tip trn GLCD. Mi chip KS0108 c 512 bytes RAM tong ng vi 4096 chm trn mt
na (64x64) LCD. RAM ca KS0108 c truy cp theo tng byte, ngha l mi ln vit mt
gi tri vo mt byte no trn RAM ca GLCD, s c 8 chm bi tc ng, 8 chm ny nm
trn cng 1 ct. Do , 64 dng GLCD c chia thnh 8 pages, mi page c cao 8 bit v
rng 128 ct (tnh c 2 chip).
So b tr RAM:

Hnh 15 2 So b tr RAM ca GLCD 128x64
103

Vi mi chip KS0108, RAM chia thnh 8 page, mi page bao gm 64 ct, mi ct bao gm 8
chm. Cc page c goi l ia ch X, mang gi tri t 0 n 7, X 0 tong ng vi page 0 v
tong tu. Cc ct c goi l ia ch , ct u tin c gi tri 0 v ct cui cng c gi tri
63. Mi ct l mt byte RAM, D0 n D7, vi D0 tong ng im trn cao v D7 tong ng
im bn di. Cc lnh di chuyn c h tr theo cp ia ch X, .
Minh hoa hin thi k tu a trn GLCD:

Hnh 15 3 K tu a trn GLCD
Nh hnh trn, k tu a c xc inh bng cch ghi d liu vo X 0 v 0...7 theo bng
sau:

Hnh 15 4 D liu RAM cho k tu a
Gi tri Data l cc gi tri cn nap cho vng RAM tong ng.
14.1.3 8Ec 5Cnh cda 9L84 128L64
Bng lnh
104

1. LCnh hiJn !hU :=f:gg
D liu c hin thi ln mn hnh khi bit D (DB0) bng 1 v ngc lai khi D bng 0. Khi D
bng 0, d liu vn tn tai trong DDRAM.
Lp trnh:
RW 0
RS 0
Opcode 0x3E D (D 0:1)
2. HiJn !hU G!a$! Lin#
Chon mt dng no ca RAM lm dng u tin c hin thi ln, ngha l cun hnh
nh trong RAM ln mt khong LOffset, vi LOffset c gi tri t 0 n 63. Phn bi che khut
khi cun s c hin thi tip ngay bn di. V du vi LOffset 20:

Hnh 15 5 Cun ln 20 dng
Lp trnh:
RS 0
RW 0
Opcode 0xC0 LOffset
3. Thi\! 5,- !$ang 2<Ua chV _3
105

Thit lp ia ch X truy xut RAM.
Lp trnh:
RS 0
RW 0
Opcode 0xB8 X
4. Thi\! 5,- <Ua chV O
Thit lp ia ch truy xut RAM.
Lp trnh:
RS 0
RW 0
Opcode 0x40
5. YZc !$ng !hEi
oc trang thi ca GLCD, ch yu kim tra bit BUS (bit 7).
Lp trnh:
RS 0
RW 1
6. 9hi )N 5iC0 hiJn !hU
Ghi d liu vo RAM tai ia ch X, . Sau khi ghi xong, gi tri s tu ng c tng ln 1 on
vi, chuyn sang ct tip theo hoc tr v ct u tin, tc 0.
Lp trnh:
RS 1
RW 0
7. YZc )N 5iC0 hiJn !hU
oc d liu t RAM tai ia ch X, . Sau khi oc xong, gi tri s tu ng c tng ln 1 on
vi, chuyn sang ct tip theo hoc tr v ct u tin, tc 0.
Lp trnh:
RS 1
RW 1

14.2 XP@ 3Z'? ch%L'? t"0'h
14.2.1 *h+i !o g$a-hic L84
u trnh khi tao c thuc hin nh sau:
Khi tao cc chn lin kt vi glcd(thit lp input/output).
Chon chip iu khin th nht.
Thit lp chn RS ch ghi lnh.
Gi lnh bt mn hnh (0x3F).
Gi lnh thit lp ia ch (0x40 ).
Gi lnh thit lp ia ch X (ia ch trang) (0xB8 X).
Gi lnh chon dng no trong RAM hin thi ln.
Lm tong t bc th 2 cho chip th 2.
Tong ng vi tng lnh trn trong chong trnh nh sau:
Code:
106

glcd_write_byte(GLCD_ON_DISPLAY);
glcd_write_byte(GLCD_SET_Y_ADDR);
glcd_write_byte(GLCD_SET_PAGE);
glcd_write_byte(GLCD_START_LINE);
Vi cc tham s truyn vo c gi tri nh sau:
Code:
#define GLCD_ON_DISPLAY 0x3F // DB0: turn display on
#define GLCD_START_LINE 0xC0 // 11XXXXXX: set lcd start line
#define GLCD_SET_PAGE 0xB8 // 10111XXX: set lcd page (X) address
#define GLCD_SET_Y_ADDR 0x40 // 01YYYYYY: set lcd Y address

14.2.2 9hi )N 5i>0 5>n 9L84
Hm ghi d liu(mt byte) c th vit nh sau:
Code:
GLCD_CTRL_PORTbits.GLCD_CTRL_RW = 0;// ch ghi
GLCD_DATA_PORT = abyte; // ghi d liu
GLCD_CTRL_PORTbits.GLCD_CTRL_E = 1; // sau khi ghi bt chn EN ln 1
cho php tn hiu
_nop();_nop();_nop();
GLCD_CTRL_PORTbits.GLCD_CTRL_E = 0;// cho chn EN xung 0 li chun b
cho ln thit lp tip theo
_nop();_nop();_nop();
Chi tit cu th v qu trnh xut d liu ln GLCD cc ban c th tham kho chong trnh mu
km theo.
14.3 Do['o23
Code mu

107

Bi 1W : Gi2o ti9p HD C2"3 $d'? HPI
17.1 Gii thiu tf'? 5u2' )S H3c2"3
15.1.1 GS 5hc vI G4 ca$)

Hnh 18 18.1 Cc loai SD Card
Secure Digital (SD) Card l b nh flash tch hp cao vi kh nng truy xut tun tu v ngu
nhin. Vi tc truyn nhn d liu nhanh v n inh, kch thc nh gon, kh nng lu tr
cao t 4MB n 2GB, SD thch hp cho cc thit bi ky thut s cm tay nh my nghe nhac,
in thoai di ng, PDA, my quay phim, chup nh.
15.1.2 GS <T 'hii cda G4 ca$)

Hnh 18 18.2 So khi ca SD Card
108

15.1.3 GS <T chcn

17.1.4 C#c th2'h ?hi $(' t"o'?

15.1.5 8h0jn giao !i\- vi G4 ca$)
SD Card h tr 2 ch giao tip l ch SD Card v SPI. Host (h thng ch - vi iu
khin) c th chon mt trong hai ch ny thuc hin giao tip vi SD Card. Ch SD
Card h tr 2 ch con l 1-bit v 4-bit, tc truyn d liu nhanh. Ch SPI tuy c tc
thp hon nhng d s dung v c h tr trong hu ht cc h thng vi iu khin.
Trong ti liu ny, chng ta s s dung SPI giao tip vi SD Card.

17.2 Gii thiu )S IA,
15.2.1 Teng @0an g7T
FAT (File Allocation Table Bng cp pht tp tin) l kin trc h thng tp tin c s dung
cho my tnh v hu ht cc loai th nh. c pht trin bi Microsoft t nm 1976.

FAT qun l b nh bng cch chia nh b nh (sector, cluster) v nh du cc khi nh
bng cc bit ia ch. Mt sector cha 512 byte b nh. Mt cluster cha nhiu sector. S sector
109

trong mt cluster l c inh v do ngi dng chon lc inh dang b nh.

ch mc inh mt cluster cha 8 sector. Khi lu tr mt file, FAT cp pht mt hoc
nhiu cluster c tng kch thc khng nh hon kch thc file . V du file c kch thc 5kB
s c cp pht 2 cluster (8 sector/cluster) lu tr. Nu s sector trong mi cluster cng
ln s gy nhiu lng ph b nh, ngc lai nu s ny cng nh th h thng hoat ng cng
chm.

Cc phin bn FAT l FAT12, FAT16, FAT32. im khc nhau co bn gia cc phin bn l v
gii han qun l b nh. FAT12 dng 12 bit nh du ia ch cc cluster, nn c th qun l
gn 212 cluster (tr mt s ia ch nh du cc vng c bit). Tong tu FAT16 dng 16
bit, FAT32 dng 28 bit nh du ia ch.
15.2.2 8;0 !$kc -hcn vlng g7T
Mt h thng file FAT gm 4 phn:
1. Reserved sectors: Nm vi tr u tin (sector 0) l Boot sector (tn y l Partition
Boot Record). Sector ny cha mt vng goi l BIOS Parameter Block (vi mt s thng
tin ca h thng file, chi tit v kiu file, v con tr ti cc phn khc) v thng cha
boot loader code ca h iu hnh. Tng s Reverved sector cng c lu trong mt
trng ca Boot sector. Nhng thng tin quan trong ca Boot sector mt cu trc goi l
Drive Parameter Block trong DOC v OS/2. Ring FAT32 c thm mt File System
Information Sector (sector 1) v mt Backup Boot Sector (sector 6).
2. FAT Region: Gm hai bng, l bn ca vng Data Region, cho bit nhng cluster no
c dng.
3. Root Directory Region: y l Directory Table, cha thng tin v file v th muc trong
th muc gc (root directory), ch c trn FAT12 v FAT16.
4. Data Region: y l noi thuc su file v th muc c lu tr v chim hu ht dung
lng ca phn vng a. FAT32 ly cluster u tin ca Data Region lm Root
Directory Table.
15.2.3 Bmng c;- -hE! !,- !in
Phn vng b nh c chia nh thnh nhng phn nh k nhau, c kch thc bng nhau goi
l cluster. Kch thc ca cluster thng t 2kB n 32kB, phu thuc vo kiu FAT, kch thc
phn vng b nh v lua chon ca ngi dng. Mi file chim mt hoc nhiu cluster ty thuc
vo kch thc ca file nh vy, mt file c cha bi mt dy cc cluster tao thnh mt
danh sch lin kt. Cc cluster ca mt file khng nht thit phi lin k nhau, iu ny
thng gy ra tnh trang phn mnh (fragmented).
Bng cp pht tp tin FAT l mt danh sch cc muc (entry) v nn bn ca tng cluster
trn phn vng a. Mi entry cha cc thng tin:
s ca cluster tip theo trong dy cc cluster
entry nh kt thc ca dy cluster (end of clusterchain EOC)
entry c bit nh du mt cluster li (bad cluster)
entry c bit nh du cluster khng dng
c zero nh du cluster cha dng
Kch thc FAT entry khc nhau mi phin bn. FAT12 v FAT16 dng 12 v 16 bit cho mi
entry. Trong FAT32, mi entry l 32 bit, nhng thuc su ch dng 28 bit, 4 bit cao du tr (khng
dng, thng l 0).
15.2.4 4i$#c!o$( !aR5#
110

Mi file/directory (cng hiu l mt folder) khi lu tr c biu thi l mt entry 32-byte trong
bng Directory Table. Mi entry ghi: tn, thuc tnh (attributes: archive, directory, hidden,
read-only, system and volume), ngy tao lp, ia ch ca cluster d liu u tin, v kch
thc ca file/directory. Tt c cc Directory Table u c cha trong vng Data Region (tr
FAT12 v FAT16, Root Directory Table chim mt vng ring goi l vng Root Directory
Region). M t mt Directory entry (c Root Directory v subdirectory):

17.3 Gii thiu $> th% )i' MDD
SD card giao tip thng qua SPI, chng ta c th lm tt c cc bc t cu hnh SPI cho PIC,
sau gi lnh t vi iu khin xung SD card ri ch tn hiu tr v, oc master boot record,
boot sector, oc ghi FAT .Vi cch lm ny i hi ban tn nhiu thi gian hon xy dung
cc hm API giao tip vi SDcard nhng ban s nm c nhiu kin thc hon v SDcard.
Ngoi ra cn mt cch khc na lm l s dung th vin cc hm c sn trn mang s
dung nh vy chng ta s tn t thi gian hon cho vic vit cc hm giao tip th nh v tp
trung hon vo xy dung ng dung s dung SD card.
MDD l th vin cha cc hm v thit lp giao tip vi SD card,nm trong b th vin y
h tr cc chc nng gm SD card, mTouch, GraphicLCD, USB, audio. do Microchip cung
cp v c t tn l Microchip solutions. y chng ti tp trung vo cch s dung th
vin MDD vo giao tip vi SD card bng SPI.
15.3.1 Hng )nn %` )Fng M44
y l mt b th vin ca Microchip cung cp c th chay trn cc dng PIC 8 bit (PIC18F),
PIC 16bit (PIC24F, PIC24H, dsPIC30) v PIC 32bit (dsPIC33) nn th vin cng kh ln, i
hi b chong trnh ca vi iu khin s dung cng phi nhiu, cu th nu s dung th vin v
ch c th oc file t SDcard th cn gn 22000 bytes b nh chong trnh lu tr(ch tnh
khng gian lu tr cho code chong trnh ng dung tu vit) v s dung ton b chc nng
ca th vin (c th oc ghi file, format th nh, tm kim file, tao xa qun l th muc, s
dung cc hm m rng pgm, s dung c hm Fsfprintf, h tr th nh inh dang FAT32) th
cn gn 35000 bytes b nh chong trnh. l thng tin do Microchip cung cp nhng thuc
th s dung th vi vi iu khin ch c 32KB b nh chong trnh th hon ton khng th s
dung c b th vin(tr ch ch oc file) m vi iu khin PIC18F4520 ch c 32KB b
nh chong trnh nn chng ti chon mt chip khc cng dng vi vi iu khin l vi iu
khin PIC18F4620 vi b nh chong trnh l 64KB, nhng vn cn mt vi chc nng phu m
chng ti b khng s dung thu gon chong trnh sau khi bin dich, nn nu ban mun
s dung ton b chc nng ca th vin th nn chon vi iu khin c b nh chong trnh
96KB tr ln.
111

Hnh 18-3 Chi tit s dung b nh chong trnh cho th vin MDD

Hnh 18-4 Cc tnh nng c lua chon ca th vin

Mun b bt chc nng no ca th vin chng ta cn phi tm v kha tt c cc dng code
define cho tnh nng (vd ifdef ALLOWS_DIRS . endif).
Bc 1: Tao 1 project mi, sau vo trang ca Microchip download xung th vin Microchip
Solutions(hoc c sn trong a CD km theo) , trong bao gm lun c th vin MDD. Vo
th muc Microchip Solutions chp th muc MDD File System v th muc Microchip vo th
muc cha project. Sau vo th muc MDD File System xa ht nhng file khng cn thit tr
th muc PIC18F, tong tu trong th muc Microchip chng ta ch lai th muc PIC18 salloc v
th muc Include, trong th muc Include chng ta cng xa ht v ch lai nhng file .h
trong th muc ny v th muc PIC18 salloc,MDD File System. Tip theo chng ta include
nhng file sau vo project vi ng dn ./ l th muc m cha project.
.\Microchip\MDD File System\FSIO.c
.\Microchip\MDD File System\SD-SPI.c
.\Microchip\PIC18 salloc\salloc.c
.\MDD File System-SD Card\PIC18F\Fsconfig.h
.\MDD File System-SD Card\PIC18F\HardwareProfile.h
.\Microchip\Include\MDD File System\FSIO.h
.\Microchip\Include\MDD File System\SD-SPI.h
.\Microchip\Include\MDD File System\FSDefs.h
112

.\Microchip\Include\PIC18 salloc\salloc.h
.\Microchip\Include\Compiler.h
.\Microchip\Include\GenericTypeDefs.h

Hnh 18-5 Project sau khi thm cc file header
File tmp.c l file cha hm main do chng ta tu vit.
Sau vo tab Project Build Options Project, chon Include Search Path, chon New sau
thm vo cc ng dn nh trn.
113

Hnh 18-6 Thm ng dn cho project

Bc 2: Thit lp buffer oc v ghi, buffer cho FAT
M file linker tong ng vi vi iu khin PIC ang s dung( y l file 18f4620.lkr ), ri
chnh sa lai vi ni dung nh sau
114

Hnh 18-7 Chnh sa file linker cho project

Bc 3: Thit lp b nh cache v xung clock
Thi\! 5,- R nh cach#
Trong file Fsconfig.h cu hnh sn b nh cache s dung l 512bytes thng qua cu lnh
inh ngha
Code:
#define MEDIA_SECTOR_SIZE 512

Nu ban mun thay i b nh ca cache th ch cn chnh sa trong cu lnh ny nhng nh
l b nh cache l bi s ca 512.Ngoi ra cn mt s thit lp chc nng khc nh bt/tt
chc nng ghi, tm file. u c trong file FSconfig.h cc ban c th tu oc tm hiu thm.
Thi\! 5,- L0ng c5oc'
cu hnh xung clock ban m file HardwareProfile.h tm n dng lnh define sau
Code:
#define GetSystemClock() 20000000 // System clock frequency (Hz)
y vi iu khin ang c cu hnh s dung xung tn s 20MHz, v ty vo nhu cu s
dung cc ban c th thay i con s ny.
115

Bc 4: Thit lp cc chn giao tip v cc thanh ghi ca ch SPI
Trong th vin ny ca Microchip ch h tr cho mt s con PIC18F (PIC18F8750,
PIC18F8722, PIC18F4650), ton b PIC24F,PIC32F v dsPIC.Cho nn s dung cho nhng
con PIC khc(v du l PIC18F4620) th cn phi chnh sa thm mt s file sau.
Trong file HardwareProfile.h ban thm vo trong muc define dnh cho PIC18F nhng dng
inh ngha sau
Code:

116

#elif defined PIC18F4520_PIM
#define USE_PIC18
#define USE_SD_INTERFACE_WITH_SPI

#define INPUT_PIN 1
#define OUTPUT_PIN 0
#define USE_SD_INTERFACE_WITH_SPI

#define TRIS_CARD_DETECT TRISBbits.TRISB4 // Input
#define CARD_DETECT PORTBbits.RB4

#define TRIS_WRITE_DETECT TRISDbits.TRISD7 // Input
#define WRITE_DETECT PORTDbits.RD7

// Chip Select Signal
#define SD_CS PORTAbits.RA5
#define SD_CS_TRIS TRISAbits.TRISA5

// Card detect signal
#define SD_CD PORTBbits.RB4
#define SD_CD_TRIS TRISBbits.TRISB4

// Write protect signal
#define SD_WE PORTDbits.RD7
#define SD_WE_TRIS TRISDbits.TRISD7

// TRIS pins for the SCK/SDI/SDO lines
#define SPICLOCK TRISCbits.TRISC3
#define SPIIN TRISCbits.TRISC4
#define SPIOUT TRISCbits.TRISC5

// Latch pins for SCK/SDI/SDO lines
#define SPICLOCKLAT LATCbits.LATC3
#define SPIINLAT LATCbits.LATC4
#define SPIOUTLAT LATCbits.LATC5

// Port pins for SCK/SDI/SDO lines
#define SPICLOCKPORT PORTCbits.RC3
#define SPIINPORT PORTCbits.RC4
#define SPIOUTPORT PORTCbits.RC5

// Registers for the SPI module you want to use
#define SPICON1 SSPCON1
#define SPISTAT SSPSTAT
#define SPIBUF SSPBUF
#define SPISTAT_RBF SSPSTATbits.BF
#define SPICON1bits SSPCON1bits
#define SPISTATbits SSPSTATbits

#define SPI_INTERRUPT_FLAG PIR1bits.SSPIF
#define SPIENABLE SSPCON1bits.SSPEN

// Will generate an error if the clock speed is too low to interface
to the card
#if (GetSystemClock() < 400000)
#error System clock speed must exceed 400 kHz
#endif
V trc ban cn phi inh ngha cc nhn PIC18F4520_PIM bng cch phn inh ngha
nhn cho cc con PIC khc ban thm vo oan code sau
Code:

117

#elif defined(__18F4620)
#define DEMO_BOARD PIC18F4620_PIM
#define PIC18F4620_PIM

Bc 5: Cu hnh b nh
Trong MPLAB IDE, chon Project Build Options Project, chon th MPLAB C18 ri chon
Memory Model trong Categories v thit lp nh sau:
Code model : Small code model
Data model : Large code model
Stack model : Multibank model

Hnh 18-8 Cu hnh Memory Model
Cc bc thit lp s dung hon tt, by gi cc ban c th tao 1 file source ca mnh
v s dung cc hm c sn trong th vin giao tip vi SDcard.
118

Hnh 18-9 Chong trnh mu
15.3.2 8Ec h !$ong !h viCn
gGHni! Initializes the card,loads the master boot record(partition information),loads the
boot sector and updates the parameters passed into it with its information
gGoc5o%# Updates the file information, writes the remaining entry in and frees the RAM
from the heap that was used to hold the information about the file.This also updates
the time-stamp information for thr file.
gGo#oo Verifies if the end of the file has been reached
gGoo-#n Allocates space in the heap for file information.If the file being opened already
exist, Fsfopen can open it so that the data would be appended at the end of the line,
erase it and create a new file qith the same name to be written to,or simply open it for
reading.If the file does nont exist, Fsfopen can creat it. This function then returns a
pointer to the tructure in the heap that contains information for this file
gGo$#a) Reads information from an open file to a buffer. The number of bytes written
can be specified by its parameters. If Fsfread is called consecutively on the same open
file, the read will continue from the place it stopped after the previous read. This
function returns the number of data objects read
g%o%##' Changes the position in a file. When a user calls FSfseek, they specify the base
address to set, which can either be at the beginning or end of the file, or at the current
position in the file.
The user also specifies an offset to add to the base (note that if the base address is at
the end of the file, the offset will be subtracted). Hence, if FSfseek is called with the
base set to the beginning of the file and a specified offset of 0, the position would be
changed to the first byte of the file.
g%o!#55 Returns the current position in the file. The first position in the file is the first
byte in the first sector of the first cluster, which has the value 0. Hence, if a file was
119

created and 2000 bytes were written to it, FSftell would return the number 1999 if it
was called.
g%oQ$i!# Writes information from a buffer to an open file. The algorithm it uses reads a
sector from the data region of the disk to SRAM, modifies the relevant bytes and then
writes the sector back to the disk. Because each FSfwrite call reads the data first, the
ability to open multiple files at a time is supported. This also means that writing data in
larger blocks takes less time than writing the same data in smaller blocks as fewer
sector reads and writes will be needed.
g%$#ov# Searches for a file based on a filename parameter passed into it. If the file
is found, its directory entry is marked as deleted and its FAT entry is erased.
g%$#ov#-g Deletes the file identified by a given filename. If the file is opened with
FSfopen, it must be closed before calling FSremovepgm. The filename must be specified
in ROM. This function is necessary only on the PIC18 architecture.
g%oo-#n-g Opens a file on the SD card and associates an FSFILE structure (stream)
with it using arguments specified in ROM. This function is necessary only on the PIC18
architecture.
gG$#na# Changes the name of a file or directory. If the pointer passed into this
function is NULL, the name of the current working directory will be changed.
g%$#Qin) Resets the position of the file to the beginning of the file.
g%')i$ Creates a new subdirectory in the current working directory.
g%ch)i$ Changes the current working directory to the one specified by the user.
gG$)i$ Deletes the specified directory. The user may also choose to specify whether
subdirectories and files contained within the deleted directory are removed. If the user
does not permit the function to delete subdirectories, it fails if the user attempts to
delete a non-empty directory.
g%g#!cQ) Returns the name of the current working directory to the user.
gin)gi$%! Locates files in the current working directory that meet the name and
attribute criteria. A SearchRec Structure Pointer will be passed into the function. Once a
file is located, the file-name, file size, create time and date stamp, and attributes fields
in the SearchRec structure will be updated with the correct file information.
gin)gi$%!-g Operates in the same manner as the FindFirst function, except the name
criteria for the file to be found will be passed into the function in ROM. This function is
necessary only on the PIC18 architecture.
Ii'3G!Bt Locates the next file in the current working directory that matches the
criteria specified in the last call of FindFirst or FindFirstpgm. It will then update the
SearchRec structure provided by the user with the file information.
g%oo$a! Erases the root directory and file allocation table of a card. The user may
also call the function in a mode that causes it to create a new boot sector based on the
information in the master boot record.
g%o-$in!o Writes a formatted string to a file. It automatically replaces any format
specifiers in the string with dynamic values from variables passed into the function.
Integer promotion must be enabled in the build options menu when using this function
with the PIC18 architecture.
G#!85oc'pa$% Used in user-defined Clock mode to manually set the current date and
time. This date and time would be applied to files as they are created or modified.

17.4 XP@ 3Z'? ch%L'? t"0'h
15.4.1 *\! nii -hPn cang

Hnh 18-10 So kt ni Sdcard
V SDcard hoat ng in p 3V3 m tn hiu ra ca vi iu khin l 5V nn cc chn
SDI,SDO,SS,SCK c gn thng qua cc in tr chia p xung 3V3 cho ph hp vi giao
tip SDcard.
120

15.4.2 8hSng !$Knh n0
Code:
1 #include <p18f4520.h>
2 #include <FSIO.H>
3 void blocking(void)
4 {
5 while (1);
6 }
7 void main(void)
8 {
9 FSFILE *file1;
10 unsigned char txt[] = "Giao tiep SDcard!!";
11 while (!MDD_MediaDetect());
12 while(!FSInit());
13 file1 = FSfopenpgm("file_test_1.txt","w+");
14 if (file1 == NULL)
15 blocking();
16 if (FSfwrite((void*)txt,1,18,file1) != 18)
17 blocking();
18 if (FSfclose(file1) != 0)
19 blocking();
20 while (1);
21 }
9imi !h.ch cEc 5Cnh&
Dng 2: include file header chnh ca th vin.
Dng 36: tao hm blocking h thng nu c li.
Dng 9: khai bo con tr s tr n file cn x l.
Dng 10: khai bo chui s c ghi vo file.
Dng 11: i tn hiu bo c th nh thng qua chn card dectec.
Dng 12: khi tao th nh bt u giao tip vi th nh.
Dng 13: khi tao cho file, t tn file , truyn vo i s cho php ghi ln file.
Dng 1415: kim tra c khi tao c file hay khng.
Dng 1617: ghi chui vo file.
Dng 1819: ng file
121

Hnh 18-11 Kt qu ca chong trnh
17.7 Do['o23
Code mu

(Codientu - Org) PIC18

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