Apr i l 1 9 9 6

4-85

1996Actel Corporation



4

Using FPGAs for
Digit al PLL Applicat ions

In addit ion t o pur ely digit al applicat ions, many designs use
Field Pr ogr ammable Gat e Ar r ays ( FPGAs) for DSP. Well
examine one such applicat ion, digit al PLLs, t o show var ious
ways of implement ing PLL designs using FPGAs.

Pul s e S t e a l PL L

In t elecommunicat ions applicat ions, it is oft en desir able t o
gener at e a digit al signal t hat is locked t o an incoming signal
and is some mult iple of it s fr equency. A dr awing of a pulse
st eal PLL, which is a simple way t o gener at e such a signal, is
shown in Figur e 1. Not e t hat t he design cont ains an or dinar y
oscillat or but no VCO. Except for t he cr yst al, t he ent ir e design
will oper at e in an FPGA.
Not e t he fr equency r elat ionship t hat holds at point s A and B
in t he figur e, wher e
OSC/( K*M) = Input /N = Compar ison Fr equency ( 1)
The t echnique is based on select ing a r efer ence oscillat or
fr equency slight ly higher t han OSC. This fr equency ( OSC+ )
should be chosen so t hat
1/Compar ison Fr eq. ( K*M) /( OSC+ ) = .5 * ( 1/OSC) ( 2)
The r ight side of equat ion 2 equals one-half t he per iod of t he
r efer ence oscillat or .
The r efer ence oscillat or fr equency delt a will cause point B
( t he det ect or flip-flop D input ) t o begin t o pr ecede point A
( t he det ect or flip-flop clock input ) by half a per iod. When t he
edge of t he D input is sufficient , t he det ect or will clock t r ue
and begin a pulse t r ain t hr ough t he t wo deglit ching flip-flops.
The out put of t he second of t hese clear s all t hr ee flip-flops
and st eals a pulse by disabling t he divide by K out put .
St ealing t he pulse put s point B behind A unt il t he r efer ence
oscillat or delt a can move it ahead by one per iod, r epeat ing
t he cycle. Point s A and B ar e always wit hin one-half a cycle of
each ot her .
The cir cuit allows t he fr equency of t he out put signal t o be
select ed simply by adjust ing t he values of t he divider s K and
M. The lock r ange of t he loop is given by t he following:
Lock Range =

( OSC+ /osc) /Input ( 3)

J i t t e r -B o un de d Di g i t a l PL L

Anot her t echnique

1

for gener at ing a wide var iet y of
synchr onized clock fr equencies wit h low jit t er employs an
accumulat or Digit al Cont r olled Oscillat or ( DCO) and phase
and fr equency compar at or s. The syst em, shown in Figur e 2,
can lock t o any division of a r efer ence fr equency ( F r ef.) as
select ed by t he dat a loaded int o fr equency divider count er s.
The Successive Approximation Register ( SAR) and its controller
serve as a low-pass filter supplying the DCO with frequency and
phase correction data. Among the three inputs to the SAR
controller is the F ref. divided by a factor Q to form F q.
The ot her t wo input s come fr om t he phase and fr equency
( zer o) compar at or s. The fr equency compar at or out put is t he
DCO fr equency divided by P t o for m F p. When t he syst em is
in lock, t he following equat ion is t r ue:
F dco = ( P/Q) * F r ef. ( 4)
The hear t of t he syst em is t he accumulat or DCO, which
det er mines t he abilit y t o lock t o a fr equency and t he amount
of jit t er allowed. The DCO consist s of a four -bit accumulat or
whose input is fed by t he SAR. The DCO input value is
det er mined fr om t he phase and fr equency compar ison
feedback loops. The most significant bit of t he accumulat or
out put is t he DCO out put signal. It is gener at ed by
successively adding t he SAR value t o it self at t he
high-fr equency syst em clock r at e. The fr equency compar at or
uses t he value of P t o divide t he DCO fr equency. If t he
fr equency is out of lock dur ing a per iod of F r ef., t he
compar at or asser t s gr eat er -t han-zer o or less-t han-zer o t o t he
SAR cont r oller t o modify t he value of t he r egist er . If t he P
count er out put is zer o, t he DCO has t he cor r ect fr equency.
The DCO lat ch act s as a phase regist er indicat ing t he phase of
t he DCO wit h respect t o F ref. The DCO phase is calculat ed by
t he N most significant accumulat or out put bit s. When t he DCO
is out of phase, t he jit t er, or phase difference, is det ect ed by t he
phase comparat or and accumulat es wit h t ime unt il it equals
one period. The feedback loops t hen cause t he SAR regist er
cont roller t o load a correct ing value int o t he regist er or t o clear
t he accumulat or wit h a synchronizing pulse.
The J it t er -Bounded DPLL may be implement ed ent ir ely on an
Act el FPGA. The r esour ce r equir ement s var y wit h t he
r elat ionships of t he syst em input and out put fr equencies, but
for any F r ef., syst em clock, and desir ed out put fr equency, t he
design is easily accommodat ed on an Act el FPGA.

References:

1. S. Walt er s and T. Tr oudet , Digit al Phase-Locked Loop
wit h J it t er Bounded,

IEEE Transactions on Circuits
and Systems

, Vol 36, No. 7, J uly 1989.
Application Note AC117

4-86

Figure 1

PulseSteal PLL
D
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4-87
Us i n g F PGAs f o r Di g i t a l PL L Appl i c a t i o n s

4

Figure 2

J itter-Bounded Digital PLL
B

[
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4-88