FPGA

Mehdi_borjkhani@yahoo.com

:
FPGA .

) TTL
( CMES
.

-
NOT , OR , AND
. )
( ...


... . NAND , NOT , OR , AND


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. . .

. FPGA
.


. .
- :

FPGA CPLD FPLD FPLD .

.
device
. download FPLD
FPLD . FPLD
.
- FPLD :
device PLA ) ( programmable logic Array
. PLA AND OR inverter
. PLA
AND
. AND
.
AND OR .
OR
.
) ( PAL .
PLA PAL
. FPGA
LUT CLB
. CLB
) (PSM ) ( programmable switch matrices .
FPGA I/O PSM CLB
. CLB
. PSM
CLB
FPGA IC
.
. .
FPGA PSM

.


.
.

. device
device

.
device

 .

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device .
.
IC
- :

XILINX Foundation
.
Foundation :
-
ABEL ) HDL ( VHDL
.
.
- ) (

.
HDL
.

XC9500/XC4000

HDL

CPLD
FPGA

Download
XS40 XS95

PC LED segment

 :
XC9500 CPLD : XC4000 FPGA

Foundation

XILINX

- Foundation

FPLD . device

XC95108 . 5XL XC400 device XC9500

CPLD XC4000 FPGA
. CLB
PSM .

FOUNDATION

-

mapping FPLD .
-
XS95 XS40
) ( Debugging .
- ) XS40 ( :
:
Input 0
Carry input
Sum output
Carry output
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
1
0
1
1
0
0
1
1
1
1
1

Input 1
0
0
0
0
1
1
1
1

ADDL 40
XC4005XL .
A . A
.
ADDL SCH .
netlist Options - create netlist
Options - Export Netlist EDIF 200 ) .
Options Integrity test
( . Flow tab project
manager .
Signal Add Signals
waveform viewer . signal Add stimulators..
) BC0 , BC1 , BC2
toolbar Logic
SIMULATOR
( .
. B

) scrollbar waveform viewer

( .

.

 ) (
XC05xl FPGA .

I/O XX4005CL . HDL
ADDL 40 . UCF

;LOC= P46
;LOC=P45
;LOC=P44
;LOC=P25
;LOC=P26

INPUT 1
INPUT 0
CARRY - INPUT
SUM
CARRY - OUTPUT

NET
NET
NET
NET
NET

.
IMPLEMMENT Design . Option
. Option User Constraints UCF
.

) . C:\XCPROJ\ADDL 40\ADDL - 40 . UCF Browse

UCF ( . OK
implement Design RUN
ADDL 40 . BIT download , XS40 .
1 XC4005XL FPGA

2

Foundation
. reports tab ,
implementation
project manager implementation report files
. report browser
.
.
.
:
-

nelist
foundation implementation
.
UCF

.
.
-
netlist
.

.
.
AND ) (GND
LOW .


LUT CLB FPGA .
-

.

.
.

XC4005XL
.
: device

4%used
8% bonded
0% used
4% used
0% used

5/112
5/61
1/961
5/112
1/196

IO

LOGIC
IBO
CLB

.
( IOB`s` ) I/O XC4005XI FPGA
.

IOB
PLCC .
% I/O

.
SUM CARRY OUTPUT
. 4LUT
LUT .
CLB 4LUT CLB
.
- PAD

.
I/O .

Pin number
P44
P25
P45
P46
P25

Comp name
CARRY-INPUT
CARRY-OUTPUT
INPUTO
INPUT
SUM

UCF .
)
Physical File Constraint ( PCF .
;`COMP ` CARRY-INPU`T LOCATE = SITE `P44
;`COMP `CARRY-OUTPUT`LOCATE = SITE `P26
;`COMP `INPUT1`LOCATE = SITE `P45
;` COMP `INPUT `LOCATE = SITE `P46
;` COMP `SUM ` LOCATE = SITE ` P25

 PCF SYNTAX UCF .

Foundation implementation RUN
FUC . %

.
.

-

.
Layout
-

.
50MHZ )

20 ns (
20ns .

- bit

.
.
.
XC4005XL
.
XC4005CL PIN
44
45
46
47
48
49
32
34

ADDER TERMINAL
CARRY-INPUT
INPUTO
INPUT1
******NOT Used
******NOT Used
******NOT Used
******NOT Used
******NOT Used

25
add1 40 . UCF carry out
. 25 SO 7 Segment
26 XC4005XL FPGA
26 S1 device .
download

.

FPGA CPLD . XC40 XS95
.
FPLD .
XC4005XL FPGA
XC95108 CPLD
XILINX F1
.
download .

 . seven -segment
download
FPLD
RAM 32KB FPLD
.

.

-
FPGA
.

.
-

1. Van Den Bout, Prentice Hall, (February 1998), The Practical Xilinx Designer Lab
Bookpp.50-70,pp.90-120,pp.270-290
2. http://www.chipcenter.com/pld/products_001-500/pldp496.htm
3. http://www.fpga-faq.com/archives/authors_u.html
4. http://www.xilinx-china.com/xlnx/xil_prodcat_product.jsp?title=ss_vir
5. http://www.cic.edu.tw/research/Xilinx/xupmirror/XESS/ho04000.html
6. http://www.dacya.ucm.es/horten/dci/manualXs401.3.pdf