1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity and_dos is
port( a : in std_logic;
b : in std_logic;
q : out std_logic);
end and_dos;

architecture arreglo of and_dos is
begin

q <= (a and b);

end arreglo;

2
######################################
## User constraint file
######################################

net a loc=" P13" ; # Pulsador PB3.
net b loc=" P30" ; #Pulsador PB2.
net q loc=" P44" ; #Led D5.