Drawing CMOS Layout For IC DesignCrestopher Saint

CMOS 1
Drawing CMOS Layout for IC Design

Beginning Level
DTT6530
CMOS 1 Drawing CMOS Layout for IC Design Beginning
Level
January 1996
Technical Publications and Training
Design Technology
Published by Technical Publications and Training, Intel Corporation
Copyright Intel Corporation 1996
Document requests: http://ats.intel.com/Docs/
Technical information: Phil Sandoval, 356-6348, FM5-43, psandova@pcocd2
Document comments: Mary Sullivan, 765-5576, RN4-43, msulliv@scdt
Published by Technical Publications and Training, Intel Corporation
Copyright Intel Corporation 1996
Document requests: http://ats.intel.com/Docs/
Technical information: Phil Sandoval, 356-6348, FM5-43, psandova@pcocd2
Document comments: Mary Sullivan, 765-5576, RN4-43, msulliv@scdt
CMOS 1
Intel Confidential i
0Table of Contents
Chapter 1: Introduction to the Course
Introduction to the Course.................................................................................. 1-2
Chapter 2: Introduction to CMOS 1 Drawing CMOS Layout for
IC Design Beginning Level
Chapter Overview .............................................................................................. 2-2
What is an IC?.................................................................................................... 2-3
How Is an IC Designed? .................................................................................... 2-4
Basic Layout Design Tasks................................................................................ 2-5
What Are the Design Data Representations? .................................................... 2-6
Chapter 3: How to Interpret Logic-level Schematics
Lesson 3-1: How to Identify the Parts of a Logic-level Schematic
Lesson Overview................................................................................................ 3-4
What Is a Logic-level Schematic?...................................................................... 3-5
Lab 3-1.a: Identify the Nodes of the Logic-level Schematic ............................... 3-6
Logic Symbols of the Basic Logic Functions...................................................... 3-8
Lab 3-1.b: Identify the Logic Symbols of the Logic-level Schematic .................. 3-9
Logic-level Schematic Drawing Conventions ................................................... 3-10
Lab 3-1.c: Identify the Parts of the Logic-level Schematic ............................... 3-12
CMOS 1
ii Intel Confidential
Lesson 3-2: How to Describe the Function of a Logic Symbol
Lesson Overview.............................................................................................. 3-14
What Are the Standard Logic Functions? ........................................................ 3-15
Practice 3-2.a: Evaluate Boolean Algebra Equations ...................................... 3-18
What Are Truth Tables?................................................................................... 3-19
How Is the Number of Rows for a Truth Table Determined? ........................... 3-20
Practice 3-2.b: Determine the Number of Columns and
Rows for a Truth Table..................................................................................... 3-21
How Are Input Values for a Truth Table Filled In? ........................................... 3-23
Practice 3-2.c: Fill in the Input Values for a Truth Table .................................. 3-26
Output Values of the Truth Tables ................................................................... 3-27
Practice 3-2.d: Describe Logic Functions with Truth Tables ............................ 3-29
Chapter Summary ............................................................................................ 3-36
Chapter 4: How to Convert a Logic-level Schematic to a
Transistor-level Schematic
Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic
Lesson Overview................................................................................................ 4-4
What Is a Transistor-level Schematic?............................................................... 4-5
What Is a Transistor?......................................................................................... 4-6
Nodes of a Transistor-level Schematic .............................................................. 4-9
Transistor Representations of the Logic-level Schematics .............................. 4-10
Lab 4-1: Identify the Parts of Transistor-level Schematics............................... 4-12
Lesson 4-2: How to Verify the Transistor-level Function of a Logic
Symbol
Lesson Overview.............................................................................................. 4-17
Values that Turn a Transistor On or Off ........................................................... 4-18
How Are Truth Table Values Verified?............................................................. 4-19
Practice 4-2: Verify the Transistor-level Function of the Logic Symbols .......... 4-22
CMOS 1
Intel Confidential iii
Lesson 4-3: How to Convert a Logic-level Schematic to a
Lesson Overview.............................................................................................. 4-28
Logic Functions Defined with Transistors ........................................................ 4-29
How Is a Logic-level Schematic Converted to a Transistor-level Schematic? . 4-30
Practice 4-3: Convert a Logic-level Schematic to a Transistor-level
Schematic ........................................................................................................ 4-32
What is Complex Logic? .................................................................................. 4-33
Order of the Series Transistors ........................................................................ 4-34
How Is a Complex Logic-level Schematic Converted to N-Type Transistors?. 4-35
Lab 4-3.a: Convert Complex Logic-level Schematics to N-Type Transistors... 4-38
How Is a Complex Logic-level Schematic Converted to P-Type Transistors? . 4-40
Lab 4-3.b: Convert Complex Logic-level Schematics to P-Type Transistors ... 4-43
Lab 4-3.c: Convert Complex Logic-level Schematics to Transistor-level
Schematics....................................................................................................... 4-44
Chapter Summary ............................................................................................ 4-45
Chapter 5: How to Create a Layout Drawing from
a Transistor-level Schematic
Lesson 5-1: How to Identify a Transistor on the IC Cross Section
Lesson Overview................................................................................................ 5-4
What Is a Cross Section?................................................................................... 5-5
Layers of the Transistor Cross Section.............................................................. 5-6
Layers of the Die Cross Section......................................................................... 5-7
What Is a Diode?................................................................................................ 5-8
How Is a Transistor Turned On or Off?............................................................ 5-10
Lesson 5-2: How to Identify Process Design Rules on the
Transistor Cross Section
Lesson Overview.............................................................................................. 5-14
What Is a Design Rule? ................................................................................... 5-15
Basic Process Design Rules ............................................................................ 5-16
How Are Process Design Rules Identified on the Transistor Cross Section?.. 5-17
CMOS 1
iv Intel Confidential
Lesson 5-3: How to Convert a Transistor-level Schematic
to a Stick Diagram
Lesson Overview.............................................................................................. 5-20
What Is a Stick Diagram?................................................................................. 5-21
Legend for a Stick Diagram.............................................................................. 5-22
Series and Parallel Transistors in a Stick Diagram.......................................... 5-23
How Is a Stick Diagram Created?.................................................................... 5-24
Lab 5-3.a: Create a Stick Diagram................................................................... 5-26
How Is the Width of a Layout Drawing Estimated from a Stick Diagram? ....... 5-29
Lab 5-3.b: Estimate the Width of a Layout Drawing from a Stick Diagram...... 5-31
Lesson 5-4: How to Get Better Layout Density with Node Sharing
Lesson Overview.............................................................................................. 5-34
What Is Node Sharing?.................................................................................... 5-35
How Is Node Sharing Achieved? ..................................................................... 5-36
Lab 5-4: Use Node Sharing to Increase Density.............................................. 5-38
Lesson 5-5: How to Estimate Area
Lesson Overview.............................................................................................. 5-40
Area Calculation............................................................................................... 5-41
Lab 5-5.a: Calculate Area ................................................................................ 5-42
Units of Measure Conversion........................................................................... 5-43
Lab 5-5.b: Convert Units of Measure ............................................................... 5-44
Average Area per Transistor Calculation ......................................................... 5-46
Lab 5-5.c: Calculate the Average Area per Transistor ..................................... 5-47
Lesson 5-6: How to Calculate Resistance
Lesson Overview.............................................................................................. 5-50
What Is Resistance? ........................................................................................ 5-51
Lab 5-6.a: Calculate Resistance Values .......................................................... 5-53
How Is Sheet Resistance Calculated?............................................................. 5-56
Lab 5-6.b: Calculate Sheet Resistance............................................................ 5-58
CMOS 1
Intel Confidential v
Lesson 5-7: How to Convert a Stick Diagram to a Layout Drawing
Lesson Overview.............................................................................................. 5-60
What Is a Layout Drawing?.............................................................................. 5-61
What Is Transistor Size?.................................................................................. 5-62
How Is a Stick Diagram Converted to a Layout Drawing? ............................... 5-63
Lab 5-7.a: Convert a Stick Diagram to a Layout .............................................. 5-64
Visually Verifying a Layout Drawing................................................................. 5-65
Lab 5-7.b: Visually Verify a Layout Drawing .................................................... 5-66
Lesson 5-8: How to Draw Layout with a Standard Cell Template
Lesson Overview.............................................................................................. 5-68
What Is a Standard Cell Template? ................................................................. 5-69
How Is a Layout Drawing Drawn with a Standard Cell Template?................... 5-70
Lab 5-8: Draw a Layout Drawing with a Standard Cell Template .................... 5-71
Lesson 5-9: How to Draw Layout to Meet Layout Restrictions
Lesson Overview.............................................................................................. 5-74
How Is a Transistor Drawn with Multiple Legs? ............................................... 5-75
How Is a Transistor Drawn with a Bent Gate? ................................................. 5-77
Lab 5-9: Draw Layout to Meet Layout Restrictions .......................................... 5-79
Chapter Summary ............................................................................................ 5-80
Appendix A: Glossary
Terms .................................................................................................................A-2
CMOS 1
vi Intel Confidential
CMOS 1 Chapter 1: Introduction to the Course
Intel Confidential 1-1
01
Chapter 1:
Introduction to the Course
Chapter 1: Introduction to the Course CMOS 1
1-2 Intel Confidential
Introduction to the Course
Introduction The goal of this course is to provide the information and practice
needed to create layout drawings with CMOS technology.
Structure This course is structured around the three main tasks of the basic
layout design process. A chapter is devoted to each task as follows:
G Interpret Logic-Level Schematics
G Convert Logic-Level Schematics to Transistor-Level Schematics
G Create Layout Drawings from Transistor-Level Schematics
Chapters are divided into lessons, the number of lessons depending
on the complexity and scope of the topic being taught. Each lesson
has a practice or lab, which gives hands-on experience.
Objectives Every chapter and lesson has a clearly stated objective so that you
will know exactly what you are expected to learn.
Format The course material is presented in a mapped-page format.
G Information is categorized as follows.
Concept: Provides denitions and examples
Process: Explains how something works
Procedure (practice/lab): Tells how to perform a task
Guidelines: Provide suggestions for performing a task or
tackling a problem
G Margin labels (labels on the left side of the page) provide visual
cues to help increase information access and retrieval time. The
labels refer to the contents of that paragraph or block of
information.
The instructor presents information using foils.
G The foils follow the sequence of the student material but contain
only key points. A page number on the upper left corner of the
foil indicates the corresponding page in your course guide.
CMOS 1 Chapter 1: Introduction to the Course
Introduction to the Course (continued)
Practices and Labs You will be given two types of exercises.
G Practice: Reinforces material for general knowledge building.
G Lab: Reinforces material directly related to a job task.
Acknowledgments Special thanks go to Phil Sandoval, who created the class that this
one is based on. Also, thanks to all who helped with the content of
this class: Brian Cyphert, Mark Drake, Barbara Drummer, Gell
Gellman, Myrna Irwin, Brent Jensen, Mary Kamprath, Lynn Olson,
Manhaz Padash, Phil Sandoval, and Seema Shafajoo.
Chapter 1: Introduction to the Course CMOS 1
CMOS 1 Chapter 2: Introduction to CMOS 1
11
Chapter 2:
Introduction to CMOS 1
Chapter 2: Introduction to CMOS 1 CMOS 1
Chapter Overview
Introduction This class covers the major job tasks for creating basic CMOS
layout. Additional knowledge is presented to aid in the
understanding of the layout design process.
Objectives In this class, you will learn how to convert logic-level schematics to
transistor-level schematics to layout drawings, and how to create
layout drawings to design specications.
Topics The following topics are covered in this chapter:
Topics Page
What is an IC? ..................................................................................
How Is an IC Designed? ..................................................................
Basic Layout Design Tasks ..............................................................
What Are the Design Data Representations? ...................................
What is an IC?
Introduction Integrated Circuits (ICs) are used in millions of applications.
Producing ICs is the primary business of Intel, which holds 75% of
the marketplace.
Denition An IC is a single piece of silicon that performs various electronic
functions.
Examples Examples of ICs, along with their applications, include the
following:
CMOS Technology Complementary Metal Oxide Semiconductor (CMOS) is the name
of the technology used to create ICs.
Example The graphic below shows a silicon wafer and one IC in the wafer.
Type of IC Use
microprocessor/CPU computers
memory data storage and retrieval
micro-controller communication between ICs
imbedded processor/controller printers, anti-lock brakes
Silicon Wafer IC
Periphery: Connections
are made to the periphery of
the IC with wires.
How Is an IC Designed?
Introduction There are many phases required in the creation of an IC.
Process The following gure shows the IC design process, an example of
each process step, and who implements that step:
Micro-Architecture
Design and Verication
Logic Design
and Verication
Circuit Design and
Performance Verication
Layout Design
and Verication
Mask
Generation
Tapeout and
First Silicon
Tapeout and
Fabrication
Design Process Example Who Implements
Dene the
Engineer
Describe
product
functions
Engineer
Engineer
Implement
product
functions
Represent
functions
physically
Mask Designer
Transfer physical
representation onto
template
Vendor
Create the
product from
product
Manufacturer
the template
Create the rst
sample of the
actual product
Manufacturer
Basic Layout Design Tasks
Introduction The basic layout design tasks are part of the layout design and
verication stage of the IC design process. The mask designer takes
the design from logic-level schematics to transistor-level schematics
to drawn layout.
Layout Design Tasks The following gure shows how the basic layout design tasks t into
the IC design process:
Create Layout Drawings
Convert Logic-level
to Transistor-level
Interpret Logic-level
Micro-Architecture
Design and Verication
Logic Design
and Verication
Circuit Design and
Performance Verication
Layout Design
and Verication
Mask
Generation
Tapeout and
First Silicon
Tapeout and
Fabrication
Design Process
Basic Layout
Design Tasks
Schematics
Schematics
from Transistor-level
Schematics
1
2
3
What Are the Design Data Representations?
Introduction There are different ways to represent the design of an integrated
circuit.
Denition The design data representations are graphical ways of displaying the
design data. As you progress through the layout design tasks, you
will work with an increasing amount of design data detail.
Examples The gure below shows one electrical function an inverter in
the logic-level schematic, transistor-level schematic, and layout
representation.
Basic Layout
Design Tasks
Logic-level Schematic
1
2
3
Create Layout Drawings
Convert Logic-level
to Transistor-level
Schematics
Schematics
Schematics
Transistor-level
Layout Drawing
Schematic
CMOS 1 Chapter 3: How to Interpret Logic-level Schematics
Chapter 3:
How to Interpret Logic-level Schematics
Convert Logic-level
to Transistor-level
Schematic
Schematics
Create Layout Drawing
Schematic
1
2
3
Chapter 3: How to Interpret Logic-level Schematics CMOS 1
Chapter Overview
Introduction Logic-level schematics are a standard way for the engineers to
communicate the functions of an IC to other project members.
Objective In this chapter, you will learn to identify the parts of logic-level
schematics and describe the function of the logic symbols.
Topic Page
Lesson 3-1: How to Identify the Parts of a Logic-level
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3
Lesson 3-2: How to Describe the Function of a Logic Symbol 3-13
Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36
CMOS 1 Lesson 3-1: How to Identify the Parts of a Logic-level Schematic
Lesson 3-1:
How to Identify the Parts of a
Logic-level Schematic
Lesson 3-1: How to Identify the Parts of a Logic-level Schematic CMOS 1
Lesson 3-1 Overview
Introduction To accomplish the task of interpreting the logic-level schematic, you
must be able to identify its parts. The logic-level schematic is the
rst graphical data representation of the ICs function.
Objective In this lesson, you will learn to identify the parts of a logic-level
schematic.
Topics The following topics are covered in this lesson:
Topic Page
What Is a Logic-level Schematic? . . . . . . . . . . . . . . . . . . . . 3-5
Lab 3-1.a: Identify the Nodes of the Logic-level Schematic 3-6
Logic Symbols of the Basic Logic Functions . . . . . . . . . . . 3-8
Lab 3-1.b: Identify the Logic Symbols of the Logic-level
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Logic-level Schematic Drawing Conventions . . . . . . . . . . . 3-10
Lesson 3-1: How to Identify the Parts of a Logic-level
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
What Is a Logic-level Schematic?
Introduction Mask designers must be able to identify the parts of a logic-level
schematic in order to convert it into a transistor-level schematic.
Denition The logic-level schematic is a short-hand representation of the actual
functions that make up the IC. Two main parts of logic-level
schematics are logic symbols and nodes.
G Logic symbol: a short-hand representation for basic or complex
logic functions.
G Node: an electrical path between logic symbols or the inputs and
output of the logic symbols. Nodes are drawn as lines. There are
three types of nodes on a logic-level schematic, as follows:
Input: Supply information to the logic symbol.
Output: Carry information away from the logic symbol.
Internal: Carry information between logic symbols.
Example 1 The following gure is a logic-level schematic containing a single
logic symbol with the logic symbol and nodes labeled.
Example 2 The following gure is a logic-level schematic containing two logic
symbols with the logic symbols and nodes labeled.
Logic Symbol
Nodes
A OUT
OUT
A
B
C
Input
Logic Symbols
Nodes
Internal
Node
Output
Node
Lab 3-1.a: Identify the Nodes of the Logic-level Schematic
Introduction Now that you know two of the main parts of a logic-level schematic,
logic symbols and nodes, you will identify the logic symbols and
nodes in a logic-level schematic.
Instructions for Lab 3-1.a
1. Given the following logic-level schematic, complete the exercises.
a. How many logic symbols are in the logic-level schematic?
b. Color each of the nodes in the logic-level schematic a different color.
c. How many nodes are in the logic-level schematic?
d. How many input nodes are in the logic-level schematic?
e. How many internal nodes are in the logic-level schematic?
f. How many output nodes are in the logic-level schematic?
2. Given the following logic-level schematic, complete the exercises.
a. How many logic symbols are in the logic-level schematic?
b. Color each of the nodes in the logic-level schematic a different color.
c. How many nodes are in the logic-level schematic?
d. How many input nodes are in the logic-level schematic?
e. How many internal nodes are in the logic-level schematic?
f. How many output nodes are in the logic-level schematic?
Logic Symbols of the Basic Logic Functions
Introduction Following are the standard logic symbols used to represent the basic
functions. A logic symbols is always drawn with its input and output
nodes.
Inverter Logic Symbol The Inverter logic symbol is as follows:
AND Logic Symbol The AND logic symbol is as follows:
NAND Logic Symbol By inverting the output of the AND logic symbol (represented by the
bubble on the output node), the NAND logic symbol is created. The
2-input NAND logic symbol is as follows:
OR Logic Symbol The OR logic symbol is as follows:
NOR Logic Symbol By inverting the output of the OR logic symbol (represented by the
bubble on the output node), the NOR logic symbol is created. The
2-input NOR logic symbol is as follows:
Number of Input Nodes There can be more than two input nodes on the AND, NAND, OR,
and NOR logic symbols. However, the inverter can only have one
input node.
Number of Output
Nodes
There is only one output node on the basic logic symbols used in this
class.
A OUT
A
B
OUT
A
B
OUT
A
B
OUT
A
B
OUT
Lab 3-1.b: Identify the Logic Symbols of the Logic-level
Schematic
Introduction Now that you know the name of the function that each logic symbol
represents, you will identify the function name and the number of
inputs for each logic symbol in a logic-level schematic.
Instructions for Lab 3-1.b
1. Given the following logic-level schematic, ll in the table below with the names of
logic symbols and the number of input nodes each logic symbol has.
1 2
3
5
4
Logic Symbol
Number
Logic Symbol
Function
Number of Input
Nodes
1
2
3
4
5
Logic-level Schematic Drawing Conventions
Introduction To draw and interpret logic-level schematics, you must follow a set
of conventions. Each project has slightly different conventions. The
following are the conventions for this class.
Logic Symbol
Orientation
The orientation of the logic symbol does not affect its functionality;
the following inverter logic symbols are all equivalent.
Connecting Nodes Nodes to be connected are drawn with a dot connecting the lines.
When nodes cross without a dot, they are not connected.
Connected Nodes:
Crossing Unconnected Nodes:
Example: Connected and crossing nodes are drawn in a schematic
as follows:
continued...
A
A
A
A
A
A
B
Nodes cross, but are not connected
Nodes are connected
Logic-level Schematic Drawing Conventions (continued)
Supply Voltages G Vcc or Power is the logical high: 1
G Vss or Ground is the logical low: 0
Example: A NAND logic symbol with one input node connected to
Vcc and the other input node connected to Vss.
Vcc
Vss
C
Lab 3-1.c: Identify the Parts of the Logic-level Schematic
Introduction Now that you know how to identify the function of the logic
symbols, and the node drawing convention, you will identify the
function of the logic symbols and the number of unique nodes in a
logic-level schematic.
Instructions for Lab 3-1.c
1. Given the following logic-level schematic, complete the following exercises.
a. List the function names of the logic symbols.
1.
2.
3.
4.
b. How many unique nodes are in the logic-level schematic?
1
2
3
4
CMOS 1 Lesson 3-2: How to Describe the Function of a Logic Symbol
Lesson 3-2:
How to Describe the Function of a Logic Symbol
Lesson 3-2: How to Describe the Function of a Logic Symbol CMOS 1
Lesson 3-2 Overview
Introduction To really understand the function of a logic symbol, you must be
able to describe its function.
Objective In this lesson, you will learn how to describe the logic function of
the logic symbols with truth tables.
Topic Page
What Are the Standard Logic Functions? . . . . . . . . . . . . . . 3-15
Practice 3-2.a: Evaluate Boolean Algebra Equations . . . . . 3-18
What Are Truth Tables? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
How Is the Number of Rows for a Truth Table Determined? 3-20
Practice 3-2.b: Determine the Number of Columns and Rows
for a Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
How Are Input Values for a Truth Table Filled In? . . . . . . . 3-23
Practice 3-2.c: Fill in the Input Values for a Truth Table . . . 3-26
Output Values of the Truth Tables . . . . . . . . . . . . . . . . . . . . 3-27
Practice 3-2.d: Describe Logic Functions with Truth Tables 3-29
What Are the Standard Logic Functions?
Introduction Logic functions are the basis of dening the functionality that exists
in an IC. Boolean algebra and truth tables are used to identify the
relationship between the input and output values of the logic
functions.
Denition A logic function is a denition of an output condition based on a set
of input conditions. The input and output values are in one of two
states, for example:
Logic Functions The basic logic functions are dened by Boolean algebra. Boolean
algebra uses the following symbols for the logic functions:
continued...
State 1 State 2
High Low
1 0
On Off
Vcc Vss
Boolean Symbol
Logic Function
Name
Inverse
*
AND
+
OR
What Are the Standard Logic Functions? (continued)
Basic Functions The basic logic functions dened by Boolean algebra are as follows:
G Inverse function: The Inverse function output is always a 0 when
the input is a 1 and always a 1 when the input is a 0.
G AND function: the output is 1 only when all inputs are 1s.
G OR function: the output is 0 only when all inputs are 0s.
continued...
Value Invert Value INVERSE
A = 0 0 = 1 0 = 1
A = 1 1 = 0 1 = 0
AND
0 * 0 = 0
0 * 1 = 0
1 * 1 = 1
OR
0 + 0 = 0
0 + 1 = 1
1 + 1 = 1
A OUT
A = OUT
A
B
OUT
A * B = OUT
A
B
OUT
A + B = OUT
What Are the Standard Logic Functions? (continued)
Inverse Functions The Boolean Algebra is created by inverting the basic functions:
G NAND function: the output is 0 only when all inputs are 1s.
G NOR function: the output is 1 only when all inputs are 0s.
AND Invert AND NAND
0 * 0 = 0 0 * 0 = 0 = 1 0 * 0 = 1
0 * 1 = 0 0 * 1 = 0 = 1 0 * 1 = 1
1 * 1 = 1 1 * 1 = 1 = 0 1 * 1 = 0
OR Invert OR NOR
0 + 0 = 1 0 + 0 = 0 =1 0 + 0 = 1
0 + 1 = 0 0 + 1 = 1 = 0 0 + 1 = 0
1 + 1 = 0 1 + 1 = 1 = 0 1 + 1 = 0
A
B
OUT
A * B = OUT
A
B
OUT
A + B = OUT
Practice 3-2.a: Evaluate Boolean Algebra Equations
Introduction Now that you know how to describe the denitions of the logic
functions with Boolean algebra, you will evaluate the following
Boolean algebra equations.
Instructions for Practice 3-2.a
1. For the following Boolean algebra equations, provide the name of the logic
function and the output value.
Equation Function Name Output Value
1 + 1 =
1 + 0 =
0 * 1 =
1 * 1 =
1 * 0 =
0 + 0 =
0 * 0 =
1 * 1 =
1 + 1 + 1 =
1 + 1 + 0 =
0 * 0 * 0 =
0 * 1 * 0 =
1 * 1 * 1 =
1 + 1 + 0 =
0 * 0 * 1 =
1 + 1 + 1 + 0 =
0 * 0 * 0 * 1 =
What Are Truth Tables?
Introduction An easy way to display the Boolean algebra equations is with a truth
table.
Denition A truth table is a chart of the output values of a logic function when
all possible combinations of 1s and 0s are applied as inputs. To
complete a truth table for a logic symbol, you need to know two
things.
G Which logic function does the logic symbol represent?
G How many input nodes does the logic symbol have?
Parts of a Truth Table The parts of the truth table are as follows.
1. Input/Output Rows: A row for each combination of input
values and the output value.
The maximum number of rows is equal to the maximum number
of input combinations.
2. Input/Output Node Values: The value of the input or output
node.
The node values are either 0s or 1s.
3. Input Columns: A column for each input node.
The number of input columns is equal to the number of input
nodes of the logic symbol.
4. Output Column: A column for the output node.
There is always one output column for a logic symbol.
B A OUT
0 0 0
0 1 0
1 0 0
1 1 1
3. Input Columns 4. Output Column
2. Input/Output
1. Input/Output
Node Values
Rows
How Is the Number of Rows for a Truth Table Determined?
Introduction The number of rows that a truth table needs is dened by the
maximum number of combinations for the input node values. There
is one row in the truth table for each combination of input node
values.
Procedure Determine the number of rows for the truth table as follows:
Examples An example using the formula with a 2-input NAND logic symbol
is as follows:
Maximum Combinations = 2
2
= 2 * 2 = 4
An example using the formula with a 3-input NOR logic symbol is
as follows:
3
= 2 * 2 * 2 = 8
Step Action
1. Identify the number of input nodes for the logic symbol you are
describing.
2. Calculate the maximum number of combinations for the input
nodes with the following formula:
(number of input nodes)
A
B
OUT
A
B OUT
C
Practice 3-2.b: Determine the Number of Columns and Rows
for a Truth Table
Introduction Now that you know how to determine the number of columns and
rows that are needed to create a truth table, determine the number of
columns and rows for the following logic symbols.
Instructions for Practice 3-2.b
1. For an Inverter, complete the following.
a. Draw the logic symbol.
b. How many inputs columns does the truth table for this logic symbol have?
2. For a 4-input AND, complete the following.
b. How many input columns does the truth table for a 4-input logic symbol
have?
3. For a 4-input OR, complete the following.
b. Calculate the maximum number of input combinations for a 4-input logic
symbol. Show your work.
4. For a 5-input NOR, complete the following.
b. Calculate the maximum number of input combinations for a 5-input logic
symbol. Show your work.
c. Calculate the number of rows.
d. Draw the truth table.
Instructions for Practice 3-2.b
How Are Input Values for a Truth Table Filled In?
Introduction It is important to list all possible input combinations in the truth
table, so that the logic function can be completely described. Once
all of the input combinations are lled into the truth table, the output
values can be calculated.
Procedure Determine all possible input combinations as follows:
continued...
Step Action
1. Draw the truth table with the correct number of rows and
columns.
2. For the right-most input column, ll in each box down this
column with alternating 0s and 1s. Start with a 0 in the top box.
3. For the next column to the left, ll in this column with alternating
groups of two 0s then two 1s.
4. For each column to the left, continue to alternate between
groups of 0s and 1s. In each column, double the number of 0s
and 1s in each group.
How Are Input Values for a Truth Table Filled In? (continued)
Example Using the above procedure ll in the input values for a 3-input
NAND logic symbol.
continued...
Step Action
1. Draw the truth table with the correct number of rows and
columns.
Three inputs = three input columns
2
3
= 2 * 2 * 2 = 8 rows
2. For the right-most input column, ll in each box down this
column with alternating 0s and 1s. Start with a 0 in the top box.
C B A OUT
C B A OUT
0
1
0
1
0
1
0
1
How Are Input Values for a Truth Table Filled In? (continued)
Example (continued)
Step Action
3. For the next column to the left, ll in this column with alternating
groups of two 0s, then two 1s.
4. For each column to the left, continue to alternate between
groups of 0s and 1s. In each column, double the number of 0s
and 1s in each group.
For this column, there are four 0s and 1s in each group. If there
was another column, there would be eight 0s and 1s in each
group.
C B A OUT
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
C B A OUT
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Practice 3-2.c: Fill in the Input Values for a Truth Table
Introduction Now that you know the procedure to ll in the input values for a
truth table, you will draw truth tables and ll in the input values.
Instructions for Practice 3-2.c
1. Complete the following steps to create a truth table for a 3-input logic symbol; the
inputs are A, B, C, and the output is OUT.
a. Calculate the number of rows for the truth table.
b. Calculate the number of columns for the truth table.
c. Draw the truth table.
d. Fill in the input values; do not ll in the output column.
Output Values of the Truth Tables
Introduction Using the input values of a truth table and the correct Boolean
algebra equation, you can determine the output values.
Inverter Truth Table For the Inverter function, the output value is always the complement
(inverse) of the input value.
G The Inverter function truth table is as follows:
AND Truth Table For the AND function, if any of the inputs are 0, then the output is 0.
G The 2-input AND function truth table is as follows:
OR Truth Table For the OR function, if any of the inputs is 1, then the output is 1.
G The 2-input OR function truth table are is as follows:
continued...
A OUT
1 0
0 1
A = OUT
1 = 0
0 = 1
OUT A
A B OUT
0 0 0
0 1 0
1 0 0
1 1 1
A * B = OUT
0 * 0 = 0
0 * 1 = 0
1 * 1 = 1
A
B
OUT
A B OUT
0 0 0
0 1 1
1 0 1
1 1 1
A + B = OUT
0 + 0 = 0
0 + 1 = 1
1 + 1 = 1
A
B
OUT
Output Values of the Truth Tables (continued)
NAND Truth Table For the NAND function, if any of the inputs is 0, then the output is 1.
G The 2-input NAND function truth table is as follows:
NOR Truth Table For the NOR function, if any of the inputs is 1, then the output is 0.
G The 2-input NOR function truth table is as follows:
A B OUT
0 0 1
0 1 1
1 0 1
1 1 0
A * B = OUT
0 * 0 = 1
0 * 1 = 1
1 * 1 = 0
A
B
OUT
A B OUT
0 0 1
0 1 0
1 0 0
1 1 0
A + B = OUT
0 + 0 = 1
0 + 1 = 0
1 + 1 = 0
A
B
OUT
Practice 3-2.d: Describe Logic Functions with Truth Tables
Introduction Now that you know how to describe the logic functions with truth
tables, you will create truth tables for different logic functions.
Instructions for Practice 3-2.d
1. Complete the following truth table for a room light that is controlled by two
switches, one at each door. If either of the switches is on, then the light is on.
a. Does the above example describe an AND or an OR logic function?
A B
1
0
1
0
Switch
A
Switch
B
Light
2. Complete the following steps to create a truth table for a 3-input AND logic
function.
b. Write the Boolean algebra equation for the logic function.
c. Determine the number of input columns.
d. Determine the maximum number of rows.
e. Draw the truth table. Fill in all input combinations and the output values.
3. Complete the following steps to create a truth table for a 3-input OR logic
function.
4. Complete the following steps to create a truth table for a 4-input AND logic
function.
5. Complete the following steps to create a truth table for a 4-input NAND logic
function.
6. Create a truth table for a 4-input NOR logic function.
7. Complete all missing input and output values in the following table.
A B C
INV
A
NOR
A, B
NOR
A, B, C
NAND
A, B
NAND
A, B, C
0 0 0
1 1 1
Chapter Summary
Introduction In this chapter, you learned how to identify the parts of logic-level
schematics and to describe the functions of the logic symbols with
Boolean algebra and truth tables. This is the rst task of basic layout
design.
Summary In this chapter, you learned to,
G identify the parts of the logic-level schematic.
Logic symbol: short-hand representation for basic or
complex logic functions.
Node: electrical path between logic symbols or the inputs
and output of the logic symbols. Nodes are drawn as lines.
G describe the function of the logic symbols with Boolean algebra.
Inverter: A = OUT
AND: A * B = OUT
OR: A + B = OUT
NAND: A * B = OUT
NOR: A + B = OUT
G create truth tables that chart the output values of a logic function
when all possible combinations of 1s and 0s are applied as
inputs. A summary of the logic functions is as follows:
B A A A * B A * B A + B A + B
0 0 1 0 1 0 1
0 1 0 0 1 1 0
1 0 1 0 1 1 0
1 1 0 1 0 1 0
CMOS 1 Chapter 4: How to Convert a Logic-level Schematic to a Transistor-level Schematic
3
Chapter 4:
How to Convert a Logic-level Schematic
to a Transistor-level Schematic
Convert Logic-level
to Transistor-level
Schematic
Schematics
Schematics
1
2
3
Chapter 4: How to Convert a Logic-level Schematic to a Transistor-level Schematic CMOS 1
Chapter Overview
Introduction The layout designer needs more detail than the logic-level schematic
provides, so the logic-level schematic must be converted into a
transistor-level schematic.
Objective In this chapter, you will learn to convert a logic-level schematic to
Lesson Page
Lesson 4-1: How to Identify the Parts of a Transistor-level
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Lesson 4-2: How to Verify the Transistor-level Function of a
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Lesson 4-3: How to Convert a Logic-level Schematic to a
Transistor-level Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45
CMOS 1 Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic
40
Lesson 4-1:
How to Identify the Parts of a Transistor-level
Schematic
Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic CMOS 1
Lesson 4-1 Overview
Introduction Before you can convert the logic-level schematic to a transistor
schematic, you need to know the parts of the transistor-level
schematic.
Objective In this lesson, you will learn to identify the parts of a transistor-level
schematic.
Topics The following are covered in this lesson:
Lesson Page
What Is a Transistor-level Schematic? . . . . . . . . . . . . . . . . . 4-5
What Is a Transistor? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Nodes of a Transistor-level Schematic . . . . . . . . . . . . . . . . . 4-9
Transistor Representations of the Logic-level Schematics . 4-10
Lab 4-1: Identify the Parts of Transistor-level Schematics . 4-12
What Is a Transistor-level Schematic?
Introduction The transistor-level schematic has more details than the logic-level
schematic; the shorthand symbols of the logic-level schematic are
converted to the transistor-level schematic.
Denition The transistor-level schematic is a representation of the actual
transistors and the connections that create the logic functions of the
IC.
G Transistors: representation of the actual layout transistors.
G Node: an electrical path between transistors or the inputs and
output of the transistors. Nodes are drawn as lines.
Example The following gure is a transistor-level schematic of an inverter
with the nodes labeled, and just the power supplies and transistors
pulled apart.
A B
Vcc
Transistors
Vss
Nodes
What Is a Transistor?
Introduction There are different types of technologies used to create transistors;
Intel uses the Complementary Metal Oxide Semiconductor (CMOS)
technology.
Denition The transistor is the basic building block of all functions on any IC.
CMOS technology uses two types of Metal Oxide Semiconductor
Field Effect Transistors (MOSFET)
G pFET (p-type)
G nFET (n-type)
Each type of MOSFET transistor has the following four elements.
G gate: input terminal
G source: terminal closest to Vcc or Vss
G drain: output terminal
G bulk: material that the transistor sits in
The complementary part of CMOS means that pairs of p-type and n-
type transistors are used to create the functions of the logic symbols.
Analogy The source, gate, and drain of a transistor are similar to the circuits
in your home.
continued...
Transistor Your Home
Source Power Company
Gate Light switch
Drain Lamp
What Is a Transistor? (continued)
Example The p-type transistor and the n-type transistor are drawn as follows:
P-Type vs. N-Type
Transistors
The p-type and n-type transistors differ as follows:
Orientation The orientation of the transistor does not affect the performance or
function of the transistor. All of the following n-type transistors are
equivalent.
Source and Drain
Regions
The source and drain regions are interchangeable and from this point
on are referred to as source/drain (S/D).
continued...
p-type n-type
Majority Current Carrier hole electron
Gate Bubble yes no
Logical On 0 1
Bulk n-well epitaxial
Source
Drain
Gate
Hole
Flow
Gate Bubble
Bulk
Source
Drain
Gate
Flow
Electron
Bulk
p-type Transistor n-type Transistor
What Is a Transistor? (continued)
Logical On A logical on is when a transistor is logically on, the current ows
through the transistor.
Hole Ahole is a mobile vacancy within a semi-conductor material created
by the lack of an electron. A hole ows in the opposite direction as
the current.
Electron An electron is the basic atomic particle orbiting an atom. An electron
ows in the same direction as the current.
Current Current is the movement of electrons through a circuit.
Nodes of a Transistor-level Schematic
Introduction It is important for you to be able to identify all of the nodes in a
Nodes of a Transistor-
level Schematic
The input and output nodes, the connections between two
transistors, Vcc and Vss, are all nodes on a transistor-level
schematic.
A transistor-level schematic of an INVERTER has the following
four nodes:
1. between the upper S/D region of the p-type transistor and Vcc
2. from the input node to the gate of both transistors
3. from the lower S/D region of the p-type transistor to the upper
S/D region of the n-type transistor to the output node
4. between the lower S/D region of the n-type transistor and Vss
Internal Nodes There will be times when a node is not an input, output, Vcc, or Vss
node as follows.
A B
A B
Logic-level
Schematic
Transistor-level
Schematic
1
3
4
2
Internal Node
Transistor Representations of the Logic-level Schematics
Introduction The following are the logic symbol, truth table, and transistor-level
representations of the logic symbols used in this class.
Inverter
Representations
The Inverter logic, transistor-level representation, and truth table are
as follows:
NAND Representations The NAND logic, transistor-level representation, and truth table are
as follows:
continued...
A B
A OUT
A OUT
0 1
1 0
Logic-level
Truth Table
Transistor-level
A
B
OUT
A
B
C
A B OUT
0 0 1
0 1 1
1 0 1
1 1 0
Logic-level
Truth Table
Transistor-level
Transistor Representations of the Logic-level Schematics
(continued)
NOR Representations The NOR logic, transistor representation, and truth table are as
follows:
Logic Symbol Dots A dot drawn on the logic symbol indicates how the series transistors
are drawn. For this class, the convention is that the dot indicates
which series transistor is drawn closest to the output node. The dot
affects only the drawing of the series transistors. The placement of
the dot is determined by the design engineer to address any timing
issues. Logic symbols with dots drawn are as follows:
A
B
C
OUT
A
B
A B Out
0 0 1
0 1 0
1 0 0
1 1 0
Transistor-level
Truth Table
Logic-level
Lab 4-1: Identify the Parts of Transistor-level Schematics
Introduction Now that you know the parts of the transistor-level schematic, you
will identify the transistors and nodes in the following exercises.
Instructions for Lab 4-1
1. Given the following logic and transistor-level schematic, complete the exercises.
a. How many nodes does the logic-level schematic have?
b. Color each node of the transistor-level schematic with a different color.
c. How many nodes does the transistor-level schematic have?
d. How many p-type transistors does the transistor-level schematic have?
e. How many n-type transistors does the transistor-level schematic have?
A OUT
A OUT
a. What type of logic symbol is this?
b. How many nodes does the logic-level schematic have?
c. Color each node of the transistor-level schematic with a different color.
d. How many nodes does the transistor-level schematic have?
e. How many p-type transistors does the transistor-level schematic have?
f. How many n-type transistors does the transistor-level schematic have?
A
B
OUT
A
B
OUT
A
B
OUT
OUT
A
B
4. Given the following logic and transistor-level schematic,
complete the exercises.
A C
OUT
B
A
B
OUT
30
15
C
Lesson 4-2: How to Verify the Transistor-level Function of a Logic Symbol CMOS 1
41
Lesson 4-2:
How to Verify the Transistor-level Function of a
Logic Symbol
CMOS 1 Lesson 4-2: How to Verify the Transistor-level Function of a Logic Symbol
Lesson 4-2 Overview
Introduction Knowledge of how transistors work allows a better understanding of
how the logic functions execute.
Objective In this lesson, you will learn to verify the input and output values of
the truth table against how the transistors turn on and off to allow
current to ow.
Topic Page
Values that Turn a Transistor On or Off . . . . . . . . . . . . . . . . 4-18
How Are Truth Table Values Veried? . . . . . . . . . . . . . . . . 4-19
Practice 4-2: Verify the Transistor-level Function of the Logic
Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
Values that Turn a Transistor On or Off
Introduction You have seen the logic, the transistor representation, and the truth
tables of the basic logic symbols. Now it is time to trace the nodes
through the transistors from the input to the output. This will
validate that the truth tables accurately represent the logic.
Turning a Transistor On
or Off
Remember that when a transistor is logically on, the current is
owing through the transistor. An analogy is a light switch in your
home; when the light switch is turned on the current ows from the
power company to the lamp.
P-Type N-Type
Logical value to turn transistor on 0 1
Logical value to turn transistor off 1 0
Memory aid Bubble No Bubble
How Are Truth Table Values Veried?
Introduction By tracing the input values and their affect on the transistors, you
can see how the output value is created.
Procedure Verify the inputs and outputs against the truth table with the
following steps:
Reminders Remember the values that turn the p-type and n-type transistors on
and off.
Remember that Vcc and Vss have the following logical values:
G Vcc = 1
G Vss = 0
continued...
Step Action
1. Apply the rst row of the truth table to the input nodes.
2. Determine which transistor gates are on and off. Write on or
off for each transistor.
3. Trace a path through the transistors from Vss to the output
node and from Vcc to the output node. Determine which path is
complete.
G If a path is found from Vss, then the output value is 0.
G If a path is found from Vcc, then the output value is 1.
4. Note that the value at the output node matches the truth table.
5. Repeat for each row of the truth table.
P-Type N-Type
How Are Truth Table Values Veried? (continued)
Inverter Example Using the transistor-level schematic and the truth table, complete the
steps of the above procedure to verify the inputs and output values.
Use the procedure for the rst line of the truth table, as follows:
continued...
Step Action
a. the p-type transistor is on
b. the n-type transistor is off
complete.
G If a path is found from Vcc, then the output value is 1.
A path is found from Vcc to the output node, so a logical 1
is at the output.
4. Note that the value at the output node matches the truth
table.
The input of a logical 0 is inverted to a logical 1.
A B
A OUT
0 1
1 0
A = 0 B = 0
on
off
How Are Truth Table Values Veried? (continued)
Inverter Example
(continued)
Use the same transistor-level schematic and truth table.
Repeat the procedure for the next line of the truth table, as follows:
Step Action
1. Repeat for the next row of the truth table.
a. the p-type transistor is off
b. the n-type transistor is on
complete.
G if a path is found from Vcc, then the output value is 1.
A path is found from Vss to the output node, so a logical 0
is at the output.
4. Note that the value at the output node matches the truth
table.
The input of a logical 1 is inverted to a logical 0.
A B
A OUT
0 1
1 0
A = 1 B = 0
off
on
Practice 4-2: Verify the Transistor-level Function of the Logic
Symbols
Introduction Now that you know what value turns on a p-type and an n-type
transistor and how to verify the values of a truth table, you will
verify the following transistor-level schematics and truth tables.
Instructions for Practice 4-2
1. Given the following 2-input NAND transistor-level schematic and truth table, use
the outlined procedure to verify the truth table values, as directed.
A
B
OUT
B A OUT
0 0 1
0 1 1
1 0 1
1 1 0
Step Action
2. Determine which transistor gates are on and off. Write ON or
OFF for each transistor.
complete.
G If a path is found from Vss, then the output value is 0
G if a path is found from Vcc, then the output value is 1
2. a. Apply the rst row of the truth table to the following transistor-level
schematic.
b. Apply the second row of the truth table to the following transistor-level
schematic.
c. Apply the third row of the truth table to the following transistor-level
schematic.
A
B
OUT
A
B
OUT
A
B
OUT
3. d. Apply the fourth row of the truth table to the following transistor-level
schematic.
4. Given the following 2-input NOR transistor-level schematic and truth table, use
the outlined procedure to verify the truth table values.
A
B
OUT
OUT
A
B
B A OUT
0 0 1
0 1 0
1 0 0
1 1 0
Step Action
2. Determine which transistor gates are on and off. Write ON or
OFF for each transistor.
complete.
G If a path is found from Vss, then the output value is 0
G if a path is found from Vcc, then the output value is 1
5. a. Apply the rst row of the truth table to the following transistor-level
schematic.
b. Apply the second row of the truth table to the following transistor-level
schematic.
c. Apply the third row of the truth table to the following transistor-level
schematic.
OUT
A
B
OUT
A
B
OUT
A
B
6. d. Apply the fourth row of the truth table to the following transistor-level
schematic.
7. For the 3-input NAND logic symbol, complete the following.
a. Draw the transistor-level schematic.
b. Draw and ll in the truth table.
c. Using the same procedure as in the previous exercises, verify the truth table
values.
8. For the 3-input NOR logic symbol, complete the following.
a. Draw the transistor-level schematic.
b. Draw and ll in the truth table.
c. Using the same procedure as in the previous exercises, verify the truth table
values.
OUT
A
B
CMOS 1 Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic
42
Lesson 4-3:
How to Convert a Logic-level Schematic to a
Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic CMOS 1
Lesson 4-3 Overview
Introduction Up to this point, the transistor-level schematics have been given to
you. However, you will need to know how to draw the transistor-
level schematics. The level of detail of the transistor-level schematic
is needed to create the layout drawings.
Objective In this lesson you will learn to convert a logic-level schematic to a
Topic Page
Logic Functions Dened with Transistors . . . . . . . . . . . . . . 4-29
How Is a Logic-level Schematic Converted to a Transistor-
level Schematic? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
Practice 4-3: Convert a Logic-level Schematic to a Transistor-
level Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
What is Complex Logic? . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
Order of the Series Transistors . . . . . . . . . . . . . . . . . . . . . . . 4-34
How Is a Complex Logic-level Schematic Converted to N-
Type Transistors? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
Lab 4-3.a: Convert Complex Logic-level Schematics to N-
Type Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
How Is a Complex Logic-level Schematic Converted to P-
Type Transistors? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
Lab 4-3.b: Convert Complex Logic-level Schematics to P-
Type Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
Lab 4-3.c: Convert Complex Logic-level Schematics to
Transistor-level Schematics . . . . . . . . . . . . . . . . . . . . . . . . . 4-44
Logic Functions Dened with Transistors
Introduction Before converting a logic-level schematic to a transistor-level
schematic, you need to understand how the transistors dene the
logic of the function.
Logic Functions The logical function of a logic symbol is always dened by the n-
type transistors.
G NAND function
based on the AND function
n-type transistors are in series
p-type transistors are parallel
G NOR function
based on the OR function
n-type transistors are parallel
p-type transistors are in series
A
B
OUT
A
B
OUT
series
parallel
transistors
transistors
OUT
A
B
A
B
OUT
series
parallel
transistors
transistors
How Is a Logic-level Schematic Converted to a
Transistor-level Schematic?
Introduction The transistor-level schematic equivalent of a logic-level schematic
is drawn with a straightforward procedure.
Procedure The procedure of converting a logic-level schematic to a transistor-
level schematic is as follows:
continued...
Step Action
1. Determine the logic function of the logic symbol: NAND or NOR.
2. Calculate the number of transistors, as follows:
# of transistors = 2 * (# of input nodes)
For example, for a 2-input NAND logic symbol:
# of transistors = 2 * (2) = 4
Half of the transistors are p-type transistors and half are n-type
transistors.
3. Draw the output node as a horizontal line.
4. Create the n-type transistors according to the logic function of
the logic symbol and label all transistor nodes according to the
5. Add the p-type transistors as the complement to the n-type
transistors and label all nodes according to the logic-level
schematic.
Remember:
6. Connect all common nodes.
If n-type transistors
are...
then p-type transistors
are...
in series parallel
parallel in series
How Is a Logic-level Schematic Converted to a
Transistor-level Schematic? (continued)
Example Use the NAND logic symbol and the procedure outlined, as follows.
Step Action
1. Determine the logic function of the logic symbol: NAND or NOR.
NAND; the n-type transistors are in series.
2. Draw the output node as a horizontal line.
3. Create the n-type transistors according to the logic function of
the logic symbol and label all transistor nodes according to the
4. Add the p-type transistors as the complement to the n-type
transistors and label all nodes according to the logic-level
schematic.
5. Connect all common nodes.
A
B
OUT
OUT
B
A
OUT
B
A
OUT
A
B
OUT
Practice 4-3: Convert a Logic-level Schematic to a
Introduction Now that you know how to convert logic symbols to transistor-level
schematics, you will convert the following logic symbols.
1. Using the described procedure, convert the following logic-level schematics to a
a.
b.
c.
d.
e.
A
B
OUT
A
B
Out
A
B
OUT
N1
OUT
A
B
N1
D
E
F
OUT
A
B
C
N1
N2
What is Complex Logic?
Introduction Understanding the basic logic functions is not enough; you need to
be able to a convert complex logic function into transistor-level
schematic.
Denition Complex logic is the combination of non-inverted logic functions
and an inverted logic function that produce a new function. The new
function is drawn with fewer transistors and has increased
performance.
The non-inverted logic functions cannot be drawn directly with the
CMOS process.
Example A logic-level schematic of a complex logic symbol is as follows:
Internal Nodes There are internal nodes in complex logic where the logic symbols
touch, as follows:
B
A
OUT
D
C
Inverted
Non-Inverted
Functions
Function
B
A
OUT
D
C
Internal Node
Internal Node
Order of the Series Transistors
Introduction For the transistors drawn in series, the ordering is important for
timing purposes and is communicated by the design engineer on the
Logic Symbol Dots A dot drawn on the logic symbol indicates the transistor that is
drawn closest to the output node. The dot affects the drawing of the
series transistors and the series boxes of complex logic.
G A dot on the parent indicated the box closest to the output node.
G A dot on the logic symbol in a box indicates the transistor of the
logic symbol that must be closest to the output node.
A logic-level schematic with dots is drawn as follows:
A
B
OUT
C
D
How Is a Complex Logic-level Schematic Converted to
N-Type Transistors?
Introduction Converting a complex logic-level schematic is accomplished with
the following procedure. Since the n-type transistors determine the
logic function it is easier to draw them rst. In the next section, you
will learn to add the p-type transistors.
Procedure The procedure of converting a complex logic-level schematic to the
n-type transistors is as follows:
continued...
Step Action
1. Identify the parts of the logic-level schematic; input, output,
internal nodes, logic symbols.
2. Identify the inverted logic function. Draw a box around the logic
symbol the output node is connected to and call this parent.
3. Identify the inputs to parent. Draw a box around each of the
logic symbols and input nodes going into parent. Label each of
these boxes; for example, Box1, Box2.
4. Begin the transistor-level schematic. Draw a horizontal line to
represent the output node and label it.
5. Determine the logic function (NAND or NOR) of the n-type
transistors of parent.
Tip: Remember that the n-type transistors determine the logic
function of the logic symbol (in series or parallel).
6. Draw and connect the boxes, in series or parallel, to the output
node and to Vss as dened by the function of parent.
7. Draw the n-type transistors into the corresponding boxes for
each logic symbol and label all the input nodes.
N-Type Transistors? (continued)
Example Using the following complex logic-level schematic:
Complete the conversion procedure, as follows:
continued...
Step Action
1. Identify the parts of the logic-level schematic; input, output,
internal nodes, logic symbols.
2. Identify the inverted logic function. Draw a box around the logic
symbol the output node is connected to and call this parent.
3. Identify the inputs to parent. Draw a box around each of the
logic symbols and input nodes going into parent. Label each of
these boxes; for example, Box1, Box2.
4. Begin the transistor-level schematic. Draw a horizontal line to
represent the output node and label it.
5. Determine the logic function (NAND or NOR) of the n-type
transistors of parent.
In this example, logic function of parent is the NAND
function, so the n-type transistor boxes are drawn in series.
B
A
OUT
D
C
B
A
OUT
D
C
parent
B
A
OUT
D
C
parent
Box 1
Box 2
OUT
How Is a Complex Logic-level Schematic Converted to N-
Type Transistors? (continued)
Example (continued) The rest of the steps are as follows:
Step Action
6. Draw and connect the boxes, in series or parallel, to the output
node and to Vss as dened by the function of parent.
Since the n-type transistors of the NAND logic are in series,
draw the boxes in series.
7. Draw the n-type transistors into the corresponding boxes for
each logic symbol and label all the input nodes.
Box 1: OR function. The transistors are parallel.
Box 2: AND function. The transistors are in series.
OUT
Box 2
Box 1
OUT
Box 2
C
D
Box 1
A B
Lab 4-3.a: Convert Complex Logic-level Schematics to
N-Type Transistors
Introduction Now that you know how to convert a complex logic-level schematic
to the n-type transistors and how to determine which transistors must
be closest to the output node, you will draw the n-type transistors in
the correct order for complex logic-level schematics.
Use a full page of paper for each drawing. Put the n-type transistors at the bottom of
the page and leave room at the top to later add the p-type transistors.
1. Given the following logic-level schematic, complete the following.
a. How many n-type transistors are needed?
b. Draw the n-type transistors for the logic-level schematic; pay attention to the
dot notation.
OUT
A
B
C
D
dot notation.
dot notation.
A
B
OUT
E
F
C
D
A
B
OUT
C
P-Type Transistors?
Introduction You know how to draw the n-type transistors of the complex logic.
Now you will add the p-type transistors.
Procedure The procedure of converting a complex logic-level schematic to the
p-type transistors is as follows:
continued...
Step Action
1. Draw and connect the boxes to hold the p-type transistors in a
way that is complementary to the boxes holding the n-type
transistors.
Pay attention to which logic symbol is marked to be drawn
nearest to the output node.
2. Draw the p-type transistors in the new boxes, connect the
transistors to the output and Vcc nodes, and label the input
nodes.
Tip: Remember that the n-type and p-type transistors are
complementary.
3. Connect the common nodes: A to A, etc.
If N-Type transistors
are...
then P-Type transistors
are...
in series parallel
parallel in series
P-Type Transistors? (continued)
Example Use the same complex logic-level schematic used to draw the n-type
transistors.
Add the p-type transistors using the procedure, as follows:
continued...
Step Action
1. Draw and connect the boxes to hold the p-type transistors in a
way that is complementary to the boxes holding the n-type
transistors.
Pay attention to which logic symbol is marked to be drawn
nearest to the output node.
In this example, the n-type transistor boxes are in series, so
the p-type transistor boxes are parallel.
B
A
OUT
D
C
parent
Box 1
Box 2
OUT
Box 2
C
D
Box 1
A B
Box 2
Box 1
P-Type Transistors? (continued)
Example (continued) The rest of the steps are as follows:
Step Action
2. Draw the p-type transistors in the new boxes, connect the
transistors to the output and Vcc nodes, and label the input
nodes.
Box 1: n-type transistors are parallel, so the p-type
transistors are in series.
Box 2: n-type transistors are in series, so the p-type
transistors are parallel.
3. Connect the common nodes: A to A, etc.
OUT
Box 1
Box 2
C D
B
A
OUT
Box 2
D
Box 1
Box 1
Box 2
C A
B
A
Lab 4-3.b: Convert Complex Logic-level Schematics to
P-Type Transistors
to the p-type transistors, you will add the p-type transistors in the
correct order for the complex logic-level schematics you drew in the
last practice.
Use the drawings you made in the previous lab and add the p-type transistors for the
following exercises.
1. For the following logic-level schematic, add the p-type transistors to the
transistor-level schematics you drew in the last practice.
OUT
A
B
C
D
A
B
OUT
E
F
C
D
A
B
OUT
C
Lab 4-3.c: Convert Complex Logic-level Schematics to
Transistor-level Schematics
to the n-type and p-type transistors, you will draw both the n-type
and p-type transistors for complex logic-level schematics.
1. For the following logic-level schematic, draw the transistor-level schematic.
2. For the following logic-level schematic, draw the transistor-level schematic.
OUT
C
D
A
B
A
B
OUT
E
F
C
D
Chapter Summary
Introduction In this chapter, you learned how to identify the parts of a transistor-
level schematic, how to verify the transistor-level function of the
logic symbols, and how to convert logic-level schematics to
transistor-level schematics.
Summary In this chapter, you learned to
G identify the parts of the transistor-level schematic.
Transistors: transistor-level schematic transistors represent
the actual layout transistors.
pFET (p-type)
nFET (n-type)
The p-type and n-type transistors differ as follows:
Node: an electrical path between transistors or the inputs and
output of the transistors. Nodes are drawn as lines.
The input and output nodes, the connections between two
transistors, Vcc and Vss, are all nodes on a transistor-level
schematic.
G verify the transistor-level function of the logic symbols
How to turn a transistor on:
continued...
P-type N-type
Majority Current Carrier hole electron
Gate Bubble yes no
Logical On 0 1
Bulk n-well epitaxial
P-Type N-Type
Chapter Summary (continued)
Summary (continued) G convert logic-level schematics to transistor-level schematics
The logical function of a logic symbol is always dened by the
n-type transistors.
NAND symbols
based on the AND function
n-type transistors are in series
p-type transistors are parallel
NOR symbol
based on the OR function
n-type transistors are parallel
p-type transistors are in series
A
B
OUT
A
B
OUT
OUT
A
B
A
B
OUT
CMOS 1 Chapter 5: How to Create a Layout Drawing from a Transistor-level Schematic
43
Chapter 5:
How to Create a Layout Drawing from
a Transistor-level Schematic
Convert Logic-level
to Transistor-level
Schematic
Schematic
from a Transistor-level
Schematic
1
2
3
Chapter 5: How to Create a Layout Drawing from a Transistor-level Schematic CMOS 1
Chapter Overview
Introduction To create the masks for IC fabrication, the actual geometry size and
spacing is needed. The transistor-level schematic must therefore be
converted into a layout drawing.
Objective To convert a transistor-level schematic to a layout drawing.
Lesson Page
Lesson 5-1: How to Identify a Transistor on the IC Cross
Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Lesson 5-2: How to Identify Process Design Rules on the
Transistor Cross Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Lesson 5-3: How to Convert a Transistor-level Schematic to a
Stick Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Lesson 5-4: How to Get Better Layout Density with Node
Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
Lesson 5-5: How to Estimate Area . . . . . . . . . . . . . . . . . . . . 5-39
Lesson 5-6: How to Calculate Resistance. . . . . . . . . . . . . . . 5-49
Lesson 5-7: How to Convert a Stick Diagram to a Layout
Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59
Lesson 5-8: How to Draw Layout with a Standard Cell
Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67
Lesson 5-9: How to Draw Layout to Meet Layout
Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73
Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-80
CMOS 1 Lesson 5-1: How to Identify a Transistor on the IC Cross Section
Lesson 5-1:
How to Identify a Transistor on the
IC Cross Section
Lesson 5-1: How to Identify a Transistor on the IC Cross Section CMOS 1
Lesson 5-1 Overview
Introduction The objective of creating layout drawings is to create the die for the
IC, so it is important to understand how your work affects the die.
Objective In this lesson, you will learn how your layout drawing affects the
creation of the die for the IC.
Topic Page
What Is a Cross Section? . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Layers of the Transistor Cross Section . . . . . . . . . . . . . . . . 5-6
Layers of the Die Cross Section . . . . . . . . . . . . . . . . . . . . . . 5-7
What Is a Diode? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
How Is a Transistor Turned On or Off? . . . . . . . . . . . . . . . . 5-10
What Is a Cross Section?
Introduction In order to understand how the p-type and n-type transistors
function, it is necessary to look at the transistor cross section.
Denition A cross section is formed when you slice open an object and look at
the cut edge.
Analogy Think of a cake as the IC. When you look at the top of the cake you
see only the top layer, the frosting. To see what makes up the cake,
you have to slice it open. After slicing the cake open, you see that it
is made up of many layers of different types of cake, lling, and
frosting. The same is true when you slice an IC.
The die is made up of many layers of different materials that are used
to achieve the various functions an IC is capable of. The following
is the cross section of an n-type and a p-type transistor.
Cake Cross Section Cake
p-type transistor n-type transistor
Layers of the Transistor Cross Section
Introduction The p-type and n-type transistors are made of different diffusion
material, so their cross section drawings are different.
P-Type Transistor The layers of the p-type transistor are as follows:
N-Type Transistor The layers of the n-type transistor are as follows:
Epitaxial
Nwell
Polysilicon
S/D (Boron)
Nwell Tap
Gate Oxide
S/D (Boron)
Wafer
(Arsenic)
Epitaxial
Polysilicon
S/D (Arsenic)
Substrate Tap
Gate Oxide
S/D (Arsenic)
Wafer
(Boron)
Layers of the Die Cross Section
Introduction A complete IC is created by accurately fabricating many layers of
materials.
Fabrication Process The process begins with a pure silicon ingot cylinder 8 inches in
diameter and about 2-3 feet long. The ingot is sliced into thin wafers
creating circular disks (like a CD). The wafers, also known as
substrate, are the foundation of ICs.
Layers The layers on different die may vary with the fabrication process
used to create the die. The following is a typical layering of the
materials on a die.
1. Epitaxial: higher resistance than the substrate, or wafer
2. Nwell: provides a collection of electrons for the p-type
transistors to sit in
3. Source/Drain: arsenic for n-diffusion S/D, and boron for
p-diffusion S/D.
4. Gate Oxide (gox): thin layer below gates
5. Polysilicon: for the gates and minimal routing
6. Field Oxide (fox): thick layer to insulate different layers
7. Contact: hole in the eld oxide so the Metal1 can make a
connection to polysilicon or diffusion
8. Metal1: rst layer of aluminum for interconnect
9. Field Oxide: same as above
10. Via 1: hole in the eld oxide so the Metal2 can make a
connection to Metal1
11. Metal2: second layer of aluminum for interconnect
12. Field Oxide: same as above
13. Repeat 10-12 for each metal layer in the process
14. Passivation: oxide to insulate the die
What Is a Diode?
Introduction Inherent in the fabrication of the CMOS transistor is the creation of
a parasitic diode.
Denition Adiode is a semiconductor device that allows current to ow in one
direction only.
A diode is created when the p-type and n-type diffusions physically
touch. Diodes can be
G intentional: purposely added to the circuit to function as an
Electro-static Discharge (ESD) device
G parasitic: occurring naturally when p-type and n-type materials
touch
The normal operating condition of a diode in CMOS is reverse
biased, which prevents electrical current from owing between
opposite polarity diffusions when they are abutting.
Parts of a Diode The terminals of a diode are the anode and the cathode.
G The anode is the p-type diffusion.
G The cathode is the n-type diffusion.
continued...
+ +
+ +
+ +
- - -
- - -
- - -
Anode Cathode
What is a Diode? (continued)
Example In the reverse biased diode, current does not ow. However, in the
forward biased diode, the current ows unrestricted.
Parasitic Diodes in an
Inverter
There are ve parasitic diodes in an inverter, as shown in the
following diagram.
Reverse Biased Diodes Forward Biased Diode
Nwell
Epitaxial
How Is a Transistor Turned On or Off?
Introduction Applying a logical 1 to an n-type transistor, or a logical 0 to a p-type
transistor, turns the transistor on and allows current to ow from the
source to the drain. In a Field Effect Transistor (FET), the current
never ows between the gate and the epitaxial layer. However, there
is a predictable eld effect on the region immediately below the
gate, between the source drain, so that current can be blocked or ow
between the source and drain.
Process Apply a logical 1 to the n-type and p-type transistors as follows:
continued...
Applying a Logical 1
N-Type P-Type
A positive electrical charge is
applied to the gate.
A positive electrical charge is
The positive charge at the gate
repels the positively charged ions
in the epitaxial below the gate,
creating an inversion layer.
The positive charge at the gate
attracts the negatively charged
ions in the n-well below the gate,
blocking the current ow.
The current can now ow freely
The current cannot ow between
the source and drain.
Nwell
Epitaxial
1
How Is a Transistor Turned On or Off? (continued)
Process (continued) Apply a logical 0 to the n-type and p-type transistors as follows:
Memory Aid The positive and negative ions attract and repel as follows:
Applying a Logical 0
N-Type P-Type
A negative electrical charge is
A negative electrical charge is
The negative charge at the gate
attracts the positively charged
ions in the epitaxial, blocking the
current ow.
The negative charge of the gate
repels the negatively charged ions
of the n-well below the gate,
creating an inversion layer.
The current cannot ow between
the source and drain.
The current can now ow freely
Ion Charge Ion Charge Action
+ + Repel
+ - Attract
- - Repel
Nwell
Epitaxial
0
CMOS 1 Lesson 5-2: How to Identify Process Design Rules on the Transistor Cross Section
Lesson 5-2:
How to Identify Process Design Rules on the
Transistor Cross Section
Lesson 5-2: How to Identify Process Design Rules on the Transistor Cross Section CMOS 1
Lesson 5-2 Overview
Introduction To ensure that transistors on the die are fabricated correctly, a set of
process-specic design rules must be followed. Your layout
drawings directly affect the fabrication of the die.
Objective In this lesson, you will learn to identify some of the design rules on
the IC cross section.
Topic Page
What Is a Design Rule? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Basic Process Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
How Are Process Design Rules Identied on the Transistor
Cross Section? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
What Is a Design Rule?
Introduction To avoid unwanted results in the fabrication of an IC, certain
process-specic design rules must be followed when drawing
layout.
Denition The process design rules are the minimum allowable drawn
dimensions. These rules affect the x and y dimensions of layout not
the depth/vertical dimension. The minimum dimensions are dened
by
G the smallest geometry and spacing that can accurately be
fabricated
G the smallest geometry and spacing that maintains electrical
isolation and/or functionality
G the minimum overlap of two materials
How to Avoid Design
Violations
To avoid these process design violations, rules must be followed
when drawing the layout. What you draw directly affects what is
created on silicon.
Basic Process Design Rules
1. N+ and P+ Diffusion A. Minimum Width S/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0
B. Minimum Spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0
2. Polysilicon A. Minimum Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0
B. Minimum Spacing of Stacked Gates . . . . . . . . . . . . . . . . 3.0
C. Field Polysilicon to Diffusion Separation . . . . . . . . . . . . 0.0
D. Polysilicon End Cap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0
3. Metal Contacts A. Minimum Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 x 2.0
C. Minimum Diffusion/Polysilicon Overlap . . . . . . . . . . . . 2.0
D. Minimum Spacing to Active Gate . . . . . . . . . . . . . . . . . . 2.0
4. Metal A. Minimum Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0
C. Minimum Metal Overlap of Contact . . . . . . . . . . . . . . . . 0.0
5. Nwell A. Nwell Spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0
B. Nwell Overlap of Diffusion . . . . . . . . . . . . . . . . . . . . . . 3.0
C. Nwell Spacing to Diffusion . . . . . . . . . . . . . . . . . . . . . . . 4.0
D. Minimum Nwell Width . . . . . . . . . . . . . . . . . . . . . . . . . 10.0
How Are Process Design Rules Identied on the Transistor
Cross Section?
Introduction Some of the basic process design rules can be identied in a cross
section of the layout.
Example In the following example, the following rules can be identied:
1. minimum metal overlap of contact
2. minimum polysilicon width
3. contact width
4. minimum S/D width
5. minimum diffusion spacing
6. minimum Nwell width
4. min S/D
Epitaxial
Nwell
2. min polysilicon
5. min diffusion
3. contact
1. metal overlap
6. min nwell width
width
of contact
width spacing
width
CMOS 1 Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram
Lesson 5-3:
How to Convert a Transistor-level Schematic
to a Stick Diagram
Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram CMOS 1
Lesson 5-3 Overview
Introduction Critical to a good design, is creating a good plan before drawing any
layout.
Objective In this lesson, you will learn how to create a stick diagram for
transistor placement and connections.
Topic Page
What Is a Stick Diagram? . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
Legend for a Stick Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
Series and Parallel Transistors in a Stick Diagram . . . . . . . 5-23
How Is a Stick Diagram Created? . . . . . . . . . . . . . . . . . . . . 5-24
Lab 5-3.a: Create a Stick Diagram . . . . . . . . . . . . . . . . . . . . 5-26
How Is the Width of a Layout Drawing Estimated from a
Stick Diagram? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
Lab 5-3.b: Estimate the Width of a Layout Drawing from a
Stick Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
What Is a Stick Diagram?
Introduction To help create an optimal layout, rst create a stick diagram. This
diagram is a shorthand representation of what your layout will look
like. This diagram helps you plan where to place transistors to
achieve the maximum density and best performance.
Denition A stick diagram is a technique to generate a free-form, topological
plan of a circuit for layout without regard to the actual geometry
sizing or process design rules. Graphical symbols representing the
transistors are drawn relative to each other and are connected
together by other symbols representing the interconnect mask
layers.
Note: In layout, transistors are formed by crossing polysilicon
and diffusion.
Parts of a Stick Diagram The stick diagram equivalents of a transistor-level schematic are as
follows:
Practice How many transistors are in the following stick diagram?
Transistor-level Stick Diagram
S/D (p-type)
Gate (polysilicon)
Schematic
S/D (n-type)
Gate (polysilicon)
Legend for a Stick Diagram
Introduction Stick diagrams are best drawn in color but can be drawn in black and
white using different patterns for the lines.
Legend The legend for the different symbols is as follows:
Example The INVERTER schematics and stick diagram are as follows:
Layer Symbol Color
P Diffusion
N Diffusion
Polysilicon
Metal
Metal Contacts
N-Well
X
Vcc
Vss
OUT
A
OUT A
Series and Parallel Transistors in a Stick Diagram
Introduction When converting transistor-level schematics to stick diagrams,
transistors will often be drawn in series or parallel.
Series Transistors Series transistors are drawn with one path from Vcc/Vss to the
output node, as follows:
Parallel Transistors Parallel transistors are drawn with multiple paths from Vcc/Vss to
the output node, as follows:
OUT
A
B
Vcc N1 OUT
A B
OUT
A
B
Vss OUT Vss
A B
How Is a Stick Diagram Created?
Introduction There are some well-dened methods for creating stick drawings.
By following the steps outlined below, you can achieve a good
layout for simple schematics.
Procedure Create a stick drawing as follows:
Guidelines G When creating parallel transistors in the stick diagram, minimize
the number of connections to the output node.
G Both S/D of a transistor cannot be connected to the same node.
G All common nodes must be connected.
G When polysilicon crosses diffusion a transistor is always created.
G Do not connect to S/D regions with polysilicon.
G All metal connections to polysilicon and diffusions must have at
least one contact.
Step Action
1. Determine how many transistors are needed, from the
# of transistors = 2 (# of inputs)
2. Draw the transistor-level schematic of the logic-level
schematic.
3. Convert the transistor-level schematic.
a. Draw horizontal lines for the p-type and n-type diffusion.
For this class, plan to have the p-type devices above the
n-type devices.
b. Draw vertical polysilicon lines to create the correct number
of gates. Label the gates.
c. Trace the transistor-level schematic and label the stick
diagram to match.
d. Make sure that all S/D nodes of each transistor match
between the transistor-level schematic and the stick
diagram.
How Is a Stick Diagram Created? (continued)
Example Use the procedure described and create a stick diagram for the
Inverter.
Step Action
# of transistors = 2 (1) = 2
schematic.
a. Draw horizontal lines for the p-type and n-type diffusion.
n-type devices.
diagram to match.
A OUT
A
OUT
A
Vcc
Vss
OUT
Lab 5-3.a: Create a Stick Diagram
Introduction Now that you know how to draw stick diagrams for transistor-level
schematics, you will draw a stick diagram for the following
exercises.
1. Using the procedure described, create a stick diagram for a 2-input NOR
function.
2. Using the procedure described, create a stick diagram for a 2-input NAND
function.
3. Using the procedure described, create a stick diagram for a 3-input NOR
function.
4. Using the procedure described, create a stick diagram for a 3-input NAND
function.
Step Action
# of transistors = 2 (# of inputs)
schematic.
a. Draw horizontal lines for the the p-type and n-type
diffusion.
n-type devices.
diagram to match.
d. Make sure that all S/D nodes of each transistor match
between the transistor-level schematic and the stick
diagram.
5. Using the procedure described and the following logic-level schematic, draw the
stick diagram.
stick diagram.
stick diagram.
stick diagram.
stick diagram.
C
OUT
A
B
A
B
OUT
C
D
IN OUT
A
OUT
B
A
B
C
OUTA OUTB
stick diagram.
stick diagram.
stick diagram.
stick diagram.
OUTB
A
B
C
OUTA
A
C
B
OUT
A
B
C
OUT
OUT
B
C
A
Stick Diagram?
Introduction To be able to calculate an area estimation, you must be aware of the
layout design rules, and you must have a stick diagram.
Procedure Determine the width of your layout as follows:
continued...
Step Action
1. Starting at one end of the stick diagram, add up the minimum
width and spacing requirements for all objects for the p-type
transistors in the diagram. This gives you the width for the
p-type transistors.
2. Repeat the above step for all objects for the n-type transistors.
This gives you the width of the n-type transistors.
3. Compare the width of the p-type and n-type transistors. The
larger value is the estimated width for the layout drawing.
Stick Diagram? (continued)
Example Use the procedure to estimate the width of the Inverter layout
drawing.
Step Action
1. Starting at one end of the stick diagram, add up the minimum
width and spacing requirements for all objects for the p-type
transistors in the diagram. This gives you the width for the
p-type transistors.
2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 = 18
2. Repeat the above step for all objects for the n-type transistors.
This gives you the width of the n-type transistors.
2 + 2 + 2 + 2 + 2 + 2 + 2 = 14
larger value is the estimated width for the layout drawing.
Since 18 is larger than 14, this cell is 18 wide.
Vcc
Vss
OUT
A
2 2 2 2 2 2 2 2 2
Vcc
Vss
OUT
A
2 2 2 2 2 2 2
Lab 5-3.b: Estimate the Width of a Layout Drawing from a
Stick Diagram
Introduction Now that you know how to estimate the width of a layout drawing
from a stick diagram, you will use your previous stick diagrams to
estimate the layout drawing width and compare this value to the
actual layout drawing width.
1. Use the stick drawing and layout drawing you drew for the 2-input NOR and
3-input NAND. Complete the following exercises for both logic functions.
a. Use your stick drawing and estimate the width of the layout drawing.
b. Measure the actual width of the layout drawing.
Compare the estimated value to actual value. Are the values close?
Step Action
1. Starting at one end of your stick diagram, add up the minimum
width and spacing requirements for all of the objects for the
p-type transistors in the diagram. This gives you the width for
the p-type transistors.
2. Repeat the above step for all of the objects for the n-type
transistors. This gives you the width of the n-type transistors.
larger value is the width of your cell.
CMOS 1 Lesson 5-4: How to Get Better Layout Density with Node Sharing
Lesson 5-4:
How to Get Better Layout Density with Node
Sharing
Lesson 5-4: How to Get Better Layout Density with Node Sharing CMOS 1
Lesson 5-4 Overview
Introduction Arranging transistors so the common nodes share the same S/D
diffusion region helps to gain better density and performance.
Objective In this lesson, you will learn to arrange the transistors so common
nodes share the same S/D diffusion region whenever possible.
Topic Page
What Is Node Sharing? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
How Is Node Sharing Achieved? . . . . . . . . . . . . . . . . . . . . . 5-36
Lab 5-4: Use Node Sharing to Increase Density . . . . . . . . . 5-38
What Is Node Sharing?
Introduction In the attempt to draw more transistors in less area, it is often
necessary for common S/D nodes to share the same diffusion region.
Denition Node sharing is touching or overlapping of same-node S/D
terminals from two different transistors. By touching or overlapping
the common terminal, the two transistors take up less room than if
the two transistor are spaced away from each other according to the
diffusion to diffusion spacing process design rule.
Example Two p-type transistors that share a common node can be drawn so
that the common node of the transistors overlaps, thus taking up less
room, as shown in the following graphic.
Overlapping S/D
S/D Diffusion Terminals
Diffusion Terminals
with Design Rule Spacing
ZING ZANG
Vcc
Vcc Vcc
ZING ZANG
How Is Node Sharing Achieved?
Introduction Before creating a layout drawing, you can determine which
transistors should share nodes and rearrange the transistors in the
stick diagram.
Procedure Find the nodes that can be shared, as follows:
continued...
Step Action
1. Identify the internal nodes on the transistor-level schematic and
label them with unique names.
2. Identify the internal nodes on the stick diagram and label each
internal node with the same name you gave it on the
3. Look at the n-type and the p-type transistors on the stick
diagram and identify any common nodes that are not drawn
next to each other.
4. Try to rearrange the common nodes so that they are next to
each other. This arrangement
G reduces the breaks in diffusion
better density
G minimizes routing
shorter wire lengths
fewer routing lines
How Is Node Sharing Achieved? (continued)
Example Use the procedure to achieve node sharing for the following
Step Action
1. Identify the internal nodes on the transistor-level schematic and
label them with unique names.
2. Identify the internal nodes on the stick diagram and able each
internal node with the same name you gave it on the
3. Look at the n-type and the p-type transistors on the stick
diagram and identify any common nodes that are not drawn
next to each other.
4. Try to rearrange the common nodes so that they are next to
each other.
A
B
ZING OUT
A
B
ZING
N1
OUT
OUT
ZING
B A
N1
A B ZING
N1 OUT
Lab 5-4: Use Node Sharing to Increase Density
Introduction Now that you know how to achieve node sharing, you will use the
node sharing procedure to draw the stick drawings for the following
logic-level schematics.
Use the node-sharing procedure to create a layout drawing for each of the following
logic-level schematics.
1. a.
b.
c.
d.
e.
A
B
Out
Do It
N17
PHZ
E
Out
D
C
BING
BANG
BOOM
ZAP
A
B
CMOS 1 Lesson 5-5: How to Estimate Area
54
Lesson 5-5:
How to Estimate Area
Lesson 5-5: How to Estimate Area CMOS 1
Lesson 5-5 Overview
Introduction A very important aspect in the layout of any design is the area
utilized by the transistors and the interconnect.
Objective In this lesson, you will learn to calculate area values.
Topic Page
Area Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41
Lab 5-5.a: Calculate Area . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42
Units of Measure Conversion . . . . . . . . . . . . . . . . . . . . . . . 5-43
Lab 5-5.b: Convert Units of Measure . . . . . . . . . . . . . . . . . 5-44
Average Area per Transistor Calculation . . . . . . . . . . . . . . . 5-46
Lab 5-5.c: Calculate the Average Area per Transistor . . . . . 5-47
Area Calculation
Introduction Area estimation is used to forecast the space needed for your circuit
which is an important part of planning.
Calculation Area is the actual space that the layout will occupy. There is a simple
formula to determine area.
The formula to calculate area is:
area = width x length
area = X * Y
If X = 4 inches and Y = 2 inches, then the area is calculated as
follows:
Area = 4 in * 2 in = 8 in
2
Area Units The units for area are square units. If the length and width are
measured in microns (), then the area units are square microns (
2
).
Y
X
Lab 5-5.a: Calculate Area
Introduction Now that you know the formula to calculate area, you will complete
the following area calculations.
1.
Calculate the area, given the following width and length values.
a. 20 x 100 =
b. 85 x 34 =
c. 56 x 135 =
d. 97 x 210 =
2.
Given the area and one of the sides, calculate what the other side must be.
a. 58 x ____ = 5626
2
b. 13 x ____ = 312
2
c. 56 x ____ = 1900
2
Units of Measure Conversion
Introduction It is important to know how to convert between mils and microns
and vice versa, because both units of measure are used in chip
design. The micron is the unit of measure in a transistor layout.
However, the mil is the unit of measure when dealing with the
functional unit, unit, or chip level.
Units of Measure The units of measure are as follows:
micron () = 1,000,000th of a meter
mil = 1,000th of an inch
Conversion G To convert mils to microns, multiply by 25.4 /mil
mil * (25.4 /mil) =
Example:
2 mil * (25.4 /mil) = 50.8
G To convert microns to mils, divide by 25.4 mil/
/ (25.4 mil/) = mil
Example:
28 / (25.4 mil/) = 1.1 mil
G To convert square mils (m
2
) to square microns (
2
), multiply by
645.16
2
/m
2
m
2
* (645.16
2
/m
2
) =
2
Example:
120 m
2
* (645.16
2
/m
2
) = 77419.2
2
Rounding All results must be rounded to two digits to the right of the decimal
point.
Lab 5-5.b: Convert Units of Measure
Introduction Now that you know how to convert the units of measure for layout
drawings, you will complete the following unit conversions.
1. Fill in the correct values for the micron column in the following table:
2. Fill in the correct values for the mil column in the following table:
3. Fill in the correct values for the mil
2
column in the following table:
mil Conversion micron
1 * 25.4 =
354 * 25.4 =
443 * 25.4 =
138 * 25.4 =
micron Conversion mil
25.4 / 25.4 =
5435 / 25.4 =
8943 / 25.4 =
138 / 25.4 =
mil
2
Conversion micron
2
1 * 645.16 =
123 * 645.16 =
321 * 645.16 =
645 * 645.16 =
4. Fill in the correct values in the mil
2
column in the following table:
Device Area
(mil
2
)
# of
Devices
Area/Transistor
12 8 =
10.4 7 =
18.3 11 =
14.7 15 =
33 23 =
Average Area per Transistor Calculation
Introduction The average area per transistor or density can be calculated with a
simple formula. This information will be used in planning.
Calculation The average area per transistor is a value used to compare different
layout drawings; the smaller the values is the better. To calculate the
area per transistor, you must rst determine the total area of the
transistors.
total_area = X * Y
Next, use the total area value in the following formula to calculate
the density.
density = total_area / number_logic-level_trans
Example If the layout of a circuit contains 25 transistors and is 100 by 100,
then the total area and density values are calculated as follows:
total_area = 100 * 100 = 10000
2
density = 10000
2
/ 25 transistors = 400
2
/transistor
Lab 5-5.c: Calculate the Average Area per Transistor
Introduction Now that you know how to calculate the average area per transistor,
or the density for layout drawings, you will complete the following
density calculations.
1. Given the following information, complete the calculation.
a. If the layout of a circuit contains 20 transistors and is 100 by 90, then what
are the total area and density values?
b. If the layout of a circuit contains 75 transistors and is 100 by 90, then what
are the total area and density values?
c. If the total area of the layout of a circuit is 350
2
and the average area per
transistor is 50
2
, then how many transistors are in the layout?
CMOS 1 Lesson 5-6: How to Calculate Resistance
Lesson 5-6:
How to Calculate Resistance
Lesson 5-6: How to Calculate Resistance CMOS 1
Lesson 5-6 Overview
Introduction A very important aspect in the layout of any design is the resistance
of the interconnect.
Objective In this lesson, you will learn to calculate resistance.
Topic Page
What Is Resistance? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51
Lab 5-6.a: Calculate Resistance Values . . . . . . . . . . . . . . . . 5-53
How Is Sheet Resistance Calculated? . . . . . . . . . . . . . . . . . 5-56
Lab 5-6.b: Calculate Sheet Resistance . . . . . . . . . . . . . . . . . 5-58
What Is Resistance?
Introduction Resistance has a direct and measurable effect on the performance of
a circuit. It can be either intentional or parasitic. You must be able to
increase and decrease the resistance in a circuit to obtain the correct
circuit functionality.
Denition Resistance is the opposition of current ow. Each material has a
different resistive value that represents how much that material
opposes current ow.
The unit of measure for resistance is the ohm ().
Resistors are drawn to show resistance. The orientation of the
resistor does not affect the resistor.
The effects of resistance in series or parallel interconnect are
described below.
Series Resistance
Calculation
The current has only one path to follow, so the total current ows
through all of the resistors (R
1
and R
2
... and R
n
).
The total resistance is equal to the sum of the individual resistances.
For the above resistors the total resistance is as follows:
continued...
R
Total
R
1
R
2
R
n
+ + + =
current current
current
R1=20 R
2
=40
R
Total
20 40 60 = + =
What Is Resistance? (continued)
Parallel Resistance
Calculation
With parallel resistors, the current has more than one path to follow,
and it follows the path of least resistance: through the smallest
resistor.
The total resistance will be less than the smallest resistor.
In the following example, since R
1
has less resistance then R
2
, more
current will ow through R
1
than R
2
.
For the above resistors the total resistance is as follows:
R
total
1
1
R
1
------
1
R
2
------
1
R
3
------
1
R
n
------ + + + +

--------------------------------------------------------------- =
current
R
1
=20
R
2
=40
current
current current
R
total
1
1
20
----------
1
40
---------- +

----------------------------------- 13.33 = =
Lab 5-6.a: Calculate Resistance Values
Introduction Now that you know how to calculate the total resistance, you will
calculate the resistance in the following exercises.
1. Given the following resistors, complete the exercises.
a. Are these resistors in series or parallel?
b. Calculate the total resistance.
R
1
= 30
R
1
= 40 R
1
= 50
R
1
= 60
R
2
= 65
R
3
= 105
R
1
= 85
R
2
= 620
R
3
= 330
R
4
= 100
R
5
= 1000
R
1
= 10
R
2
= 20
R
3
= 30
R
1
= 100
R
2
= 100
R
1
= 1000
R
2
= 880
R
3
= 316
How Is Sheet Resistance Calculated?
Introduction In order to determine if routing has met the engineering
specications, it is often important to know how much resistance the
routing has. To calculate this, you must know the ohms per square.
Denition The sheet resistance or ohms per square or RHO is the electrical
resistance per square of a given material.
Some examples of values are as follows:
G S/D Diffusion 30/square
G Polysilicon 25/square
G Metal 1 .03/square
The dimensions of a square can be 3 x 3 or 20 x 20, but each square
of the same material will have the same amount of resistance. Each
of the following shapes represent one square of diffusion, so both are
30 ohms.
Practice Which of the above materials has the least resistance?
continued...
3 x 3 20 x 20
30 30
How Is Sheet Resistance Calculated? (continued)
Procedure Calculate the sheet resistance as follows.
Example A piece of polysilicon is 2 wide and 30 long. If polysilicon has a
sheet resistance of 25/square, then how much resistance does this
piece of polysilicon have?
Step Action
1. Calculate the number of squares.
Number of squares = S
T
= length / width
2. Calculate the total resistance; multiply the number of squares
by the sheet resistance.
Total Resistance = R
T
= S
T
* Sheet Resistance
Step Action
1. Calculate the number of squares.
Number of squares = S
T
= 30 / 2 = 15 squares
2. Calculate the total resistance; multiply the number of squares
by the sheet resistance.
Total Resistance = R
T
= S
T
* Sheet Resistance
15 squares * 25/square = 375
2
30
Lab 5-6.b: Calculate Sheet Resistance
Introduction Now that you know how to calculate sheet resistance, you will
calculate the sheet resistance, width, and length in the following
exercises.
1. An engineer wants a 5000 diffusion resistor that is 10 wide. If diffusion has a
sheet resistivity of 30/square, how long must the resistor be?
2. If polysilicon has a sheet resistivity of 22.3/square, what is the total resistance
of a polysilicon line that is 300 long and 2.5 wide?
3. An inverter needs to have some delay added to its output. If polysilicon has a
sheet resistivity of 30/square, how much polysilicon should be added if the
polysilicon width is 20 and you need 30 of resistance?
4. A Metal1 line is 2.4 wide and runs 44000 across the chip. If Metal1 has a sheet
resistivity of 0.084/square, what is the total resistance of the node?
CMOS 1 Lesson 5-7: How to Convert a Stick Diagram to a Layout Drawing
56
Lesson 5-7:
How to Convert a Stick Diagram to a
Layout Drawing
Lesson 5-7: How to Convert a Stick Diagram to a Layout Drawing CMOS 1
Lesson 5-7 Overview
Introduction The nal step of the layout design process is actually create a layout
drawing.
Objective In this lesson, you will learn how to convert the stick diagram, your
plan, into a layout drawing.
Topic Page
What Is a Layout Drawing? . . . . . . . . . . . . . . . . . . . . . . . . . 5-61
What Is Transistor Size? . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62
How Is a Stick Diagram Converted to a Layout Drawing? . 5-63
Lab 5-7.a: Convert a Stick Diagram to a Layout . . . . . . . . . 5-64
Visually Verifying a Layout Drawing . . . . . . . . . . . . . . . . . 5-65
Lab 5-7.b: Visually Verify a Layout Drawing . . . . . . . . . . . 5-66
What Is a Layout Drawing?
Introduction All prior information in this class has prepared you to create a layout
drawing. The stick drawing is your actual plan for drawing your
layout.
Denition A layout drawing is the actual geometries that will create the
transistors and routing on the IC die.
G Transistors are created with diffusion for the source and drain
regions and with polysilicon for the gate region.
G Routing is created with metal, polysilicon, and contacts.
Example The following graphics illustrate the logic-level schematic,
transistor-level schematic, stick diagram, and layout drawing of an
Inverter.
Vcc
Vss
OUT
A
Vcc
Vss
A
OUT
A
OUT
Logic-level Schematic Transistor-level Schematic
Stick Diagram
Layout Drawing
What Is Transistor Size?
Introduction The transistor sizes are established by the engineering design
specications.
Denition The transistor size is determined by the z/l ratio which is the gate
width and length. The n-type transistors and p-type transistors have
different z/l ratios.
G z = gate width
G l = gate length
The larger the ratio...
G the more energy the gate uses
G the more devices it can drive
The z/l values are drawn on the logic-level schematic as follows.
When there is only one number, the l value is assumed to be the
default for the design process.
Example The following transistor layout shows the z and l dimensions.
10/3
5/3
16
8
l = length
z= width
diffusion
polysilicon
Transistor-level Layout Drawing
Schematic
How Is a Stick Diagram Converted to a Layout Drawing?
Introduction Once you have a stick diagram, the layout drawing can easily be
created.
Procedure The steps to convert a stick drawing to a layout drawing are as
follows:
Example Use the procedure to convert the Inverter stick diagram to a layout
drawing.
Step Action
1. Get an idea of what the layout will look like by fattening the
lines on your stick diagram. Do this by creating rectangles of the
correct minimum width for each material.
2. Redraw the stick diagram as a layout drawing, labeling all
nodes. At this time, do not be concerned about the spacing
process design rules.
Step Action
nodes.
Vcc
Vss
Out
A
Vcc
Vss
A OUT
Lab 5-7.a: Convert a Stick Diagram to a Layout
Introduction Now that you know the process to convert a stick diagram to a layout
drawing, use the stick diagrams you drew in lab 5-3.a to draw the
layout drawing in the following exercises.
1. Use a stick diagram and the following procedure to create the layout drawing that
reects the following logic functions. Draw all materials to the correct minimum
width process design rules, however do not be concerned about the spacing
design rules at this time.
a. 2-input NOR
b. 2-input NAND
c. 3-input NOR
d. 3-input NAND
2. Use the design rules provided by your instructor and draw the layout drawings for
the following logic functions with the correct width and spacing design rules.
a. 2-input NOR
b. 2-input NAND
c. 3-input NOR
d. 3-input NAND
Step Action
nodes. At this time, do not be concerned about the spacing
process design rules.
Visually Verifying a Layout Drawing
Introduction To ensure that layout drawings meet the process design rule
specications and template requirements, you must verify all layout
drawings.
Checklist To verify that a layout drawing meets the process design rules,
complete the following checklist against your layout.
Check
1. Polysilicon head minimum size: 6 x 6
2. Diffusion head minimum size: 6 x 6
3. Metal pitch: 5
4. End cap: 2
5. Tap density: 1/cell
6. Contact to gate spacing: 2
7. Width and spacing process-specic design rules
8. Template width and spacing requirements
Lab 5-7.b: Visually Verify a Layout Drawing
Introduction Now that you know how to visually verify a layout drawing with the
simplied process design rule checklist, you are ready to verify your
layout drawings.
1. Use the simplied process design rule checklist to verify the layout drawings your
instructor provides.
2. Use the simplied process design rule checklist to verify the layout drawings you
drew in prior labs.
CMOS 1 Lesson 5-8: How to Draw Layout with a Standard Cell Template
57
Lesson 5-8:
How to Draw Layout with a Standard Cell
Template
Lesson 5-8: How to Draw Layout with a Standard Cell Template CMOS 1
Lesson 5-8 Overview
Introduction To easily combine a layout drawing with other layout drawings, you
will use a standard cell template.
Objective In this lesson, you will learn to draw a standard cell layout drawing
to the specications of a standard cell template.
Topic Page
What Is a Standard Cell Template? ....................................... 5-69
How Is a Layout Drawing Drawn with a Standard Cell
Template? .............................................................................. 5-70
Lab 5-8: Draw a Layout Drawing with a Standard Cell
Template ................................................................................ 5-71
What Is a Standard Cell Template?
Introduction Standard cells are layout drawings that are drawn to a special set of
layout requirements, reduce the drawing time and ensuring
predictable performance. The requirements for standard cells are
often communicated with a template.
Denition A standard cell template is a graphical guide that denes the layout
design rules to create standard cells. Layout drawn to specications
of a standard cell template can occupy a large area of an IC.
Parts of a Standard Cell
Template
A typical standard cell template is as follows:
Tap
Region
Vcc
NWELL
Metal
tracks for
Inter-
connect
Vss
NAC
Region
10 m
10 m
3 m
2 m
How Is a Layout Drawing Drawn with a Standard Cell
Template?
Introduction To make sure that a layout meets the design specications, you must
follow the specications of a standard cell template.
Procedure Create a layout drawing to the specications of a standard cell
template as follows.
Example With your instructor, use the above procedure and the template
provided to create a layout drawing for an Inverter.
Step Action
1. Use the correct standard cell template.
2. Transfer the template specications to your drawing.
3. Add the layout to your drawing.
10/2
8/2
IN OUT
Lab 5-8: Draw a Layout Drawing with a Standard Cell
Template
Introduction Now that you know what a standard cell template is, you will use
one to draw a standard cell layout.
1. Given the following logic-level schematics, calculate how many transistors are
needed for each layout function.
2. Use the template provided by your instructor to draw a standard cell layout
drawing for the following logic functions.
a. Inverter
b. 2-input NOR
c. 3-input NAND
d. Complex logic
10/2
8/2
IN OUT
A
B
OUT
12/1
6/1
C
D
OUT
12/1
6/1
E
OUT
12/1
8/1
F
G
H
J
CMOS 1 Lesson 5-9: How to Draw Layout to Meet Layout Restrictions
58
Lesson 5-9:
How to Draw Layout to Meet Layout Restrictions
Lesson 5-9: How to Draw Layout to Meet Layout Restrictions CMOS 1
Lesson 5-9 Overview
Introduction It is often necessary to alter how a transistor is drawn due to process
or area restrictions.
Objective In this lesson, you will learn to draw transistors with multiple legs
and bent gates.
Topic Page
How Is a Transistor Drawn with Multiple Legs? . . . . . . . . . 5-75
How Is a Transistor Drawn with a Bent Gate? . . . . . . . . . . 5-77
Lab 5-9: Draw Layout to Meet Layout Restrictions . . . . . . 5-79
How Is a Transistor Drawn with Multiple Legs?
Introduction When a transistor is too long to t into the given area or the transistor
gate is too long for the maximum gate length of the process, the gate
must be broken into multiple legs.
Denition A transistor with multiple legs is a set of parallel transistors with a
total z value equivalent to the desired z value. For example, three
parallel n-type transistors each with a z/l of 10/2 is equivalent to one
n-type transistor with a z/l of 30/2.
continued...
10/2 10/2 10/2 30/2
parallel transistors equivalent single transistor equivalent
to the single transistor to the parallel transistors
How Is a Transistor Drawn with Multiple Legs? (continued)
Procedure Drawing transistors with multiple legs consists of the following:
Example 1 If z/l = 30/2 and the maximum z value is 10 then,
Number of legs = (total z) / (maximum z) = 30 / 10 = 3
Each leg is 30 / 3 = 10.
Example 2 If z/l = 30/2 and the maximum z value is 8 then,
Number of legs = (total z) / (maximum z) = 30 / 8 = 3.75
Number of legs = round (3.75) = 4
Each leg is 30 / 4 = 7.5
Step Action
1. Calculate the number of legs needed to replace a single leg
transistor as follows:
a. Divide the total z value by the maximum z value.
L1 = (total z) / (maximum z)
If L1 is a whole number, than this is the number of legs.
If L1 is not a whole number, than continue to steps b
and c.
b. Round L1 up to the next whole number to get the actual
number of legs.
# of Legs = round(L1)
c. Divide the total z value by the actual number of legs to
get the length of each leg.
New gate length = (total z) / (# of legs)
2. Draw the multiple legs of the transistor in parallel with
the new gate length.
A A A A
V
s
s
V
s
s
V
s
s
O
U
T
O
U
T
How Is a Transistor Drawn with a Bent Gate?
Introduction Some processes allow the gate of a transistor to be bent. Bending the
transistor gates can increase the layout density. Symbolic editor
CAD tools usually cannot draw bent gates; the polygon editor CAD
tools can draw bent gates.
Procedure Drawing layout with bent gates consists of the following:
Guidelines When drawing bent gates in this class, determine the total z value of
the gate as follows:
G Do not count corners when calculating the total z value.
G When both corners overlap, do not count the overlap.
continued...
Step Action
1. Calculate the total z value of the gate. (See guidelines below.)
2. Draw the layout with the bent gate.
Note: For this class, draw bends at 90.
Bent gate with overlapping corners
Overlapping corners
Count
length
Count
length
How Is a Transistor Drawn with a Bent Gate? (continued)
Example The following bent gate provides a savings of 4 in the vertical
dimension of the diffusion.
Gate length = 6 + 6 + 6 = 18
Diffusion height = 14
Diffusion height savings = 18 - 14 = 4
This bent gate provides an area savings of 4 in the vertical
dimension.
Bent
Diffusion
Metal 1
6
6
6
14
Gate
Corner
Contact
Lab 5-9: Draw Layout to Meet Layout Restrictions
Introduction Now that you know how to draw layout to meet layout restrictions,
use the template provided by your instructor to draw a standard cell
layout drawing for the following logic functions. Draw each logic
function twice; once with a bent gate and once with multiple leg
devices. The maximum z value is 8.
1. Inverter
2. 2-input NOR
3. 3-input NAND
4. Complex logic
20/2
8/2
IN OUT
A
B
OUT
12/2
10/2
C
D
OUT
20/2
12/2
E
OUT
12/2
8/2
F
G
H
J
Chapter Summary
Introduction In this chapter, you learned how transistors are created in silicon,
how to estimate area, how to calculate resistance, and how to create
a layout drawing from a stick diagram.
Summary In this chapter, you learned to do the following:
G identify a transistor and a diode on the IC cross section
G identify process design rules on the transistor cross section
G identify the parts of a stick diagram
G estimate area
G calculate resistance
G convert a stick diagram to a layout drawing
G get better layout density with node sharing
G draw layout with a standard cell template
G draw layout to meet layout restrictions
CMOS 1 Appendix A: Glossary
Intel Confidential A-1
0
Appendix A:
Glossary
Appendix A: Glossary CMOS 1
A-2 Intel Confidential
Terms
Alternating Current
(AC)
An electrical current that continuously changes in magnitude and in
direction of ow.
Aluminum The metal most often used in semiconductor processing to form the
interconnects between the devices on an integrated circuit chip.
Ampere The unit of measurement for electrical current in coulombs per
second. One ampere ows in a circuit that has one ohm resistance
when one volt is applied to the circuit.
Analog A signal that varies in amplitude continuously and without
interruption. Also called linear. Contrast with digital.
Angstrom The unit used to depict the wavelength of light or other
electromagnetic radiation. Two hundred fty-four million
angstroms equals one inch. Ten angstroms equals one nanometer.
Anode The p-type diffusion of a semiconductor diode.
Arsenic The n-type dopant commonly used for the source and drain of n-
channel MOS integrated circuits.
Base In a bipolar transistor, the terminal that controls the current ow.
Battery A source of electromotive force (voltage and current) obtained from
chemical reaction in an assembly called a cell. The voltage produced
by a fresh cell depends on the materials used, but it is usually
between one and two volts. Cells are connected in a series to obtain
a higher voltage or in parallel to obtain greater current capacity.
Binary A numbering system with only two digits, 0 and 1.
Bipolar A type of transistor where a ow of both conduction electrons and
holes determines the device characteristics.
Bi-CMOS A technology in which the advantages of bipolar transistors (speed)
and of CMOS devices (low power consumption) are combined in the
fabrication of a single IC.
Bonding Pads A square or rectangular area on the die that is used to attach the die
to the package by wire bonding.
Boron A p-type dopant commonly used for the source and drain of p-
channel MOS integrated circuits.
Capacitor A circuit element formed by placing an insulating layer between two
conducting layers. This structure is often fabricated in the
manufacturing of integrated circuits.
Cathode The negative electrode of a semiconductor diode.
Circuit 1. A complete path that allows electrical current from one
terminal of a voltage source to the other terminal.
2. An interconnection of electrical or electronic components to
accomplish a specic function.
Complementary Metal
Oxide Semiconductor
(CMOS)
A semiconductor that has low power drain. It is produced by an
integrated-circuit fabrication technique using both P-channel and
N-channel MOS transistors. Each transistor is made of three
elements: gate, drain, and source.
Computer-Aided-
Design (CAD)
A design technique (using a computer and special software) that can
be used in the design of a product and in the verication of its
performance by simulation.
Conductance A measure of the ease of conducting current. The reciprocal of
resistance in DC circuits or of the real part of impedance in AC
circuits. Expressed in mho (ohm spelled backwards.)
Conductivity The inverse of resistivity.
Conductor A substance through which electrons ow with relative ease.
Contact A vertical hole cut into the eld oxide and allowing connection of
two vertical materials of an IC.
Current The movement of electrons through a circuit. Current is measured in
amperes.
Die A single piece of silicon cut from a wafer and containing the
complete device.
Dielectric The insulating material between the plates of a capacitor.
Diffusion 1. Another name for the impurities implanted into silicon
devices.
2. The movement of particles away from regions of high
concentration (caused by the random thermal motion of
atoms and molecules).
Digital Representing information in discrete or quantized form or in the
form of pieces such as bits or digits.
Diode A semiconductor device made of n+ and p+ diffusions abutting. The
diode is used to control current ow.
Direct Current (DC) Current that ows in only one direction, usually without change in
magnitude.
Doping A process used to change the electrical characteristics of the wafer
by ion implantation (diffusion).
Drain In a MOS transistor, the terminal to which the carriers ow.
Electron The basic atomic particle having a negative charge.
Epitaxial (Epi) The deposition of a single crystal layer on the silicon wafer. This is
the rst layer added to the new wafer and usually has a higher
resistance than the raw wafer.
Gate In a MOS transistor, the terminal that controls the current ow.
Hole A vacancy within the valence band of a semiconductor material
caused by the deciency of an electron. It appears as if it were a
moving positive charge.
Ingot A cylindrical crystal grown from polysilicon material that is sliced
into wafers.
Integrated Circuit (IC) A tiny slice or chip of material on which a complex electrical circuit
is etched or imprinted. ICs are made from semiconductor material
and work according to semiconductor physics.
Layout A process in which engineering schematics are transposed into
graphic symbols that will by used to make a mask.
Micron () A unit of length equal to one millionth of a meter.
Microprocessor The central processor of a computer fabricated as an integrated
circuit. It performs semi-intelligent functions based on software
instructions. Fundamentally, a microprocessor is a hardware device
that can be electrically rewired by using software instructions. It
is considered the brain of a circuit or a computet.
Ohm () The unit of electrical resistance. A circuit component has a
resistance of one ohm when one volt applied to the component
produces a current of one ampere.
Oxidation The process of growing a layer of silicon dioxide onto the wafer.
Passivation A process in which a thin layer of nitride is deposited over the metal
layer to protect it.
Parallel Circuit Current path that divides from a single source into two or more
separate paths that will later rejoin.
Phosphorus The n-type dopant commonly used for the emitter diffusion in
standard bipolar integrated-circuit technology and for the n-channel
source and drain of MOS integrated circuits.
Photo Resist A light sensitive material used during the photolithography process.
Polycrystalline Silicon
(Polysilicon)
Silicon composed of many (poly) crystals. Raw silicon comes in
ingots of poly prior to crystal growth. Polysilicon may be deposited
accidentally during epitaxial deposition by depositing it too fast or
at too low a temperature. Chemical vapor deposition (CVD) of
polysilicon usually occurs on a layer of silicon dioxide.
Programmable Read
Only Memory (PROM)
A type of electronically programmable semiconductor memory
device which is programmed after manufacture, but whose contents
are unalterable once programmed.
Random Access
Memory (RAM)
In computer or digital systems, a memory system in which any
memory location can be directly accessed as easily and as quickly as
any other. The contents of random access memory can be readily
changed.
Read-Only Memory
(ROM)
A semiconductor memory which is programmed during
manufacture. The contents can be read but cannot be altered.
Resistance The opposition to current ow. It results in loss of energy in a circuit
and is dissipated as heat.
Semiconductor A type of material, such as silicon, that exhibits characteristics
between a good conductor and a poor conductor.
Series Circuit Current that ows through one or more devices in a single path.
Sheet Resistance (RHO) A measurement (in ohms per square cm) that is frequently used to
evaluate predispositions and drive-ins. It is related to the number of
n-type donor, or p-type acceptor donor, or acceptor atoms in a
semiconductor.
Silicon Dioxide The oxide of silicon that is used (either deposited or thermally
grown) in chip fabrication as an insulating layer and as a barrier to
unwanted impurities.
Source In a MOS transistor, the terminal from which the carriers ow.
Transistor A three-terminal circuit element manufactured using semiconductor
material. The transistor provides signal amplication.
Very Large Scale
Integration (VLSI)
The process of creating an integrated circuit (IC) that contains
1000 - 10,000 transistors.
Wafer The substrate, made usually from semiconductor material such as
silicon, that is used as the foundation on which integrated circuits are
built.
White Space Unused area on the die.

Drawing CMOS Layout For IC DesignCrestopher Saint

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Drawing CMOS Layout For IC DesignCrestopher Saint

Uploaded by

Copyright:

Available Formats

CMOS 1

Drawing CMOS Layout for IC Design

You might also like