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  • CoA Lab 2013 Assgn 7

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    This document provides instructions for an assignment on implementing a 16-bit non-restoring binary division circuit in Verilog. Students are asked to: (1) draw a flowchart of the non-restoring division algorithm, (2) write structural and behavioral descriptions of the datapath and controller, (3) write a testbench to test 5 pairs of inputs, and (4) replace the behavioral controller with an equivalent structural description. The Verilog code is to be submitted by September 5th.

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    This document provides instructions for an assignment on implementing a 16-bit non-restoring binary division circuit in Verilog. Students are asked to: (1) draw a flowchart of the non-restoring division algorithm, (2) write structural and behavioral descriptions of the datapath and controller, (3) write a testbench to test 5 pairs of inputs, and (4) replace the behavioral controller with an equivalent structural description. The Verilog code is to be submitted by September 5th.

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    6 views1 page

    CoA Lab 2013 Assgn 7

    Uploaded by

    rameshbssv
    This document provides instructions for an assignment on implementing a 16-bit non-restoring binary division circuit in Verilog. Students are asked to: (1) draw a flowchart of the non-restoring division algorithm, (2) write structural and behavioral descriptions of the datapath and controller, (3) write a testbench to test 5 pairs of inputs, and (4) replace the behavioral controller with an equivalent structural description. The Verilog code is to be submitted by September 5th.

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    © All Rights Reserved
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    CS39001: Computer Organization Laboratory

    Assignment-7 (10 marks)


    Assigned On: 29
    th
    August 2013
    Due Date: 5
    th
    September 2013 (2 PM)
    1. In this assignment you will implement a circuit to perform 16-bit non-restoring
    division of two binary signed numbers, as described in class. Perform the following:
    (a) Draw a flow-chart of the non-restoring division algorithm.
    (b) Write a Verilog structural description of the datapath.
    (c) Write a behavioural description of the controller.
    (d) Write a Verilog testbench to test your design for at least 5 pairs of dividends and
    divisors.
    (e) Now, replace the behavioral controller module by an equivalent structural
    description of the controller, having one-one correspondence of the controller flip-
    flops with the flow-chart states. Use the same testbench as part-(d), and show that
    the results are independent of the style of coding of the controller.
    Submit only your Verilog code (design files and the testbench) in a zipped folder
    Assignment_7.zip on Intinno (one submission per group). (10 marks)

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