Lecture 7 EE 486

M.J. Flynn 1
Computer Architecture & Arithmeti c Group 1 Stanford University
EE 486 lecture 7: Integer Multiplication
M. J. Flynn
slides prepared by Albert Liddicoat and Hossam Fahmy
Computer Architecture & Arithmeti c Group 2 Stanford University
Multiplication Add-and-Shift Algorithm
Multiplicand
Multiplier
Partial Products
Result
1 1 0
1 0 1
1 1 0
0 0 0
1 1 0
1 1 1 1 0
X
Y
PP
S
6
5
30
x x
ALU
X Y
P
0
Shift
Shift
Computer Architecture & Arithmeti c Group 3 Stanford University
Parallel Multiplication
1 Simultaneous generation of partial products
2 Parallel reduction of partial products
3 Carry Propagate Addition (CPA)
Parallel generation of partial products
X
0
X
1
Y
2
Y
1
Y
0
X
0
Y
0
X
1
Y
0
X
2
Y
0
X
0
Y
1
X
1
Y
1
X
2
Y
1
X
0
Y
2
X
1
Y
2
X
2
Y
2
R
0
R
1
R
2
R
3
R
4
R
5
x
X
2
. . .
X
0
X
1
Y
2
Y
1
Y
0 x
X
2
. . .
. . .
. . . . . .
Using AND gate as 1x1-bit multiplier DOT representation
Computer Architecture & Arithmeti c Group 4 Stanford University
Generation of PPs Using ROMs
A
d
d
r
e
s
s
D
a
t
a
256x8-bit ROM
X
Y
R
4b x 4b Multiply Using
X
3
X
2
X
1
X
0
X
7
X
6
X
5
X
4
Y
3
Y
2
Y
1
Y
0
Y
7
Y
6
Y
5
Y
4
X
3
X
2
X
1
X
0
* Y
3
Y
2
Y
1
Y
0
* Y
3
Y
2
Y
1
Y
0
X
7
X
6
X
5
X
4
* Y
7
Y
6
Y
5
Y
4
* Y
7
Y
6
Y
5
Y
4
X
3
X
2
X
1
X
0
X
7
X
6
X
5
X
4
x
8b x 8b Multiply Using
256x8-bit ROMs
Computer Architecture & Arithmeti c Group 5 Stanford University
Generation of PPs Using ROMs
a
b
c
d
a
c
b
d
8 x 8 bit Multiply using
256x8b ROMs
4x4 bit
8x8 bit
16x16 bit
4, 8, and 16 bit Multiply
using 256x8bit ROMs
n h CSA Delay
4
8
16
32
64
1
3
7
15
31
0
1
4
6
8
Computer Architecture & Arithmeti c Group 6 Stanford University
Booths Algorithm
Observation: We can replace a string of 1s in the multiplier by +1 and -1.
Example:
. . . 0 1 1 1 1 1 0 . . .
+1
- 1
. . . 1 0 0 0 0 0 0 . . .
- 1
. . . 1 0 0 0 0-1 0 . . .
. . . 0 1 1 1 1 1 0 . . .
X
X
X
X
X
X*(0 1 1 1 1 1)
0
1
1
1
1
0
1
Y
X*(1 0 0 0 0-1)
-X
0
0
0
0
0
0
0
0
1
-1
Y
X
Lecture 7 EE 486
M.J. Flynn 2
Computer Architecture & Arithmeti c Group 7 Stanford University
Booths Algorithm
+ Reduces the number of partial products which in turn reduces the
hardware and delay required to sum the partial products.
- Adds Delay into the formation of the Partial Products.
Works well for serial multiplication that can tolerate variable
latency operations by reducing the number of serial additions
required for the multiplication.
The number of serial additions depends on the data (multiplicand).
Worst case 8-bit multiplicand requires 8 additions
01010101 <=> 1 -1 1 -1 1 -1 1 -1
Parallel systems generally are designed for worst case hardware
and latency requirements. Standard booth 2 does not significantly
reduce the worst case number of partial products.
Computer Architecture & Arithmeti c Group 8 Stanford University
Modified Booth 2
Booth 2 modified to produce at most
n
/
2
+1
partial products.
Algorithm: (for unsigned numbers)
1) Pad the LSB with one zero.
2) Pad the MSB with 2 zeros if n is even and 1 zero if n is odd.
3) Divide the multiplier into overlapping groups of 3-bits.
4) Determine partial product scale factor from modified
booth 2 encoding table.
5) Compute the Multiplicand Multiples
6) Sum Partial Products
Computer Architecture & Arithmeti c Group 9 Stanford University
Modified Booth 2
0 0 Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
0
Example: (n=8-bits unsigned)
Y
i
Y
i+1
Y
i-1
Scale
Factor
0
0
0
1
1
1
1
0 0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+0
+X
+X
+2X
-2X
-X
-X
-0
3) Form 3-bit overlapping groups
for n=8 we have 5 groups
1) Pad LSB with 1 zero
2) n is even so Pad MSB with 2 zeros
4) Determine action from
table for each 3-bit group
Computer Architecture & Arithmeti c Group 10 Stanford Uni versity
Modified Booth 2
5) Compute Multiplicand Scale Factor (~4 gate delays)
Y
j
X
i
PP
ij
X
i
X
i-1
0
Y
j+1
Y
j
Y
j-1
PP
ij
Direct Multiplier
Modified Booth 2
Multiplier
Mux Control
Logic
Scale
Factor Action
+0 Mux 0
+X
+2X
-2X
-X
Mux X
i
Mux X
i-1
Mux X
i-1

Mux X
i

Computer Architecture & Arithmeti c Group 11 Stanford Uni versity

Modified Booth 2
6) Sum Partial Products
Sign extend partial products to the full width of the final result
Logic may replace the A
9
, B
9
, C
9
, D
9
, and E
9
sign extention bits.
Y
i+1
bit determines if the multiple needs to be complemented
A
9
. . . A
9
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
B
9
. . . B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
Y
1
C
9
. . . C
6
C
5
C
4
C
3
C
2
C
1
C
0
Y
3
D
9
. . . D
4
D
3
D
2
D
1
D
0
Y
5
E
9
. . . E
2
E
1
E
0
Y
7
S
15
. . . S
10
S
9
S
8
S
7
S
6
S
5
S
4
S
3
S
2
S
1
S
0
(Y
1
Y
0
0 )
(Y
3
Y
2
Y
1
)
(Y
5
Y
4
Y
3
)
(Y
7
Y
6
Y
5
)
( 0 0 Y
7
)
Partial Products
Multiplicand
Y
i+1
Y
i
Y
I-1
Computer Architecture & Arithmeti c Group 12 Stanford Uni versity
Modified Booth 2
Algorithm Extension: (for signed multiplier)
1) Pad the LSB with one zero.
2) If n is even dont pad the MSB (
n
/
2
PPs) and
if n is odd sign extend the MSB by 1 bit (
n+1
/
2
PPs).
3) Divide the multiplier into overlapping groups of 3-bits.
4) Determine partial product factor from table.
5) Compute the Multiplicand Multiples
6) Sum Partial Products
n Even:
X
n-1
X
n-2
X
n-2
0 x x
1 x x
n Odd:
X
n-1
X
n-2
0 0 x
1 1 x
Positive:
Negative:
Lecture 7 EE 486
M.J. Flynn 3
Computer Architecture & Arithmeti c Group 13 Stanford Uni versity
Modified Booth 2
Algorithm Extension: (for signed multiplicand)
Nothing the algorithm works fine !
The multiplicand may be represented in 2s complement code.
The scale factors (0, +X, +2X, -X, and -2X) are handled correctly.
Shift left for 2 times weighting.
2s complement the multiplicand for subtraction.
Computer Architecture & Arithmeti c Group 14 Stanford Uni versity
Booth 3
Reduces the partial products to ~
n
/
3
Form overlapping groups of 4 bits.
0 Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
0
Booth 3 Encoding
Y
i
Y
i+1
Y
i-1
Scale
Factor
0
0
0
1
1
1
1
0 0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-4X
-3X
-2X
-2X
-X
-X
-0
Y
i+2
1
1
1
1
1
1
1
1
Y
i
Y
i+1
Y
i-1
Scale
Factor
0
0
0
1
1
1
1
0 0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+0
+X
+X
+2X
+2X
+3X
Y
i+2
0
0
0
0
0
0
0
0
+3X
+4X
-3X
Note: 3x is a hard
multiple that must
be precomputed
Computer Architecture & Arithmeti c Group 15 Stanford Uni versity
Partially Redundant Booth 3
Computer Architecture & Arithmeti c Group 16 Stanford Uni versity
Partially Redundant Booth 3