______________________________________________________________________________Chng 7

B nh bn dn VII - 1

CHNG 7: B NH BN DN

THUT NG
I CNG V VN HNH CA B NH
Cc tc v v cc nhm chn ca IC nh
Giao tip vi CPU
CC LOI B NH BN DN
ROM
PLD
RAM
M RNG B NH
M rng di t
M rng v tr nh
M rng dung lng nh
_________________________________________________________________________________

Tnh u vit ch yu ca cc h thng s so vi h thng tng t l kh nng lu tr
mt lng ln thng tin s v d liu trong nhng khong thi gian nht nh. Kh nng nh
ny l iu lm cho h thng s tr thnh a nng v c th thch hp vi nhiu tnh hung.
Th d trong mt my tnh s, b nh trong cha nhng lnh m theo my tnh c th hon
tt cng vic ca mnh vi s tham gia t nht ca con ngi.
B nh bn dn c s dng lm b nh chnh trong cc my tnh nh vo kh nng
tha mn tc truy xut d liu ca b x l trung tm (CPU).
Chng ta qu quen thuc vi Fliflop, mt linh kin in t c tnh nh. Chng ta
cng thy mt nhm cc FF hp thnh thanh ghi lu tr v dch chuyn thng tin nh
th no. Cc FF chnh l cc phn t nh tc cao c dng rt nhiu trong vic iu hnh
bn trong my tnh, ni m d liu dch chuyn lin tc t ni ny n ni khc.
Tin b trong cng ngh ch to LSI v VLSI cho php kt hp mt lng ln FF
trong mt chip to thnh cc b nh vi cc dng khc nhau. Nhng b nh bn dn vi cng
ngh ch to transistor lng cc (BJT) v MOS l nhng b nh nhanh nht v gi thnh ca
n lin tc gim khi cc cng ngh LSI v VLSI ngy cng c ci tin.
D liu s cng c th c lu tr di dng in tch ca t in, v mt loi phn
t nh bn dn rt quan trng dng nguyn tc ny lu tr d liu vi mt cao nhng
tiu th mt ngun in nng rt thp.
B nh bn dn c dng nh l b nh trong chnh ca my tnh, ni m vic vn
hnh nhanh c xem nh u tin hng u v cng l ni m tt c d liu ca chng trnh
lu chuyn lin tc trong qu trnh thc hin mt tc v do CPU yu cu.
Mc d b nh bn dn c tc lm vic cao, rt ph hp cho b nh trong, nhng
gi thnh tnh trn mi bit lu tr cao khin cho n khng th l loi thit b c tnh cht lu
tr khi (mass storage), l loi thit b c kh nng lu tr hng t bit m khng cn cung cp
nng lng v c dng nh l b nh ngoi (a t , bng t , CD ROM . . .). Tc x l
d liu b nh ngoi tng i chm nn khi my tnh lm vic th d liu t b nh ngoi
c chuyn vo b nh trong.
Bng t v a t l cc thit b lu tr khi m gi thnh tnh trn mi bit tng i
thp. Mt loi b nh khi mi hn l b nh bt t (magnetic bubble memory, MBM) l
b nh in t da trn nguyn tc t c kh nng lu tr hng triu bit trong mt chip. Vi
tc tng i chm n khng c dng nh b nh trong.
Chng ny nghin cu cu to v t chc ca cc b nh bn dn.
_________________________________________________________Nguyn Trung Lp
K THUT S

______________________________________________________________________________Chng 7
B nh bn dn VII - 2

7.1 Thut ng lin quan n b nh
tm hiu cu to, hot ng ca b nh chng ta bt u vi mt s thut ng lin
quan n b nh
- T bo nh: l linh kin hay mt mch in t dng lu tr mt bit n (0 hay
1). Th d ca mt t bo nh bao gm: mch FF, t c tch in, mt im trn bng t
hay a t. . . .
- T nh : l mt nhm cc bit (t bo) trong b nh dng biu din cc lnh hay d
liu di dng mt s nh phn. Th d mt thanh ghi 8 FF l mt phn t nh lu tr t 8 bit.
Kch thc ca t nh trong cc my tnh hin i c chiu di t 4 n 64 bit.
- Byte : t 8 bit, y l kch thc thng dng ca t nh trong cc my vi tnh.
- Dung lng : ch s lng bit c th lu tr trong b nh. Th d b nh c kh
nng lu tr 4.096 t nh 20 bit, dung lng ca n l 4096 x 20, mi 1024 (=2
10
) t nh
c gi l 1K, nh vy 4096 x 20 = 4K x 20. Vi dung lng ln hn ta dng 1M hay
1meg ch 2
20
= 1.048.576 t nh.
- a ch : l s nh phn dng xc nh v tr ca t nh trong b nh. Mi t nh
c lu trong b nh ti mt a ch duy nht. a ch lun lun c biu din bi s nh
phn, tuy nhin thun tin ngi ta c th dng s hex hay thp phn, bt phn
- Tc v c : (Read, cn gi l fetch ), mt t nh ti mt v tr no trong b nh
c truy xut v chuyn sang mt thit b khc.
- Tc v vit : (ghi, Write, cn gi l store ), mt t mi c t vo mt v tr trong
b nh, khi mt t mi c vit vo th t c mt i.
- Thi gian truy xut (access time) : s o tc hot ng ca b nh, k hiu t
ACC

l thi gian cn hon tt mt tc v c. Chnh xc l thi gian t khi b nh nhn
mt a ch mi cho ti lc d liu kh dng ng ra b nh
- B nh khng vnh cu (volatile) : B nh cn ngun in lu tr thng tin. Khi
ngt in, thng tin lu tr b mt. Hu ht b nh bn dn l loi khng vnh cu, trong khi
b nh t l loi vnh cu (nonvolatile).
- B nh truy xut ngu nhin (Random-Access Memory, RAM) : Khi cn truy xut
mt a ch ta ti ngay a ch . Vy thi gian c hay vit d liu vo cc v tr nh khc
nhau trong b nh khng ty thuc vo v tr nh. Ni cch khc, thi gian truy xut nh
nhau i vi mi v tr nh. Hu ht b nh bn dn v nhn t (b nh trong ca my tnh
trc khi b nh bn dn ra i) l loi truy xut ngu nhin.
- B nh truy xut tun t (Sequential-Access Memory, SAM) : Khi cn truy xut
mt a ch ta phi lt qua cc a ch trc n. Nh vy thi gian c v vit d liu
nhng v tr khc nhau th khc nhau. Nhng th d ca b nh ny l bng t, a t. Tc
lm vic ca loi b nh ny thng chm so vi b nh truy xut ngu nhin.
- B nh c/vit (Read/Write Memory, RWM) : B nh c th vit vo v c ra.
- B nh ch c (Read-Only Memory, ROM): l b nh m t l tc v c trn tc
v ghi rt ln. V mt k thut, mt ROM c th c ghi ch mt ln ni sn xut v sau
thng tin ch c th c c ra t b nh. C loi ROM c th c ghi nhiu ln nhng
tc v ghi kh phc tp hn l tc v c. ROM thuc loi b nh vnh cu v d liu c
lu gi khi ct ngun in.
- B nh tnh (Static Memory Devices) : l b nh bn dn trong d liu lu tr
c duy tr cho n khi no cn ngun nui.
- B nh ng (Dynamic Memory Devices) : l b nh bn dn trong d liu
lu tr mun tn ti phi c ghi li theo chu k. Tc v ghi li c gi l lm ti
(refresh).
- B nh trong (Internal Memory) : Ch b nh chnh ca my tnh. N lu tr cc
lnh v d liu m CPU dng thng xuyn khi hot ng.
_________________________________________________________Nguyn Trung Lp
K THUT S

______________________________________________________________________________Chng 7
B nh bn dn VII - 3

- B nh khi (Mass Memory): Cn gi l b nh ph, n cha mt lng thng tin
rt ln bn ngoi my tnh. Tc truy xut trn b nh ny thng chm v n thuc loi
vnh cu.
7.2 i cng v vn hnh ca b nh
7.2.1 Cc tc v v cc nhm chn ca mt IC nh
Mc d mi loi b nh c hot ng bn trong khc nhau, nhng chng c chung
mt s nguyn tc vn hnh m chng ta c th tm hiu s lc trc khi i vo nghin cu
tng loi b nh.
Mi h thng nh lun c mt s yu cu cc ng vo v ra hon thnh mt s
tc v:
- Chn a ch trong b nh truy xut (c hoc vit)
- Chn tc v c hoc vit thc hin
- Cung cp d liu lu vo b nh trong tc v vit
- Gi d liu ra t b nh trong tc v c
- Cho php (Enable) (hay Khng, Disable) b nh p ng (hay khng) i vi lnh
c/ghi a ch gi n.
T cc tc v k trn, ta c th hnh dung mi IC nh c mt s ng vo ra nh sau:
- Ng vo a ch : mi v tr nh xc nh bi mt a ch duy nht, khi cn c d
liu ra hoc ghi d liu vo ta phi tc ng vo chn a ch ca v tr nh . Mt IC c n
chn a ch s c 2
n
v tr nh. K hiu cc chn a ch l A
0
n A
n-1
Mt IC c 10 chn a
ch s c 1024 (1K) v tr nh.
- Ng vo/ra d liu: Cc chn d liu l cc ng vo/ra, ngha l d liu lun c
x l theo hai chiu. Thng th d liu vo/ra chung trn mt chn nn cc ng ny thuc
loi ng ra 3 trng thi. S chn a ch v d liu ca mt IC xc nh dung lng nh ca IC
. Th d mt IC nh c 10 chn a ch v 8 chn d liu th dung lng nh ca IC l
1Kx8 (8K bit hoc 1K Byte).
- Cc ng vo iu khin: Mi khi IC nh c chn hoc c yu cu xut nhp d
liu cc chn tng ng s c tc ng. Ta c th k ra mt s ng vo iu khin:
* CS: Chip select - Chn chip - Khi chn ny xung thp IC c chn
* CE: Chip Enable - Cho php chip - Chc nng nh chn CS
* OE: Output Enable - Cho php xut - Dng khi c d liu
* W R/ : Read/Write - c/Vit - Cho php c d liu ra khi mc cao v Ghi d
liu vo khi mc thp
* CAS : Column Address Strobe - Cht a ch ct
*RAS: Row Address Strobe - Cht a ch hng.
Trong trng hp chip nh c dung lng ln, gim kch thc ca mch gii m
a ch bn trong IC, ngi ta chia s chn ra lm 2: a ch hng v a ch ct. Nh vy phi
dng 2 mch gii m a ch nhng mi mch nh hn rt nhiu. Th d vi 10 chn a ch,
thay v dng 1 mch gii m 10 ng sang 1024 ng, ngi ta dng 2 mch gii m 5
ng sang 32 ng, hai mch ny rt n gin so vi mt mch kia. Mt v tr nh by gi
c 2 a ch : hng v ct, d nhin mun truy xut mt v tr nh phi c 2 a ch nh 2
tn hiu RAS v CAS .
(H 7.1) cho thy cch v cc nhm chn ca IC nh (m chn a ch v n chn d
liu). (H 7.1b) v (H 7.1c) v cc chn a ch v d liu di dng cc Bus. (H 7.1b) c
dng trong cc s chi tit v (H 7.1c) c dng trong cc s khi.

_________________________________________________________Nguyn Trung Lp
K THUT S

______________________________________________________________________________Chng 7
B nh bn dn VII - 4


(a) (b) (c)
(H 7.1)
7.2.2 Giao tip gia IC nh v b x l trung tm (CPU)
Trong h thng mi hot ng c lin quan n IC nh u do b x l trung tm
(Central Processing Unit, CPU) qun l. Giao tip gia IC nh v CPU m t (H 7.2)

(H 7.2)
Mt tc v c lin quan n b nh c CPU thc hin theo cc bc:
- t a ch quan h ln bus a ch.
- t tn hiu iu khin ln bus iu khin.
- D liu kh dng xut hin trn bus d liu, sn sng ghi vo hoc c ra.
hot ng ca IC ng b, cc bc trn phi tun th gin thi gian ca tng
IC nh (s cp n khi xt cc loi b nh)
7.3 Cc loi b nh bn dn
C 3 loi b nh bn dn :
- B nh bn dn ch c : (Read Only Memory, ROM)
- B nh truy xut ngu nhin : (Random Access Memory, RAM)
Tht ra ROM v RAM u l loi b nh truy xut ngu nhin, nhng RAM c gi
tn gi ny. phn bit chnh xc ROM v RAM ta c th gi ROM l b nh cht
(nonvolatile, vnh cu) v RAM l b nh sng (volatile, khng vnh cu) hoc nu coi
ROM l b nh ch c th RAM l b nh c c - vit c (Read-Write Memory)
- Thit b logic lp trnh c : (Programmable Logic Devices, PLD) c th ni im
khc bit gia PLD vi ROM v RAM l qui m tch hp ca PLD thng khng ln nh
ROM v RAM v cc tc v ca PLD th c phn hn ch.


7.3.1 ROM (Read Only Memory)
Mc d c tn gi nh th nhng chng ta phi hiu l khi s dng ROM, tc v c
c thc hin rt nhiu ln so vi tc v ghi. Thm ch c loi ROM ch ghi mt ln khi xut
xng.
Cc t bo nh hoc t nh trong ROM sp xp theo dng ma trn m mi phn t
chim mt v tr xc nh bi mt a ch c th v ni vi ng ra mt mch gii m a ch
_________________________________________________________Nguyn Trung Lp
K THUT S

______________________________________________________________________________Chng 7
B nh bn dn VII - 5

bn trong IC. Nu mi v tr cha mt t bo nh ta ni ROM c t chc bit v mi v tr l
mt t nh ta c t chc t.
Ngoi ra, gim mc cng knh ca mch gii m, mi v tr nh c th c xc
nh bi 2 ng a ch : ng a ch hng v ng a ch ct v trong b nh c 2 mch
gii m nhng mi mch c s ng vo bng 1/2 s ng a ch ca c b nh.

7.3.1.1 ROM mt n (Mask Programmed ROM, MROM)
y l loi ROM c ch to thc hin mt cng vic c th nh cc bng tnh,
bng lng gic , bng logarit . . . . ngay sau khi xut xng. Ni cch khc, cc t bo nh
trong ma trn nh c to ra theo mt chng trnh xc nh trc bng phng php
mt n: a vo cc linh kin in t ni t ng t qua ng bt to ra mt gi tr bit
v trng cho gi tr bit ngc li.
- (H 7.3) l m hnh ca mt MROM trong cc vung l ni cha (hay khng)
mt linh kin (diod, transistor BJT hay MOSFET) to bit. Mi ng ra ca mch gii m
a ch gi l ng t v ng ni t bo nh ra ngoi gi l ng bit. Khi ng t ln
mc cao th t bo nh hoc t nh c chn.



(H 7.3)

Nu t bo nh l Diod hoc BJT th s hin din ca linh kin tng ng vi bit 1
(lc ny ng t ln cao, Transsisstor hoc diod dn, dng in qua in tr to in th cao
hai u in tr) cn v tr nh trng tng ng vi bit 0.
i vi loi linh kin MOSFET th ngc li, ngha l s hin din ca linh kin
tng ng vi bit 0 cn v tr nh trng tng ng vi bit 1 (mun c kt qu nh loi BJT th
thm ng ra cc cng o).
(H 7.4) l mt th d b nh MROM c dung lng 16x1 vi cc mch gii m hng
v ct (cc mch gii m 2 ng sang 4 ng ca hng v ct u dng Transistor MOS v
c cng cu trc).

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K THUT S

______________________________________________________________________________Chng 7
B nh bn dn VII - 6


(H 7.4)
Trong thc t, n gin cho vic thc hin, mi v tr nh ngi ta u cho vo
mt transistor MOS. Nhng nhng v tr ng vi bit 1 cc transistor MOS c ch to vi
lp SiO
2
dy hn lm tng in th ngng ca n ln, kt qu l transistor MOS ny lun
lun khng dn in (H 7.5), Cc transistor khc dn in bnh thng.


(H 7.5)

7.3.1.2 ROM lp trnh c (Programmable ROM, PROM)
C cu to ging MROM nhng mi v tr nh u c linh kin ni vi cu ch.
Nh vy khi xut xng cc ROM ny u cha cng mt loi bit (gi l ROM trng), lc s
dng ngi lp trnh thay i cc bit mong mun bng cch ph v cu ch cc v tr tng
ng vi bit . Mt khi cu ch b ph v th khng th ni li c do loi ROM ny
cho php lp trnh mt ln duy nht s dng, nu b li khng th sa cha c (H 7.6).


(H 7.6)
Ngi ta c th dng 2 diod mc ngc chiu nhau, mch khng dn in, to bit
0, khi lp trnh th mt diod b ph hng to mch ni tt, diod cn li dn in cho bit 1

_________________________________________________________Nguyn Trung Lp
K THUT S

______________________________________________________________________________Chng 7
B nh bn dn VII - 7

7.3.1.3 ROM lp trnh c, xa c bng tia U.V. (Ultra Violet Erasable
Programmable ROM, U.V. EPROM)
y l loi ROM rt tin cho ngi s dng v c th dng c nhiu ln bng cch
xa v np li. Cu to ca t bo nh ca U.V. EPROM da vo mt transistor MOS c cu
to c bit gi l FAMOS (Floating Gate Avalanche Injection MOS)


(H 7.7)
Trn nn cht bn dn N pha long, to 2 vng P pha m (P
+
) ni ra ngoi cho 2 cc
S (Source) v D (Drain). Trong lp cch in SiO
2
gia 2 cc ngi ta cho vo mt thi
Silicon khng ni vi bn ngoi v c gi l cng ni. Khi ngun V
DD
, phn cc ngc
gia cc nn v Drain cn nh, transistor khng dn, nhng nu tng V
DD
ln, hin tng
thc (avalanche) xy ra, electron nng lng chui qua lp cch in ti bm vo cng
ni. Do hin tng cm ng, mt in l P hnh thnh ni hai vng bn dn P
+
, transistor tr
nn dn in. Khi ct ngun, transistor tip tc dn in v electron khng th tr v ti
hp vi l trng.
xa EPROM, ngi ta chiu tia U.V. vo cc t bo trong mt khong thi gian
xc nh electron trn cng ni nhn nng lng vt qua lp cch in tr v vng nn
ti hp vi l trng xa in l P v transistor tr v trng thi khng dn ban u.


(H 7.8)

Mi t bo nh EPROM gm mt transistor FAMOS ni tip vi mt transistor MOS
khc m ta gi l transistor chn, nh vy vai tr ca FAMOS ging nh l mt cu ch
nhng c th phc hi c.
loi b transistor chn ngi ta dng transistor SAMOS (Stacked Gate Avalanche
Injection MOS) c cu to tng t transistor MOS nhng c n 2 cng nm chng ln
nhau, mt c ni ra cc Gate v mt ni. Khi cng ni tch in s lm gia tng in th
thm khin transistor tr nn kh dn in hn. Nh vy nu ta chn in th V
c
khong
gia VT
1
v VT
2
l 2 gi tr in th thm tng ng vi 2 trng thi ca transistor
(VT
1
<V
c
<VT
2
) th cc transistor khng c lp trnh (khng c lp electron cng ni) s
dn cn cc transistor c lp trnh s khng dn.

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K THUT S

______________________________________________________________________________Chng 7
B nh bn dn VII - 8


(H 7.9)

im bt tin ca U.V EPROM l cn thit b xa c bit pht tia U.V. v mi ln
xa tt c t bo nh trong mt IC nh u b xa. Nh vy ngi s dng phi np li ton
b chng trnh

7.3.1.4 ROM lp trnh c v xa c bng xung in (Electrically
Erasable PROM, EEPROM hay Electrically Alterable PROM, EAPROM)
y l loi ROM lp trnh c v xa c nh xung in v c bit l c th xa
sa trn tng byte. Cc t bo nh EEPROM s dng transistor MNOS (Metal Nitride
Oxide Semiconductor) c cu to nh (H 7.10).


(H 7.10)
Gia lp kim loi ni ra cc cc v lp SiO
2
l mt lp mng cht Nitrua Silic (Si
3
N
4
)
- t 40nm n 650nm - D liu c np bng cch p mt in th dng gia cc G v S
(khong 20 n 25V trong 100ms). Do s khc bit v dn in, electron tch trn b mt
gia 2 lp SiO
2
v Si
3
N
4
, cc electron ny tn ti khi ngt ngun v lm thay i trng
thi dn in ca transistor. By gi nu p mt in th m gia cc G v S ta s c mt
lp in tch tri du vi trng hp trc. Nh vy hai trng thi khc nhau ca Transistor
c th thit lp c bi hai in th ngc chiu nhau v nh vy cc t bo nh c ghi v
xa vi 2 xung in tri du nhau.

7.3.1.5 FLASH ROM
EPROM l loi nonvolatile, c tc truy xut nhanh (khong 120ns), mt tch
hp cao, gi thnh r tuy nhin xa v np li phi dng thit b c bit v ly ra khi
mch.
EEPROM cng nonvolatile, cng c tc truy xut nhanh, cho php xa v np li
ngay trong mch trn tng byte nhng c mt tch hp thp v gi thnh cao hn EPROM.
B nh FLASH ROM tn dng c cc u im ca hai loi ROM ni trn, ngha l
c tc truy xut nhanh, c mt tch hp cao nhng gi thnh thp.
Hu ht cc FLASH ROM s dng cch xa ng thi c khi d liu nhng rt
nhanh (hng trm ms so vi 20 min ca U.V. EPROM). Nhng FLASH ROM th h mi cho
php xa tng sector (512 byte) thm ch tng v tr nh m khng cn ly IC ra khi mch.
FLASH ROM c thi gian ghi khong 10s/byte so vi 100 s i vi EPROM v 5 ms i
vi EEPROM

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K THUT S

______________________________________________________________________________Chng 7
B nh bn dn VII - 9

7.3.1.6 Gin thi gian ca ROM
Ngoi tr MROM ch dng ch c, cc loi ROM khc u s dng hai ch
c v np chng trnh.
Nh vy ta c hai loi gin thi gian: Gin thi gian c v gin thi gian
np trnh.
(H 7.11) l gin thi gian tiu biu cho mt chu k c ca ROM.
Cc gi tr a ch, cc tn hiu W R/ v CS c cp t CPU khi cn thc hin tc v
c d liu ti mt a ch no . Thi gian thc hin mt tc v c gi l chu k c
t
RC
. Trong mt chu k c c th k mt s thi gian sau:


(H 7.11)

- t
ACC
: Address Access time: Thi gian truy xut a ch: Thi gian ti a t lc CPU
t a ch ln bus a ch n lc d liu c gi tr trn bus d liu. i vi ROM dng BJT
thi gian ny khong t 30 ns n 90 ns, cn loi MOS th t 200 ns n 900 ns.
- t
ACS
(t
ACE
): Chip select (enable) access time: Thi gian thm nhp chn chip: Thi
gian ti a t lc tn hiu CS c t ln bus iu khin n lc d liu c gi tr trn bus
d liu. ROM BJT khong 20 ns , MOS 100 ns
- t
H
(Hold time): Thi gian d liu cn tn ti trn bus d liu k t lc tn hiu CS
ht hiu lc
(H 7.12) l gin thi gian ca mt chu k np d liu cho EPROM. Mt chu k np
liu bao gm thi gian np (Programmed) v thi gian kim tra kt qu (Verify)

(H 7.12)

7.3.2 Thit b logic lp trnh c (Programmable logic devices, PLD)
L tn gi chung cc thit b c tnh cht nh v c th lp trnh thc hin mt cng
vic c th no
Trong cng vic thit k cc h thng, i khi ngi ta cn mt s mch t hp
thc hin mt hm logic no . Vic s dng mch ny c th lp li thng xuyn v s
thay i mt tham s ca hm c th phi c thc hin tha mn yu cu ca vic thit
k. Nu phi thit k t cc cng logic c bn th mch s rt cng knh, tn km mch in,
_________________________________________________________Nguyn Trung Lp
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______________________________________________________________________________Chng 7
B nh bn dn VII - 10

dy ni nhiu, kt qu l tin cy khng cao. Nh vy, s rt tin li nu cc mch ny c
ch to sn v ngi s dng c th ch tc ng vo lm thay i mt phn no chc nng
ca mch bng cch lp trnh. l tng c s cho s ra i ca thit b logic lp trnh
c. Cc thit b ny c th c xp loi nh b nh v gm cc loi: PROM, PAL
(Programmable Array Logic) v PLA (Programmable Logic Array).
Trc nht, chng ta xt qua mt s qui c trong cch biu din cc phn t ca PLD
Mt bin trong cc hm thng xut hin dng nguyn v o ca n nn chng ta
dng k hiu m v o chung trong mt cng c 2 ng ra.
Mt ni cht, cn gi l ni cng (khng thay i c) c v bi mt chm m
(.) v mt ni sng, cn gi l ni mm (dng lp trnh) bi mt du (x). Ni sng thc cht
l mt cu ch, khi lp trnh th c ph b.
Mt cng nhiu ng vo thay th bi mt ng vo duy nht vi nhiu mi ni (H
7.13).

(H 7.13)

Chng ta ch ly th d vi mch tng i n gin thy c cu to ca cc
PLD, l cc PLD ch thc hin c 4 hm mi hm gm 4 bin, nh vy mch gm 4
ng vo v 4 ng ra. Trn thc t s hm v bin ca mt PLD rt ln.

7.3.2.1 PROM
(H 7.14 ) l cu to PROM c 4 ng vo v 4 ng ra.
C tt c 16 cng AND c 4 ng vo c ni cht vi cc ng ra o v khng o
ca cc bin vo, ng ra cc cng AND l 16 t hp ca 4 bin (Gi l ng tch)
Cc cng OR c 16 ng vo c ni sng thc hin hm tng (ng tng). Nh vy vi
PROM vic lp trnh thc hin cc ng tng.
Th d dng PROM ny to cc hm sau:
C D B D A O
1
+ + = A B DC BA C D O
2
+ = A B C O
3
= C D BA O
4
+ =
Ta phi chun ha cc hm cha chun
A B C D A B C D A CB D A B C D A B C D A B C D A B DC BA C D BA C D CBA D DCBA O
1
+ + + + + + + + + + =
A B C A B C A B C O
3
D D + = =
A B C D A B C D A B C D DCBA BA C D CBA D BA C D C D BA O
4
+ + + + + + = + =
Mch cho (H 7.14b)
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B nh bn dn VII - 11


(a) (b)
(H 7.14)

7.3.2.2 PAL
Mch tng t vi IC PROM, PAL c cc cng AND 8 ng vo c ni sng v 4
cng OR mi cng c 4 ng vo ni cht vi 4 ng tch. Nh vy vic lp trnh c thc
hin trn cc ng tch
(H 7.15b) l IC PAL c lp trnh thc hin cc hm trong th d trn:

C D B D A O
1
+ + = A B DC BA C D O
2
+ = A B C O
3
= C D BA O
4
+ =



(a) (b)
(H 7.15)

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B nh bn dn VII - 12

7.3.2.3 PLA
PLA c cu to tng t PROM v PAL, nhng cc ng vo ca cng AND v cng
OR u c ni sng (H 7.16). Nh vy kh nng lp trnh ca PLA bao gm c hai cch lp
trnh ca 2 loi IC k trn.


(H 7.16)

7.3.3 RAM (Random Acess Memory)
C hai loi RAM : RAM tnh v RAM ng
RAM tnh cu to bi cc t bo nh l cc FF, RAM ng li dng cc in dung k
sinh gia cc cc ca transistor MOS, trng thi tch in hay khng ca t tng ng vi hai
bit 1 v 0. Do RAM ng c mt tch hp cao, dung lng b nh thng rt ln nn
nh v cc phn t nh ngi ta dng phng php a hp a ch, mi t nh c chn khi
c hai a ch hng v ct c ln lt tc ng. Phng php ny cho php n ng a
ch truy xut c 2
2n
v tr nh. Nh vy gin thi gian ca RAM ng thng khc vi
gin thi gian ca RAM tnh v ROM.

7.3.3.1 RAM tnh (Static RAM, SRAM)
Mi t bo RAM tnh l mt mch FlipFlop dng Transistor BJT hay MOS (H 7.17)

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B nh bn dn VII - 13



(a) (H 7.17) (b)

(H 7.17a) l mt t bo nh RAM tnh dng transistor BJT vi 2 ng a ch hng
v ct.
Khi mt trong hai ng a ch hng hoc ct mc thp cc t bo khng c
chn v cc E c in th thp hai Transistor u dn, mch khng hot ng nh mt FF.
Khi c hai a ch hng v ct ln cao, mch hot ng nh FF, hai trng thi 1 v 0 ca t
bo nh c c trng bi hai trng thi khc nhau ca 2 ng bit v bit .
Gi s khi T
1
dn th T
2
ngng, ng bit c dng in chy qua, to in th cao R
3

trong khi ng bit khng c dng chy qua nn R
4
c in th thp. Nu ta qui c
trng thi ny tng ng vi bit 1 th trng thi ngc li, l trng thi T
1
ngng v T
2
dn,
hiu th in tr R
3
thp v R
4
cao, s l bit 0. R
3
v R
4
c tc dng bin i dng in ra
in th.
i vi t bo nh dng MOS, hai ng t ni vi T
5
, T
6
v T
7
, T
8
nn khi mt trong
hai ng t mc thp T
1
v T
2
b c lp khi mch, t bo nh khng c chn. Khi c
hai ln cao mch hot ng tng t nh trn. Trong mch ny R
1
v R
2
thay bi T
3
v T
4
v
khng cn R
3
v R
4
nh mch dng BJT.
(H 7.18) l mch iu khin chn chip v thc hin tc v c/vit vo t bo nh.


(H 7.18)

OPAMP gi vai tr mch so snh in th hai ng bit v bit cho ng ra mc cao
hoc thp ty kt qu so snh ny (tng ng vi 2 trng thi ca t bo nh) v d liu c
c ra khi cng m th 2 m ( W R/ ln cao).
Khi cng m th nht m ( W R/ xung thp) d liu c ghi vo t bo nh qua
cng m 1. Cng 3 to ra hai tn hiu ngc pha t d liu vo. Nu hai tn hiu ny cng
trng thi vi hai ng bit v bit ca mch trc , mch s khng i trng thi ngha l
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B nh bn dn VII - 14

nu t bo nh ang lu bit ging nh bit mun ghi vo th mch khng thay i. By gi,
nu d liu cn ghi khc vi d liu ang lu tr th mch FF s thay i trng thi cho ph
hp vi 2 tn hiu ngc pha c to ra t d liu. Bit mi c ghi vo.

- Chu k c ca SRAM
Gin thi gian mt chu k c ca SRAM tng t nh gin thi gian mt chu
k c ca ROM (H 7.11) thm iu kin tn hiu W R/ ln mc cao.

- Chu k vit ca SRAM
(H 7.19) l gin thi gian mt chu k vit ca SRAM
Mt chu k vit t
WC
bao gm:
- t
AS
(Address Setup time): Thi gian thit lp a ch : Thi gian gi tr a ch n
nh trn bus a ch cho ti lc tn hiu CS tc ng.
- t
W
(Write time): Thi gian t lc tn hiu CS tc ng n lc d liu c gi tr trn
bus d liu.
- t
DS
v t
DH
: Khong thi gian d liu tn ti trn bus d liu bao gm thi gian trc
(t
DS
) v sau (t
DH
) khi tn hiu CSkhng cn tc ng
- t
AH
(Address Hold time): Thi gian gi a ch: t lc tn hiu CSkhng cn tc
ng n lc xut hin a ch mi.


(H 7.19)

7.3.3.2 RAM ng (Dynamic RAM, DRAM)
(H 7.20a) l mt t bo nh ca DRAM

(a) (H 7.20) (b)

(H 7.20b) l mt cch biu din t bo nh DRAM trong n gin mt s chi tit
c dng m t cc tc v vit v c t bo nh ny.
Cc kha t S
1
n S
4
l cc transistor MOS c iu khin bi cc tn hiu ra t
mch gii m a ch v tn hiu W R/ .
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B nh bn dn VII - 15

ghi d liu vo t bo, cc kha S
1
v S
2
ng trong khi S
3
v S
4
m. Bit 1 thc
hin vic np in cho t C v bit 0 lm t C phng in. Sau cc kha s m c lp C
vi phn mch cn li. Mt cch l tng th C s duy tr trng thi ca n vnh vin nhng
thc t lun lun c s r in qua cc kha ngay c khi chng m do C b mt dn in
tch .
c d liu cc kha S
2
, S
3
, S
4
ng v S
1
m, t C ni vi mt mch so snh vi
mt in th tham chiu xc nh trng thi logic ca n. in th ra mch so snh chnh l
d liu c c ra. Do S
2
v S
4
ng, d liu ra c ni ngc li t C lm ti n. Ni
cch khc, bit d liu trong t bo nh c lm ti mi khi n c c.
S dng DRAM, c mt thun li l dung lng nh kh ln nhng phi c mt s
mch ph tr:
- Mch a hp a ch v DRAM lun s dng a ch hng v ct
- Mch lm ti phc hi d liu c th b mt sau mt khong thi gian ngn no
.
a. a hp a ch
Nh ni trn, do dung lng ca DRAM rt ln nn phi dng phng php a
hp chn mt v tr nh trong DRAM. Mi v tr nh s c chn bi 2 a ch hng v
ct ln lt xut hin ng vo a ch.
Th d vi DRAM c dung lng 16Kx1, thay v phi dng 14 ng a ch ta ch
cn dng 7 ng v mch a hp 14 7 (7 a hp 21) chn 7 trong 14 ng a ch
ra t CPU (H 7.21). B nh c cu trc l mt ma trn 128x128 t bo nh, sp xp thnh 128
hng v 128 ct, c mt ng vo v mt ng ra d liu, mt ng vo W R/ . Hai mch cht
a ch (hng v ct) l cc thanh ghi 7 bit c ng vo ni vi ng ra mch a hp v ng ra
ni vi cc mch gii m hng v ct. Cc tn hiu S RA v S CA dng lm xung ng h
cho mch cht v tn hiu Enable cho mch gii m. Nh vy 14 bit a ch t CPU s ln
lt c cht vo cc thanh ghi hng v ct bi cc tn hiu S RA v S CA ri c gii m
chn t bo nh. Vn hnh ca h thng s c thy r hn khi xt cc gin thi gian
ca DRAM.


(H 7.21)

b. Gin thi gian ca DRAM
(H 7.22) l gin thi gian c v vit tiu biu ca DRAM (Hai gin ny ch
khc nhau v thi lng nhng c chung mt dng nn ta ch v mt)
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(H 7.22)
Gin cho thy tc ng ca tn hiu X MU v cc tn hiu S RA v S CA . Khi
X MU mc thp mch a hp cho ra a ch hng (A
0
. . . A
6
) v c cht vo thanh ghi
khi tn hiu S RA xung thp. Khi X MU mc cao mch a hp cho ra a ch ct (A
7
. . .
A
13
) v c cht vo thanh ghi khi tn hiu S CA xung thp. Khi c a ch hng v ct
c gii m, d liu ti a ch xut hin trn bus d liu c ra hoc ghi vo ( kh
dng)

c. Lm ti DRAM
DRAM phi c lm ti vi chu k khong 2ms duy tr d liu.
Trong phn trc ta thy t bo nh DRAM c lm ti ngay khi tc v c
c thc hin. Ly th d vi DRAM c dung lng 16Kx1 (16.384 t bo) ni trn, chu k
lm ti l 2 ms cho 16.384 t bo nh nn thi gian c mi t bo nh phi l 2 ms/16.384
= 122 ns. y l thi gian rt nh khng c mt t bo nh trong iu kin vn hnh
bnh thng. V l do ny cc hng ch to thit k cc chip DRAM sao cho mi khi tc
v c c thc hin i vi mt t bo nh, tt c cc t bo nh trn cng mt hng
s c lm ti. iu ny lm gim mt lng rt ln tc v c phi thc hin lm ti
t bo nh. Tr li th d trn, tc v c lm ti phi thc hin cho 128 hng trong 2 ms.
Tuy nhin va vn hnh trong iu kin bnh thng va phi thc hin chc nng lm
ti ngi ta phi dng thm mch ph tr, gi l iu khin DRAM (DRAM controller)
IC 3242 ca hng Intel thit k s dng cho DRAM 16K (H 7.23)
Ng ra 3242 l a ch 7 bit c a hp v ni vo ng vo a ch ca DRAM.
Mt mch m 7 bit kch bi xung ng h ring cp a ch hng cho DRAM trong sut
thi gian lm ti. 3242 cng ly a ch 14 bit t CPU a hp n vi a ch hng v ct
c dng khi CPU thc hin tc v c hay vit. Mc logic p dng cho cc ng REFRESH
ENABLE v ROW ENABLE xc nh 7 bit no ca a ch xut hin ng ra mch
controller cho bi bng

REFRESH ROW
ENABLE ENABLE
Controller
output
HIGH X
LOW HIGH
LOW LOW
Refresh address (t mch m)
a ch hng (A
0
. . . A
6
t CPU)
a ch ct (A
7
. . .A
13
t CPU)

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(H 7.23)
7.4 M RNG B NH
Cc IC nh thng c ch to vi dung lng nh c gii hn, trong nhiu trng
hp khng th tha mn yu cu ca ngi thit k. Do m rng b nh l mt vic lm
cn thit. C 3 trng hp phi m rng b nh.

7.4.1. M rng di t
y l trng hp s v tr nh cho yu cu nhng d liu cho mi v tr nh th
khng . C th hiu c cch m rng di t qua mt th d
Th d: M rng b nh t 1Kx1 ln 1Kx8 :
Chng ta phi dng 8 IC nh 1Kx1, cc IC nh ny s c ni chung bus a ch v
cc ng tn hiu iu khin v mi IC qun l mt ng bit. 8 IC s vn hnh cng lc
cho mt t nh 8 bit (H 7.24).

(H 7.24)

7.4.2 M rng v tr nh
S bit cho mi v tr nh theo yu cu nhng s v tr nh khng
Th d: C IC nh dung lng 1Kx8. M rng ln 4Kx8. Cn 4 IC. chn 1 trong 4
IC nh cn mt mch gii m 2 ng sang 4 ng, ng ra ca mch gii m ln lt ni
vo cc ng CS ca cc IC nh, nh vy a ch ca cc IC nh s khc nhau (H 7.25). Trong
th d ny IC1 chim a ch t 000H n 3FFH, IC2 t 400H n 7FFH, IC3 t 800H n
BFFH v IC4 t C00H n FFFH

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(H 7.25)

7.4.3 M rng dung lng nh
C v tr nh v di t ca cc IC u khng thit k. m rng dung lng
nh ta phi kt hp c hai cch ni trn
Th d: M rng b nh t 4Kx4 ln 24Kx8. Cn 6 cp IC mc song song, mi cp IC c
chung a ch v c chn bi mt mch gii m 3 sang 8 ng (H 7.26). Ta ch dng 6
ng ra t Y
0
n Y
5
ca mch gii m

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(H 7.26)
- a ch IC (1&2): 0000H - 0FFFH, IC (3&4) : 1000H - 1FFFH, IC (5&6): 2000H -
2FFFH v IC (7&8) : 3000H - 3FFFH IC (9&10): 4000H - 4FFFH v IC (11&12) :
5000H - 5FFFH
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BI TP

1. Dng IC PROM 4 ng vo v 4 ng ra thit k mch chuyn m t Gray sang nh phn ca
s 4 bit.

2. Dng IC PAL 4 ng vo v 4 ng ra thit k mch chuyn t m Excess-3 sang m Aiken
ca cc s t 0 n 9.
Di y l 2 bng m
Excess-3 Aiken

N A B C D A B C D
0
1
2
3
4
5
6
7
8
9
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
1
1
1
1
0
0
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1

3. Thit k mch m rng b nh t 2Kx4 ln 2Kx8

4. Thit k mch m rng b nh t 1Kx4 ln 8Kx4.
Cho bit a ch c th ca cc IC

5. Thit k mch m rng b nh t 2Kx4 ln 16Kx8.
Cho bit a ch c th ca cc IC





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