INTRODUCTION TO MICRO COMPUTER AND MICROPROCESSOR

Introduction
A Microprocessor is a multipurpose programmable logic device which reads the binary
instructions from a storage device called Memory , accepts binary data as input and
process data according to the instructions and gives the results as output. So, you can
understand the Microprocessor as a programmable digital device, which can be used for
both data processing and control applications. In view of a computer student, it is the C!
of a Computer or heart of the computer. A computer which is built around a
microprocessor is called a microcomputer. A microcomputer system consists of a C!
"microprocessor#, memories "primary and secondary# and I$% devices as shown in the
bloc& diagram in Fig 1. 'he memory and I$% devices are lin&ed by data and address
"control# buses. 'he C! communicates with only one peripheral at a time by enabling
the peripheral by the control signal. (or e)ample to send data to the output device, the
C! places the device address on the address bus, data on the data bus and enables the
output device. 'he other peripherals that are not enabled remain in high impedance state
called tri*state.
Fig.1 Block diagram o a Microcom!ut"r
E#olution o Micro!roc"$$or$
1
'he first Microprocessor "+,,+# was designed by Intel Corporation which was founded by
Moore and -oyce in ./01. In the early years, Intel focused on developing semiconductor
memories "23AMs and 43%Ms# for digital computers. In ./0/, a 5apanese Calculator
manufacturer, 6usicom approached Intel with a design for a small calculator which need
.7 custom chips. 'ed 8off, an Intel 4ngineer thought that a general purpose logic device
could replace the multiple components. 'his idea led to the development of the first so
called microprocessor. So, Microprocessors started with a modest beginning of drivers for
calculators. (edrico (aggin and Stanely Ma9or implemented the ideas of 'ed 8offs and
designed the Intel +,,, family of processors comprising +,,. "7:*3%M#, the +,,7 ";7,
bit 3AM#, the +,,; "., bit I$% shift*register# and the +,,+, a + bit C!. Intel introduced
the +,,+ microprocessor to the world wide mar&et on -ovember .<, ./=.. It was a +*bit
M%S chip with 7;,, transistors. Around the same time 'e)as Instruments developed a
+*bit microprocessor 'MS .,,, and became the owner of microprocessor patent. >ater
Intel introduced worlds first 1 bit general purpose microprocessor 1,,1 in ./=7. 'his
processor was used in the popular computer Mar&*1 in those days. In ./=+, Intel
introduced the improved version of 1,,1, the 1,1, microprocessor. 'his 1,1, is the much
more highly integrated chip than its predecessors which is built around -*channel M%S
technology. It could e)ecute up to 7/,,,,, operations per second and could address up to
0+:.bytes of memory. 'he other notable 1 bit microprocessors include Motorola 01,,,
3oc&well S*1 and Signetics 70<, with powerful architecture and instruction set.
?ith developments in integration technology Intel was able to integrate the additional chips li&e
177+ cloc& generator and the 1771 system controller along with 1,1, microprocessor with
in a single chip and released the 1 bit microprocessor 1,1< in the year ./=0. 'he 1,1<
microprocessor consisted of 0<,, M%S transistors and could wor& at cloc& fre@uencies of
;*< M89. It wor&s on a single A< volts supply. 'he other improved 1 bit microprocessors
include Motorola MC 01,/, Bilog B*1, and 3CA C%SMAC.
In ./=1, Intel introduced the .0 bit microprocessor 1,10 and 1,11 in ./=/. I6M selected
the Intel 1,11 for their personal computer "I6M*C#.1,10 microprocessor made up of
7/,,,, M%S transistors and could wor& at a cloc& speed of <*., M89. It has a .0*bit A>!
with .0*bit data bus and 7,*bit address bus. It can address up to .M6 of address space.
'he pipelining concept was used for the first time to improve the speed of the processor. It
had a pre*fetch @ueue of 0 instructions where in the instructions to be e)ecuted were
fetched during the e)ecution of an instruction. It means 1,10 architecture supports parallel
processing. 'he 1,11 microprocessor is similar to 1,10 processor in architecture ,but the
basic difference is it has only 1*bit data bus even though the A>! is of .0*bit.It has a pre*
fetch @ueue of +*instructions only.
In ./17 Intel released another .0*bit processor called 1,.10 designed by a team under the
leadership of 2ave Stamm. 'his is having higher reliability and faster operational speed
but at a lower cost. It had a pre*fetch @ueue of 0*instructions and it is suitable for high
volume applications such as computer wor&stations, word*processor and personal
computers. It is made up of .;+,,,, M%S transistors and could wor& at cloc& rates of +
and 0 M89. 'his is also comes under first generation of Microprocessors.
Intel released another .0 bit microprocessor 1,710 having ., ;+,,,, transistors in ./1.. It was
used as C! in C*A's in ./17. It is the second generation microprocessor, more
advanced to 1,.10 processor. It could run at cloc& speeds of 0 to .7.< M89 .It has a .0*
bit data bus and 7+*bit address bus, so that it can address up to .0M6 of address space
and .C6 of virtual memory. It had a pre*fetch @ueue of 0 instructions .Intel introduced the
concept of protected mode and virtual mode to ensure proper operation. It also had on*
chip memory management unit "MM!# .'his was popularly called as Intel 710 in those
days.
2
In ./1<, Intel released the first ;7 bit processor 1,;10, with 7=<,,,, transistors. It has ;7*
bit data bus and ;7*bit address bus so that it can address up to a total of +C6 memory
also a virtual memory space of 0+'6.It could process five million instructions per second
and could wor& with all popular operating systems including ?indows. It has a pre*fetch
@ueue of length .0*bytes with e)tensive memory management capabilities. It is
incorporated with a concept called paging in addition to segmentation techni@ue. It uses a
math co*processor called 1,;1=.
Intel introduced 1,+10 microprocessor with a built*in maths co*processor and with ..7
million transistors. It could run at the cloc& speed of <, M89 'his is also a ;7 bit processor
but it is twice as fast as 1,;10.'he additional features in +10 processor are the built*in
Cache and built*in math co*processors. 'he address bus here is bidirectional because of
presence of cache memory.
%n ./
th
%ctober, .//7, Intel released the entium*I rocessor with ;.. million transistors. So,
the entium began as fifth generation of the Intel )10 architecture. 'his entium was a
bac&ward compatible while offering new features. 'he revolutionary technology followed is
that the C! is able to e)ecute two instruction at the same time. 'his is &nown as super
scalar technology. 'he entium uses a ;7*bit e)pansion bus, however the data bus is 0+
bits.
'he =.< million transistors based chip, Intel entium II processor was released in .//=. It
wor&s at a cloc& speed of ;,,M.89. entium II uses the 2ynamic 4)ecution 'echnology
which consists of three different facilities namely, Multiple branch prediction, 2ata flow
analysis, and Speculative e)ecution unit. Another important feature is a thermal sensor
located on the mother board can monitor the die temperature of the processor. (or
thermal management applications.
Intel Celeron rocessors were introduced in the year .///. entium*III processor with /.< million
transistors was introduced in .///. It also uses dynamic e)ecution micro*architecture, a
uni@ue combination of multiple branch prediction, dataflow analysis and speculative
e)ecution. 'he entium III has improved MMD and processor serial number feature. 'he
improved MMD enables advanced imaging, ;2 streaming audio and video, and speech
recognition for enhanced Internet facility.
entium*IE with +7 million transistors and ..< C89 cloc& speed was released by Intel in
-ovember 7,,,. 'he entium + processor has a system bus with ;.7 C*bytes per second
of bandwidth. 'his high bandwidth is a &ey reason for applications that stream data from
memory. 'his bandwidth is achieved with 0+ Fbit wide bus capable of transferring data at
a rate of +,, M89. 'he entium + processor enables real*time M4C7 video encoding
and near real*time M4C+ encoding, allowing efficient video editing and video
conferencing.
Intel with partner 8ewlett*ac&ard developed the ne)t generation 0+*bit processor architecture
called IA*0+ .'his first implementation was named Itanium. Itanium processor which is the
first in a family of 0+ bit products was introduced in the year 7,,..'he Itanium processor
was specially designed to provide a very high level of parallel processing ,to enable high
performance without re@uiring very high cloc& fre@uencies .:ey strengths of the Itanium
architecture include ,up to 0 instructions$cycle. 'he Itanium processor can handle up to 0
simultaneous 0+ Fbit instructions per cloc& cycle.
3
'he Itanium II is an IA*0+ microprocessor developed Gointly by 8ewlett*ac&ard "8#
and Intel and released on 5uly 1,7,,7..It is theoretically capable of performing nearly 1
times more wor& per cloc& cycle than other CISC and 3ISC architectures due to its
parallel computing micro*architecture. 'he recent Itanium processor features a split >7
cache, adding a dedicated .M6 >7 cache for instructions and thereby effectively growing
the original 7<0:6>7 cache, which becomes a dedicated data cache. 'he first Itanium 7
processor "code named Mc:inley# was more powerful than the original Itanium processor,
with appro)imately two times performance.
entium +44 was released by Intel in the year 7,,; and entium +4 was released in the
year 7,,+.
'he entium 2ual*Core brand was used for mainstream D10*architecture
microprocessors from Intel from 7,,0 to 7,,/ 'he 0+ bit Intel Core7 was released on 5uly
7=,7,,0. In terms of features, price and performance at a given cloc& fre@uency, entium
2ual*Core processors were positioned above Celeron but below Core and Core 7
microprocessors in IntelHs product range. 'he entium 2ual*Core was also a very popular
choice for over cloc&ing, as it can deliver optimal performance "when over cloc&ed# at a
low price.
'he entium 2ual Core, which consists of .0= million transistors was released on 5anuary 7.,
7,,=. Intel Core 2uo consists of two cores on one die, a 7 M6 >7 cache shared by both
cores, and an arbiter bus that controls both >7 cache and (S6 access.
Core 7 Iuad processors are multi*chip modules consisting of two dies similar to those used in
Core 7 2uo, forming a @uad*core processor. ?hile this allows twice the performance to a
dual*core processors at the same cloc& fre@uency in ideal conditions, this is highly
wor&load specific and re@uires applications to ta&e advantage of the e)tra cores.
In September.7,,/, new Core i= models based on the >ynnfield des&top @uad*core processor
and the Clar&sfield @uad*core mobile were added, and models based on the Arrandale
dual*core mobile processor have been announced. 'he first si)*core processor in the
Core lineup is the Culftown, which was launched on March .0, 7,.,. 6oth the regular
Core i= and the 4)treme 4dition are advertised as five stars in the Intel rocessor 3ating.
T%" Int"l &'&( Micro!roc"$$orJ
Intel 1,1<A is a single chip 1*bit -*channel microprocessor which wor&s at A<E 2C power
supply. It is a +, pin IC available as a 2I "2ual Inline ac&age# chip. 1,1<A can operate
with a ;M8B single phase cloc& and 1,1<A*7 version can operate at a ma)imum
fre@uency of <M8B. 'his 1,1< is an enhanced version of its predecessor the 1,1,A. Its
instruction set is upward compatible with that of the 1,1,A. 1,1<A has an on*chip cloc&
generator with e)ternal crystal, >C or 3C networ&. 'his 1,1< microprocessor is built with
nearly 07,, transistors. 'he enhanced version of 1,1, is the Intel 1,1<A8. It is an -
channel depletion load, silicon gate "8M%S# 1*bit processor. 8ere ;M8B, <M8B and
0M8B selections are available. It has 7,K lower power consumption than 1,1<A for
;M8B and <M8B. Its instruction set is .,,K software compatible with the 1,1<A. It is also
.,,K compatible with 1,1<A.
C"ntral Proc"$$ing Unit )CPU*
'he Central rocessing !nit of any microcomputer is the microprocessor. 8ence
microprocessor is also &nown as the heart of the computer. 'he C! performs the various
activities in response to a set of instructions called a program. rograms are stored in the
memory. 'he C! reads in data control signals "instructions# through the input ports and
e)ecutes one instruction at a time. So, generally spea&ing, a microprocessor is nothing but the
C! .'he Intel 1,1< C! is an 1*bit device with a cloc& speed of ; * < M8B. It has 1, basic
instructions and 7+0 op*codes. Its cloc& cycle is ;7, ns. 'he time for the cloc& cycle of Intel 1,1<
is 7,, ns. 'he bloc& diagram of 1,1< microprocessor is shown in Fig +. 'he 1,1< C! consists
of three maGor sections,
4
'hey areJ
"i#. Arithmetic and logic unit "A>!#
"ii#.3egisters
"iii#.'iming and Control unit.
Arit%m"tic and logic unit )A,U*
'he A>! performs all the arithmetic and logical operations li&e addition, subtraction,
complementing, logical A-2, logical %3, logical 4)clusive %3, incrementing and decrementing,
rotate, shift and clear. An A>! is made of many logic gates and adders etc.
'he arithmetic and logic unit consists of the following units
"a#.Accumulator "A#.
"b#.'emporary register.
"c#.(lag register.
)a* Accumulator )A*-
It is an 1*bit register which is treated as a special function register. Most of the arithmetic
and logic operations are performed using this accumulator. All the I$% data transfers between
1,1< and I$% devices are performed via accumulator. %ne of the operands for arithmetic
operations in A>! is from the accumulator. After performing the arithmetic operations the result is
stored bac& in accumulator. It is from the accumulator only, the data is sent out to an output
device. Similarly, the data from an input device is read only through the accumulator. 'he data in
the accumulator alone can be rotated or shifted. -o other register can be used for these
operations. Certain instructions li&e 2AA are performed using only accumulator. So, many times
the Accumulator register is treated as a default register.
5
Figur" + .T%" Block Diagram o &'&( Micro!roc"$$or
).* T"m!orar/ r"gi$t"r-
6
'his is an 1*bit register which is not accessible to the user. 'his register is used by the
microprocessor to load the second operand during arithmetic$logical operations in A>!. 'he final
result is stored in the Accumulator and the flags are set or reset according to the result of the
operation. (or e)ample when MEI M, .=8 instruction is fetched, I3 register will receive the
opcode for MEI M and the 'emporary register will receive .=8.
In arithmetic and logical operations, that involves two operands ,the accumulator provides one
operand. 'he other is provided by the temporary register. (or e)ample in A22 C
instruction C register contents are moved to the 'emp. 3egister and the addition of A and
'emp. 3egister contents is performed by the A>!.
"c#.(lag registerJ 'he flag register is an 1* bit register which generally reflect data conditions in
the accumulator with certain e)ceptions. 8ence this flag register is also &nown as Status
register. 'hough this flag register is an eight bit register, it contains only < flag bits and the
remaining three bits are undefined as shown in (ig.;.; In the (lag register each flag bit is
a (lip*(lop. i.e., the bit may be either in the flip state or flop state
Figur" 0. Flag R"gi$t"r
S 1 Sign Flag
After e)ecution of an arithmetic and logic operation, if bit 2
=
of the result "-ormally in the
Accumulator# is ., the sign flag is set. 'his (lag is used with signed numbers.(or e)ample
in a given byte, if 2
=
is ., the number is treated as a negative number. 4lse "if it is 9ero#, it
is viewed as a positive. In arithmetic operations with signed numbers bit 2
=
is reserved
for indicating the sign and the remaining seven bits are used to denote the magnitude of
the number.
2 1 2"ro Flag
'his (lag is set "made .# if the result after any arithmetic operation is 9ero, and the flag is reset
"made ,# if the result is not 9ero. So, this flag is set or reset based on the results in the
accumulator as well as in the other registers.
AC 3 Au4iliar/ carr/ Flag
In this arithmetic operation, when a carry is generated by and passed on to bit + , the AC flag is
set. 'his flag is used internally for 6C2 arithmetic and is not available for the programmer
to change the se@uence of a program with a Gump instruction. 6ut the B and CL flags can
be used for this purpose.
P1Parit/ Flag
If the result after an arithmetic and logical operation has an even number of .s, this parity flag is
set to . otherwise "if number of .s is odd# the flag is reset "made,#.
(or e)ample the data byte .,....,. has even parity and the data byte .,,..,.. has odd parity.
So bitM,.
C51Carr/ lag
After an arithmetic operation, li&e addition, subtraction if there e)ists a carry or barrow, this flag
CL is set to . else it is reset "made,#
E4am!l" J >et us consider the addition of two binary numbers ..,..,,. and ...,..,. and
chec& the (lag register.
7

2
=
2
,

. . , . . , , .
. . . , . . , .

. . , , , . . ,
In the result, the sum is not 9ero, So B*(lag is reset "BM,#.
'here is a carry from the third bit to fourth bit. So AC (lag is set "ACM.#.
'he 2
=
bitM., so, the sign (lag is set "SM.#.
In the result, the no. of .s is even. So, parity is even "M.#.
After addition, there is a carry. So carry (lag is set "CLM.#.
'he (lag register contents after addition are shown belowJ
2
=
2
,
R"gi$t"r Organi6ation

'he 1,1< microprocessor has different types of registers. It includes si) , 1 F bit registers
"6, C, 2. 4, 8 and >#, one 1*bit Accumulator and two .0*bit registers "S and C#. Also there are
two 1*bit temporary registers ? and B. Among these registers ? and B are not accessible to the
user, 'hey are used by the processor for internal, intermediate operations. 'he remaining
registers are accessible to the user. 'he organi9ation of 1,1< registers is shown in Fig. 0.7
'he various registers of 1,1< are classified into three types. 'hey are
"i#.'emporary registers.
"ii#.Ceneral purpose registers
"iii#.Special purpose registers.
)i* T"m!orar/ r"gi$t"r$ -
'he 'emporary registers are temporary data registers, ? register and B register. All are 1*
bit registers. 'he temporary data register is associated with the A>! operations. %ne of the
operand is stored in this register. 'his is not accessible to user.
Similarly ? and B are also temporary registers used to hold 1*bit data during e)ecution of certain
instructions.As these registers are internally used by the C!, they are not accessible to
the user.
'he ? and B registers are used by the processor during CA>> instruction. ?hen a CA>>
instruction is encountered in any program, the current rogram counter "C# contents are
pushed on to the stac& and the given address is loaded on to C. 'he given address is
temporarily stored in ? and B registers and placed on the bus for the fetch cycle. 'hus the
program control is transferred to the address given in the instruction.
Another e)ample is, during the e)ecution of DC8C instruction, the contents of 8*> pair are
e)changed with 2*4 pair. At the time of e)change ? and B registers are used for
temporary storage of data.
)ii* 8"n"ral !ur!o$" r"gi$t"r$ J
8
1
6, C, 2, 4, 8 and > are si), 1*bit general purpose registers to store data. 'hese registers
can be used as separate 1*bit registers and also can be paired as .0*bit registers to store the
address of a memory location. 6ut they must be paired as 6*CN 2*4 and 8*> register pairs only
as shown below.

Figur" 7. R"gi$t"r organi6ation
?hen used as pair, for e)ample 6*C, the higher order byte moves to the first register "6# and the
low order byte moves to the second register "C#. 'he 8*> pair also functions as a data
pointer or memory pointer
(or 4)J >DI 8, 1<,, 8.
'his will load immediately the address of memory location "1<,,8# in to 8*> pair .-ow the 8*>
pair points to the location 1<,, 8.
)iii* S!"cial !ur!o$" r"gi$t"r$-
'he Special purpose registers ,as their name indicates, are used for some specific
purpose. 'he Special purpose registers are Accumulator "A#, (lag 3egister, Instruction
3egister"I3#, rogram Counter "C# and Stac& ointer "S#.
Accumulator "3egister A#J It is an 1*bit tri*state register. It is mainly used for arithmetic, logic, load
and store operations. It is also used in I$% operations. In most of operations, the result is
stored in Accumulator after e)ecution.
(lag 3egisterJ It is an 1*bit register, ?hich consists of only five flags.4ach flag bit is a flip flop that
indicates either a set or reset state. 'he five flags are Sign, Bero, Au)iliary carry, arity
and
Carry as shown below
8ere D means undefined.
9
Sign Flag- 'he sign flag is set to. if the most significant bit of the result of an arithmetic or logic
operations is .. 4lse it is reset ",#.
2"ro Flag- 'he Bero status flag is set to . if the result of an arithmetic or logic operation is Bero
(or non*Bero result it is reset to ,.C
Au4iliar/ carr/ Flag- 'his flag is set if there is a carry from ;
rd
bit to +
th
bit during 6C2 operations
"carry from lower nibble to higher nibble#. 'his flag is not accessible to the user.
Parit/ Flag- arity is defined by the number of .s present in a binary number stored in A register.
After any arithmetic or logical operation, if the result has an even number of .s it is called
even parity and the arity (lag is set to .. %therwise. i.e. If there is odd number of .s in
the result, it is called %dd arity and the arity flag is set ,.
Program Count"r )PC*-
It is a .0*bit special purpose register, which stores the address of the ne)t instruction to be
fetched or e)ecuted. 'he e)ecution of a program is initiated by loading the C by the address of
the first instruction of the program. %nce the first instruction is e)ecuted, the C is automatically
incremented to point to the ne)t instruction unless a Gump to some specific address occurs. 'his
process is repeated till the last instruction of the program.
In case of 5!M or CA>> instructions, current address is stored in the rogram Counter.
'he processor then fetches the ne)t instruction from the new address specified by the
5!M or CA>> instruction. In conditional 5!M and conditional CA>> instructions, if the
condition is not satisfied, the processor increments the rogram Counter by three so that it
points the instruction followed by the conditional 5!M or CA>> instruction. %therwise the
processor fetches the ne)t instruction from the new address specified by 5!M or CA>>
instruction.
Stack Point"r )SP*-
It is a .0*bit special purpose register which always stores the address of top of the Stac&.
i.e. it always points to top of the Stac&. Stac& is a part of the memory location used to store the
data temporarily. A stac& wor&s on >ast in (irst out ">I(%# basis. As the Stac& pointer always
points to the top of the Stac&, only top of the Stac& of the memory can be accessed. ?hen a
?rite operation "!S8# ta&es place, the contents of the stac& pointer is decremented by two so
that the S points to the new location. Similarly when the 3ead operation "%# occurs, the
Stac& pointer is incremented by two to point to the ne)t data on top of the Stac&.
'he Stac& ointer is initiali9ed by load register pair immediate instruction.
4)J >DI S, 1<;, 8
8ere 1<;, 8 is the .0 bit address of the top of Stac& location.
T%" r"maining .lock$ o &'&( micro!roc"$$or .lock diagram
In$truction R"gi$t"r and D"cod"r- T%" instruction register and the decoder are also part of the
A>!. ?hen an instruction is fetched from memory, it is loaded in the instruction register.
'he 2ecoder decodes the instruction and develops the se@uence of events to follow. 'he
instruction register is a 1 F bit special register, but it is not a programmable and is not
accessible to the user. 'he instruction decoder decodes the instruction at a binary level
and sends the appropriate signals to the control unit.
10
Incr"m"nt9 D"cr"m"nt Addr"$$ ,atc%- 'his is a .0 bit special register not accessible to the
user. 'his register is used by the C! to increment$ decrement the contents of the Stac&
ointer "S# and increment program counter "C# during instruction e)ecution. 2uring first
' * state of op code fetch machine cycle "'
.
# the microprocessor increments the C
register contents to point to the ne)t location. 'his increment operation ta&es place on
increment$ decrement register address latch. 'he .0 bit address that is sent out through
A2
,
*A2
=
and A
1
*A
.<
are latched into this register. 'he address bus A2
,
*A2
=
continues to be
available on the bus after '
.
state from this latch.
Addr"$$ Bu"r- 'his is an 1*bit unidirectional buffer. It is used to drive e)ternal higher order
address bus. It is also used to tri*state the higher order address "A
1
*A
.<
# bus under certain
conditions li&e reset, hold, and halt and also when address lines are not in use.
Addr"$$9Data Bu"r- 'his is an 1*bit bi*directional buffer. It is used to drive multiple)ed
address$data bus. It means low order address bus "A
=
*A
,
# and data bus "2
=
*2
,
#. It is also
used to tri*state the multiple)ed address$data bus under certain conditions li&e reset, hold,
and halt and also when A$2 bus lines are not in use.
'he address and data bus buffers are used to drive e)ternal address and data buses
respectively. 2ue to these buffers the address and data buffers can be tri*stated when
they are not in use. In actual practice, in a microprocessor the driving capacity of the
address pins after the internal buffering may not be ade@uate. So, there will be e)ternal
buffer chips also available.
S"rial I9O control-
'his control provides two lines S%2 "Serial %ut 2ata# and SI2 "serial In 2ata# for serial
communication. 'hese lines are used during serial data transmission over long distance
where data is transmitted and received bit by bit. 'he Serial %utput 2ata "S%2# pin is
used to send data out serially and serial Input 2ata "SI2# pin is used to receive data
serially by the 1,1< microprocessor.
Int"rru!t control-
'his is an important bloc& related to interrupts. 'his bloc& is lin&ed to the C! through the
1*bit internal data bus. 'his interrupt control has five interrupt signals. 'hey are '3A,
3S' =.<, 3S' 0.<, 3S' <.< and I-'3. 'he control bloc& will ta&e care of enabling and
disabling of these interrupts etcO
&'&( Int"rru!t$-
'he 1,1< microprocessor has five interrupts. 'hey are '3A, 3S' =.<, 3S' 0.<, 3S'<.< and
I-'3. Among all these interrupts '3A has the highest priority and I-'3 "Interrupt
3e@uest# has the lowest priority. 'he '3A is also a non mas&able interrupt. 'he numbers
succeeding the 3S' "=.<, 0.<, and <.<# are related to the call locations. 'he various
interrupts, their locations in the order of highest to lowest priority are given in 'able ;...
8ere 3S' means 34S'A3'. Among these interrupts I-'3 is the only non*vector interrupt
whereas the other interrupts are vectored interrupts.
TRAP- It is a non mas&able interrupt with highest priority. It means that whenever the pin is
activated, the 1,1< will always get interrupted even if the 1,1< is in 2I "2isable Interrupt#
state. 'rap input is both edge and level sensitive. So, the microprocessor is interrupted
when the input is both edge and level sensitive. So, the microprocessor is interrupted
when the input pulse goes from low to high or when it remains high .?hen interrupted, the
microprocessor loads the program counter with ,,7+8.
11
RST :.(- It is an edge sensitive pin. Internal to 1,1< there is a flip*flop connected to 3S' =.<
interrupt pin . 'his flip flop is set ., when a positive Fgoing edge occurs on 3S' =.< input.
3S' =.< interrupt has a higher priority than 3S' 0.<, 3S' <.< and I-'3. 'his 3S' =.< is a
mas&able interrupt &nown as MI. 'his interrupt is enabled under program control with two
instructions 4I "4nable Interrupt# and SIM "Set Interrupt Mas&#
RST ;.(and RST (.(- 'hese interrupts are level sensitive, it means the triggering level should
be on until the microprocessor completes the e)ecution of the current instruction. If the
microprocessor is not able to respond to the re@uests immediately, they should be stored
or held by e)ternal hardware. 'hese two interrupts are also mas&able interrupts. 3S' 0.<
and 3S' <.< have higher priority than I-'3 interrupt. 'he condition of these interrupts can
be &nown using 3IM "3ead Interrupt Mas&# instruction and the condition of the mas&ing
interrupt can be set and reset using SIM instruction "Set Interrupt Mas&#.
INTR- It is only non*vectored interrupt in 1,1< microprocessor. 'his interrupt has the lowest
priority among all the interrupts. 'his is also a mas&able interrupt and can be disabled
using the instruction 2I "2isable Interrupt#. 'he mas& on I-'3 can be removed by
e)ecuting 4I "4nable Interrupt# instruction. ?hen 4I instruction is e)ecuted, the flip flop
associated with this is set and the mas& is removed. 'his is a non*vectored interrupt
because when the remaining interrupts are initiali9ed, they are automatically transferred
"vectored# to specific locations on memory page ,,8 without any e)ternal hardware. 'hey
do not re@uire the signal. 'he necessary hardware is already implemented inside
the 1,1<. 6ut coming to I-'3, interrupt, it e)ecutes interrupt ac&nowledge machine cycle.
2uring this cycle, the device that has interrupted this microprocessor will provide the
operation code. 'he signal wor&s as a signal during
ac&nowledge machine cycle. 2uring this time, the microprocessor loads the code into instruction
register from I$% device. 6ased on the code, the remaining operation is e)ecuted by the
processor
Ta.l" 1 . <ariou$ Int"rru!t$ =Call location$ in ord"r o %ig%"$t to lo>"$t !riorit/
Timing and control Unit
'his unit of the microprocessor issues necessary timing and control signals for the
e)ecution of instructions. It generates three types of signals namely status, control and timing
signals re@uired for the operation of memory and I$% devices. 'his unit with the help of these
signals controls the entire operation of the microprocessor and the peripherals. 'he signals
associated with this unit are two control signals. and three status signals I%$ , S
.
and
S
,
to identify the nature of the operation and one special signal A>4 which indicates the starting
of the operation. 'hese signals are e)plained below in detail.
S.- o Interrupts Call locations
.
7
;
+
<
'3A "8ighest priority#
3S' =.<
3S' 0.<
3S' <.<
I-'3 "least priority#
,,7+8
"=.< ) 1#8 M ,,;C8
"0.< ) 1#8 M ,,;+8
"<.< ) 1#8 M ,,7C8
-o location
12
*3ead "active low#J 'his is a 3ead control signal. 'his signal indicates that the selected I$% or
memory device is to be read and data are available on the data bus.
* ?rite "active low#J 'his is a ?rite control signal. 'his signal indicates that the data on the
data bus are to be written into a selected memory or I$% device.
13
Ta.l" +. Statu$ $ignal$ o &'&(

IO9 J 'his is a status signal used to differentiate between I$% and memory operations. ?hen
this signal is high, it indicates an I$% operation, when it is low it denotes a memory
operation. 'his signal is combined with 3ead " # and ?rite to generate necessary
I$% and memory control signals.
S
1
and S
'J
'hese signals are also status signals li&e I%$ , used to identify various operations.
'he complete operation of the microprocessor can be understood by these three signals.
'he various operations and the associated status signals are shown in 'able ;.7 .
A,E )Addr"$$ ,atc% Ena.l"*- 'his is a positive going pulse generated every time the 1,1<
begins an operation, It indicates that the bits on A2
=
* A2
,
are address bits. 'his signal is
used primarily to latch the low*order address from the multiple)ed bus and generate a set
of eight address lines A
=
F A
,
.
Addr"$$= Data and Control Bu$"$-

Intel 1,1< has .0*bit unidirectional address bus which carries the address of memories
and peripheral devices. A bus is nothing but a group of electrical lines used to transmit the
information as electrical signals. So, this .0*bit parallel address bus carries address from
microprocessor to memories$peripherals. 8ence it is !ni*directional"because the converse is not
possible#. 'he width of the parallel bus determines how much memory that a microprocessor can
address.'he 1,1< microprocessor with .0*bit address bus can address a ma)imum of 7
.0
M
0<<;0M0+ :6 of memory locations. 'he si9e of the address bus is independent of the si9e of the
microprocessor.
S. No
IO9
S
1
S
'
Statu$
. , , , Memory ?rite
7 , . , Memory 3ead
; . , . I$% ?rite
+ . . , I$% 3ead
< .$, . . %pcode fetch
0 . . . Interrupt
Ac&nowledge
= P , , 8alt
1 P D D 8old
/ P D D 34S4'
14
In I-'4> 1,1< microprocessor, the 1 most significant bits of the address are transmitted
by the high order address bus A
1
*A
.<
. 6ut the 1 least significant bits of the addresses are
transmitted by Address$2ata bus or A$2 bus. i.e. the lower order address lines are
multiple)ed with the data bus. So, the A$2 bus operates in a time shared mode. i.e. the
data and address are sent on the same lines but at different instants of time. A
,
*A
=
will
always have the address during the first

' state "'
.
# of the machine cycle. 'o demultiple)e
the A$2 bus the pin A>4 is used. ?hen A>4M. "high# the A$2 bus acts as a lower order
address bus else it acts as 2ata bus.
'he 2ata bus is a bidirectional bus which is used to send data to and from the microprocessor.
'his is also a parallel bus. 'he si9e of the data bus determines the si9e of the
microprocessor. 'he 1,1< microprocessor has 1*bit data bus and hence it is called an 1*
bit microprocessor. 'his refers to the width of the data bus but not the address bus.
Similarly1,10 is a .0*bit microprocessor and its data bus width is .0 bits
I-'4> 1,1< has Address$ 2ata bus namely A2
=
*A2
,
. i.e. at some instances it acts as a
1* bit address bus and at other instances it wor&s as a 1*bit data bus. I-'4> used this
time multiple)ing techni@ue to save the pins. Cenerally the si9e of the internal general
purpose registers matches the si9e of the data bus. 'hus, the I-'4>s 1*bit general
purpose registers matches with its 1*bit data bus. 'he si9e of the data bus matches the
si9e of the internal registers, so that all the bits on the bus can at one time come into or
go out of any of the registers.
'he control bus of 1,1< is a uni*directional bus because the microprocessor alone sends
control signals to memories or peripheral devices. 'he si9e of the control bus depends
upon the specific microprocessor. 'ypical control signals are 3ead or ?rite signals. It
means whether the microprocessor operation is a read or writes and whether it is memory
or I$% operation. In addition to this it includes state signals, and address latch enables. A
microprocessor may also have certain additional control signals and such as interrupt
signals, ac&nowledgement signals and hold signals. 6ut they are not considered as part of
control bus even through they ta&e part in control of microprocessor based systems.
'he above three buses that interface the C! to the system components are combinedly
&nown as the System bus.
Pin coniguration
'he pin diagram of 1,1< microprocessor is shown in Fig (. (rom the figure it is clear that it is
+, pin 2I chip. 'he various pins of 1,1< microprocessor can be grouped in the following
categories
ower Supply and Cloc& pins
2ata bus and Address bus
Control and Status signals
Interrupt signals
2MA signals
Serial I$% signals
T%" d"$cri!tion o #ariou$ !in$ i$ gi#"n ."lo>.
Po>"r $u!!l/ and clock !in$-
<cc- A<E power supply
<$$- Cround reference.
?
1
and ?
+
- A Crystal "or 3C, >C -etwor&# is connected at these two pins. 'he internal
cloc& generator divides oscillator fre@uency by 7, therefore to operate a system at ;M8B,
the crystal of the tuned circuit should have a fre@uency of 0M8B.
15
C,@ )OUT*- 'his signal is used as a system cloc& for other devices. Its fre@uency is half
the oscillator fre@uency
Data .u$ and Addr"$$ .u$-
AD
'
1AD
:
- 'hese lines are Address$2ata lines, which are bidirectional with dual purpose.
'hey are used as the low*order address bus as well as the data bus. 2uring the first part
of the machine cycle "'
.
#, lower 1 bits of memory address or I$% address appear on the
bus. 2uring the remaining part of the machine cycle "'
7
,'
;
# these lines are used as a bi*
directional data bus
. Figur" (. Pin Diagram o &'&( A
A
&
1A
'
- 'hese are the upper half of the .0 bit address lines. 'hese lines are e)clusively
used for the most significant 1 bits of the .0 bits of the.0 bit address bus.
Control and Statu$ Signal$-
A,E )Addr"$$ ,atc% Ena.l"*- 'his is a positive going pulse generated every time the
1,1< begins an operation. 'he A>4M8igh indicates that the bits on A2
=
*A2
,
are address
bits. 'his signal is mainly used to latch the low order address from the multiple)ed bus
and generate a separate set of eight address lines "A=*A
,
#
"3ead#J 'his is an active low read control pin. 'his signal indicates that the selected
I$% or memory device is to be read and data are available on data bus.
16
"?rite#J 'his is an active low write control pin. It indicates that the data on the data
on the data bus are to be are to be written into a selected memory or I$% location
IO9 - 'his is a status signal used to differentiate between I% and memory operations.
?hen it is high, it indicates an I$% operation and when it is low, it indicates a memory
operation. 'his signal is combined with and signals to generate I$% and memory
control signals.
S
1
and S
'
- 'hese are status signals and they indicate the type of machine cycle in
progress during e)ecution of an instruction.
READ5 )In!ut*- 'hrough this pin, the microprocessor will &now whether peripheral device
is ready or not for data transfer. If the device is not ready the processor waits. So, this pin
helps to synchroni9e slow devices to the microprocessor.
Int"rru!t $ignal$-
'3A, 3S' =.<, 3S' 0.<, 3S'<.< and I-'3J 'hese are the interrupt signals which are e)ternally
initiated.
INTR )Int"rru!t R"Au"$t*- 'his is used as a general purpose interrupt. It has a lowest
priority and it is the only non*vectored interrupt.
RST :.(- It is a restart interrupt pin. It has higher priority than 3S' 0.<, 3S'<.< and I-'3.
It is a mas&able vectored interrupt.
RST ;.( and RST(.(- 'hese two are mas&able vectored interrupt with higher priority than
I-'3.
TRAP- It is a non*mas&able vectored interrupt. It has higher priority.
)Out!ut*- It is an active low interrupt ac&nowledge pin. 'his will ac&nowledge the
receival of interrupt re@uest to the peripheral device.
DMA Signal$-
Bold- 'his pin is used during the 2irect Memory Access. A high on this pin indicates that,
a peripheral li&e 2MA controller is re@uesting the use of address and data buses.
B,DA )Out!ut*- A high on this p in ac&nowledges the hold re@uest from peripheral.
- It is an active low signal. ?hen the signal on this pin goes low, the system is in
reset i.e. the program counter is set to 9ero, the address Q data buses are tristated.
RESETOUT- 'his signal is used to 3eset other devices in microprocessor system.
S"rial in!ut9 Out!ut $ignal$-
SID- Serial input 2ata is a pin through which serial data are brought into the micro
processor accumulator after the 3IM instruction is e)ecuted.
17
SOD- Serial output 2ata pin is used by the microprocessor to output data serially to the
e)ternal devices. Serial data is sent out of the microprocessor by e)ecuting SIM
instruction. 'he most significant bit of accumulator should have the serial bit and 2
0
bit of
the accumulator must be made high to enable the serial data transfer.
Timing Diagram -
'he graphical representation of the time ta&en for the e)ecution of each instruction by a
microprocessor is &nown as timing diagram. 'he e)ecution time is denoted by '*states. %ne '*
state is e@ual to the time period of the internal cloc& signal of the microprocessor
(or 4)J If the internal cloc& fre@uency of 1,1< microprocessor is ; M8B, %ne '*state is e@ual to
M M,.;;;).,
*0
secM;;;).,
*/
sec. ";;; nano seconds nearly#
As far as e)ecution of instructions is concerned, in 1,1< microprocessor, each instruction is
divided into two partsJ 'he operation code "opcode# and the operand. 'he opcode tells us
what
the operation is and the operand is the necessary information re@uired for the instruction. 'he
operand may be either data or an address or other information re@uired for the instruction.
4ach instruction is divided into machine cycles and each machine cycle is divided into cloc&
cycles or '* states
'he first machine cycle is every instruction is the op*code fetch. 2uring this time the
opcode is fetched from memory and returned on the data bus to the microprocessor. 'he
1,1< machine cycles are divided into following si) types. 'hey are
.. %pcode fetch
7. Memory read
;. Memory write
+. I$% read
<. I$% write
0. Interrupt ac&nowledge
O!cod" "tc% Mac%in" c/cl"-
'he first operation in every instruction is the opcode fetch. 'he opcode fetch cycle is
called the M
.
machine cycle and is usually for four '*states or cloc& cycles "certain instructions
may also have 0' states in their opcode fetch machine cycle#. 2uring '
.
*'
;
states the address is
placed on the address bus and the opcode is returned on the data bus. 'he '
+
*state is used to
decode and e)ecute the opcode. 'he ne)t machine cycles "M
7
, M;******# that follow depend upon
what the instruction actually is.
'he timing diagram for e)ecution of MEI A, 7< machine cycle is shown in Fig ; as shown in the
timing diagram, in '
.
state, the 1,1< places the contents of the program counter o n the
address bus. 'he high order byte of the .C "1,# is placed on the A
1*
A
.<
lines. 'he low*
order byte of the .C",,# is placed on the A2
,*
A2
=
line which stays only on only during '
.
.
So, the microprocessor activates the A>4 "Address >atch 4nable# pin which is used to
latch the low*order byte of the address in e)ternal latch before it vanishes. 2uring '
.
state,
1,1< also sends status signals I%$ , S
.
and S
,
. 'he I%$ signal specifies whether the
operation is read or write. In opcode fetch machine cycle status signals are I%$ M,, S
.
M.
and S
,
M,
In '
7
state, the lower order address disappears from A2
,*
A2
=
lines and 1,1< sends signal
low to enable the addressed memory location. 'he memory device then places the
contents of the addressed memory location on the data bus "A2
,*
A2
=
#
18
2uring '
;
state, the microprocessor loads the data from the data bus in its instruction register
and raises to high which disables the memory device
In '
+
state, the microprocessor decodes the opcode and based on the instruction it decides
whether to '
,
state '
<
or to enter state '
.
of the ne)t machine cycle "M
7
#. All the one byte
instructions which operate on 1*bit data li&e M%E A, 6, A226, 2C3C, 3A> etcO..are
e)ecuted '
+
state. %ne byte instructions which operate on .0*bit data are e)ecuted in '
<
and '
0
states.
(or e)ampleJ I-D8, S8>, <2CD8 etc.

Figur" ; Timing diagram or O!cod" "tc% Mac%in" c/cl"
M"mor/ R"ad c/cl"-
Memory read machine cycle is a machine cycle during which memory is read. (or
e)ample, the instruction >2A 1/,,8 which is a ;*byte instruction has three memory read cycles
immediately after the opcode fetch cycle. 'he first two cycles are to get the memory address, in
two 1*bit groups "the low*order part of the address and then the high*order address#. 'he third
read cycle is needed to read the data located at the address previously retrieved. 'his data is
then loaded into accumulator.
19
'he timing diagram for memory read cycle R(or 4)J >2A 7,7,8S is shown in Fig :. As shown in
the memory read timing diagram, after the opcode fetch cycle, the first two read cycles
have the address going out over the address bus first for the low*order of the address
"7,,.8# and then for the high*order of the address"7,,78#. In the third read cycle, the
address of the instruction Gust read from memory "7,7,8# is sent bac& over the address
bus in '
.
and then data from that memory location is returned over the data bus in '
7
*'
;
.
I%$ goes low at the beginning of the opcode fetch cycle and remains low during the ne)t
three cycles. , on the other hand goes low each time data on the data bus is to be read
into the microprocessor.
Figur" :. Timing diagram or M"mor/ R"ad mac%in" c/cl"
M"mor/ Crit" c/cl"-
'his memory write cycle is used when the microprocessor needs to send data out from
accumulator or specific register and then write into the memory. As an e)ample let us consider
the instruction M%E M, A "<,8#. 'his instruction re@uires two machine cycles*an opcode fetch
machine cycle followed by one write cycle. 6ecause, after fetching the opcode, the instruction
has to write the data in the accumulator out to memory at the address location in the 8*> register.
'his operation re@uires =*' states for opcode fetch and three F' states for the memory write.
20


Figur" & .Timing diagram or M"mor/ Crit" mac%in" c/cl"
'he timing diagram of the instruction M%E A, M is shown in (ig .1. 'he opcode fetch cycle shows
the address R7,,,8S going out over the address bus and the opcode for the M%E M,A
"<,8# returning over the data bus. 2uring the write cycle "M
7
#, the address that was stored
in the 8*> pair goes out from the microprocessor during '
.
and data to be written from the
accumulator goes out during '
7
*'
;
. 'he remaining signals li&e A>4, I%$ , and
have their usual meaning as shown in the timing diagram.
I9O R"ad c/cl"-
'his I$% read cycle occurs when the microprocessor e)ecutes I- instruction and during
the I$% read cycle, data is read in from an I$% device. In the case of I- %3', there are three
machine cycles. 'he opcode fetch cycle, a memory read cycle and an I$% read cycle. 'he three
machine cycles combinedly ta&en .,*states.
'he (ig /. shows the timing diagram of the instruction I- 1,8, 8ere 1,8 is the port address of
the device being read.
'he opcode fetch cycle shows the address of the instruction "7,,,8# going out over t he address
bus and the opcode "268# for the I- instruction returning on the data bus. 'he memory
read cycle "M
7
# displays the address of the second byte of the instruction "1,,.8# going
out over the address bus and the port address "1,8# returning on the data bus. 2uring the
I$% read cycle, the port address of the device being read is sent over the address bus and
the lower 1*bits carry the same 1*bit port address and the data from the input device is
returned on the data bus during '7*';.
21

Figur" D. Timing diagram or I9O R"ad mac%in" c/cl"
I9O >rit" c/cl"-
2uring this I$% write cycle 2A'A is written into I$% device specified by the port address
from the accumulator. 'he out port instruction has three machine cycles. 'he first one is opcode
fetch cycle, second one is memory read to get the port address and the third cycle is an I$% write
cycle. 'he %!' command writes the data stored in the accumulator over the data bus to the
device whose port address was sent out over the address bus. 'he three machine cycle that
forms the outport command has a total of ten '*states. 'he (ig ., Shows the timing diagram for
%!' ,+8 instruction. ,+8 is the address of the output device
'he opcode fetch cycle sends the address of the instruction "7,,,8# over the address bus while
the opcode "2;8# for the %!' instruction is returns on the data bus. 'he second machine
cycle shows the address of the second byte of the instruction "7,,.8# going out over the
address bus with the port address "1+8# returning over the data bus.
(rom the timing diagram it is clear that, In the third machine cycle the port address "1+8# is sent
out over both the upper and lower parts of the address bus, similar to I$% read cycle
whenever the microprocessor addresses an I$% device, the port address of the device
being read is sent out over both the lower and higher order parts of the address bus.
It is also to be noted that the data in the accumulator is being written to the output device and
goes out over the data bus during '
7
*'
;
states after the port address has been sent over
the two parts of the address bus during '
.
of the I$% write cycle
22
Figur" 1' Timing diagram or I9O Crit" mac%in" c/cl"
Int"rru!t Ackno>l"dg"
'his Interrupt ac&nowledge machine cycle is a special machine cycle that is used in place
of opcode fetch cycle in the 3S' "restart# instruction. It is same as an opcode fetch e)cept
that it ,sends out an signal instead of an signal and the status lines I%$ , S
,
and
S
.
are ... instead ,... Another difference is, the interrupt ac&nowledge is si)*' states
whereas opcode fetch is only four '*states
In$truction c/cl"= Mac%in" c/cl"= "tc% and "4"cut" c/cl"$
In$truction c/cl"
An instruction is a command given to the microprocessor to perform a specific operation
on the given data. Se@uence of instructions written for a processor to perform a particular tas& is
called a program. rogram Q data are stored in the memory. 'he microprocessor fetches one
instruction from the memory at a time Q e)ecutes it. It e)ecutes all the instructions of the program
one by one to produce the final result. 'he necessary steps that a microprocessor carries out to
fetch an instruction Q necessary data from the memory Q to e)ecute it constitute an instruction
cycle.
In other words, an instruction cycle is defined as the time re@uired completing the e)ecution of an
instruction.
An instruction cycle consists of a fetch cycle and an e)ecute cycle. 'he time re@uired to fetch an
opcode "fetch cycle# is a fi)ed slot of time while the time re@uired to e)ecute an instruction
"e)ecute cycle# is variable which depends on the type of instruction to be e)ecuted.
23
Instruction cycle"IC# M (etch cycle"(C# A 4)ecute cycle"4C#
'his is shown diagrammatically in the Fig.0.11

Figur" 11 In$truction c/cl"
Mac%in" c/cl"J
Machine cycle is defined as the time re@uired for completing the operation of accessing
either memory or I$% device. In the 1,1<, the machine cycle may consist of three to si) ' states.
'he '*state is defined as one sub*division of the operation performed in one cloc& period. 'hese
sub*divisions are internal states synchroni9ed with the system cloc&.In every machine cycle the
first operation is op*code fetch and the remaining will be read or write from memory or I%
devices.
F"tc% o!"ration-
'he first byte of an instruction is its op*code. An instruction may be more than one byte
long. 'he other bytes are data or operand address. 'he program counter "C# &eeps the
memory address of the ne)t instruction to be e)ecuted. In the beginning of a fetch cycle the
content of the program counter, which is the address of the memory location where op*code is
available, is sent to the memory. 'he memory places the op*code on the data bus so as to
transfer it to the microprocessor. 'he entire operation of fetching an op*code ta&es three cloc&
cycles.
E4"cut" o!"ration-
'he op*code fetched from the memory goes to the instruction register "I3#. (rom the
instruction register it goes to the decoder circuitry which decodes the instruction. After the
instruction is decoded, e)ecution begins. If the operand is in general purpose registers e)ecution
is immediately performed.
'he time ta&en for decoding and e)ecution is one cloc& cycle. If an instruction contains data or
operand and address which are still in the memory, the microprocessor has to perform
some read operations to get the desired data. After receiving the data it performs e)ecute
operation. A read cycle is similar to a fetch cycle. In case of a read cycle the @uantity
received from the memory are data or operand address instead of an op*code. In some
instructions write operation is performed. In write cycle data are sent from the
microprocessor to the memory or an output device. 'hus we see that in some cases an
e)ecute cycle may involve one or more read or write cycles or both.
In$truction $"t o &'&(
An Instruction is a command given to the microprocessor to perform a given tas&
on specified data. 4ach instruction has two parts one is the tas& to be performed called
the operation code "op*code# and the second is the data to be operated on, &nown as
operand. 'he operand or data can be specified in various ways.
24
In$truction and data ormat$-
'he format of a typical instruction is composed of two partsJ an operation code or op*code
and an operand. 4very instruction needs an op*code to specify what the operation of the
instruction is and then an operand that gives the appropriate data needed for that particular
operation code.
According to the word or byte si9e the 1,1< instructions are classified into three types.
'hey are
"a# %ne byte "single# instructions.
"b#'wo byte instructions.
"c# 'hree byte instructions.
On"3./t" in$truction$- An instruction with only opcode and do not re@uire any dat or address is
called a one byte instruction.
E4- .. M%E C, A 8e) code M +(8 "one byte#
7. A22 6 8e) code M 1,8 "one byte#
;. CMA 8e) code M 7(8 "one byte#
T>o3./t" in$truction$- At wo byte instruction is one which contains an 1*bit op*code and 1*bit
operand "2ata#.
E4- .. MEI A, ,/ 8e) code M ;4, ,/ "two bytes#
7. A22 6, ,= 8e) code M 1,, ,= "two bytes#
;. S!6 A, ,< 8e) code M /=, ,< "two bytes#
T%r""3./t" in$truction$- A three byte instruction contains an opcode plus a .0 F bit address.
E4- ..>DI 8, 1<,/ 8e) code M 7., ,/, 1< "'hree bytes#
7 .>2A 1<,/ 8e) code M ;A, ,/, 1< "'hree bytes#
;. 5M /<0= 8e) code M C;, 0=, /< "'hree bytes#
+. S'A ;<7< 8e) code M ;7, ;<, 7< "'hree bytes#
DATA FORMATS- 'he 1,1< is an 1*bit microprocessor which process only binary numbers. 6ut
it is very difficult to understand these binary numbers by a common user. So, we have to
code these binary numbers into different data formats. 'he commonly &nown data formats
are ASCII, 6C2, signed integers and unsigned integers. 'he ASCII code is a =*bit alpha*
numeric code that represents decimal numbers, 4nglish alphabets and certain special
characters. 'he ASCII stands for TAmerican Standard code for Information InterchangeT
'he term 6C2 stands for binary coded decimal, used for decimal numbers from ,*/.An 1*
bit register can store two 6C2 numbers. A signed integer is either a positive or a negative
number. In 1,1< microprocessor the most significant bit 7
D
is used for the sign. 8ere ,
denotes
positive sign and . denotes the negative sign. An integer without a sign can be represented by all
the 1*bits in a microprocessor register. So, the largest number that can be processed at
one time
is ((8. 'he numbers larger than 1*bits li&e .0, 7+, ;7 bits can be processed by dividing them in
groups of 1*bits.
C,ASSIFICATION OF INSTRUCTIONS
25
An instruction is a binary pattern designed inside a microprocessor to perform a specific
function. 'he entire group of instructions, called the instruction set, determines what functions the
microprocessor can perform. 'he 1,1< microprocessor instruction set has =+ operation codes
that result in 7+0 instructions. 'his instruction set includes all the 1,1,A instructions plus two
additional instructions namely SIM and 3IM.
'he instruction set of 1,1< microprocessor is classified into five groups. 'hey areJ
.. 2ata transfer "copy# group.
7. Arithmetic group
;. >ogic group
+. 6ranch control group
<. Machine control and I$% group.
Data tran$"r )co!/* in$truction$
'he data transfer instructions are used to transfer data from one register to another
register, from memory to register or register to memory but not from one memory location
to another memory location. Actually this data transfer instruction copies the data from
source to destination and the contents of the source are not altered. So, the data transfer
instruction performs basically copy operation.
4)amples of data transfer instructions are M%E, MEI "Move Immediate#, >DI ">oad Immediate 8*
> air#, >2A ">oad Accumulator#, S'A "Store Accumulator#, >8>2 ">oad 8*> pair direct#,
S8>2 "Store 8*> pair direct#, DC8C "4)change the contents of 8*> pair with 2*4 pair#
etcO
E4- MEI A, <<8 N Move the data <<8 into Accumulator
M%E 6, C N Copies the contents of C register into 6 register
I- ,,8 N 3ead the Input port",,8 is the port address#
%!' ,.8 N write data to an output port",.8 is the port address#
>DI8 1<=,8 N >oad 8*> pair by address 1<=,8.
In the 1,1< microprocessor, data transfer instructions do not affect any flags.
Arit%m"tic In$truction$
'he arithmetic operations li&e addition, subtraction, increment and decrement are
performed by the 1,1< microprocessor using the following arithmetic instructions.
A22, A2I "Add Immediate#, S!6 "Subtract#, S!I "Subtract Immediate#, I-3 "Increment#, 2C3
"2ecrement# etcO
'he arithmetic operations Add and subtract are performed in relation to the
contents of the accumulator. 6ut, the increment or the decrement operations can be
performed in any register.
E4-A22 6, C N Add the contents of 6 register to the 6 register contents
A2I ,1 N Add the data ,1 to the accumulator.
S!6 A, 6 N Subtract the contents of 6 register from accumulator.
S!I ,< NSubtract immediate the 1*bit data from accumulator
I-3 6 N Increment the 6 register contents by one bit
2C3 C N 2ecrement the C register contents by one bit.
Arithmetic instructions modify all the flags according to the data conditions of the result. 'he I-3
and 2C3 instructions affect all flags e)cept the carry flag.
,ogical 8rou! o In$truction$-
26
Since the microprocessor is a programmable logic chip, it can be perform all the logic
functions of the hard*wired logic through its instruction set. 'he 1,1< processor can perform the
logic instructions li&e, A-2, %3, -%' "Complement# and D*%3 "4)clusive %3# etcO 'he
mnemonics of these instructions are given below.

A-A J >ogically A-2 the contents of a register
A-I J >ogically A-2 immediate the 1*bit data.
%3A J >ogically %3 the contents of a register.
%3 J >ogically %3 immediate the 1*bit data.
D3A J 4)clusive*%3 the contents of a register.
D3I J Immediate 4)clusive*%3 the 1*bit data
CMA J Complement the accumulator
All the logic operations are performed in relation to the contents of the accumulator. 'he CMA
instruction does not affect any flags. 'he e)ecutions of the logical instruction do not affect
the contents of the operand register.
Branc% In$truction$
'hese instructions are very important because they allow the microprocessor to change
the se@uence of a program either conditionally or unconditionally. 'he conditional branch
instructions transfer the program to the specified label when certain condition is satisfied. 'he
unconditional branch instructions transfer the program to the specified location unconditionally.
?e &now that the microprocessor is a se@uential machine. So, it e)ecutes machine codes from
one memory location to the ne)t. 6ranch instructions instruct the microprocessor to go to
a different memory location and the processor continues e)ecuting machine codes from
the new location. 'he address of the new locations either specified e)plicitly or provided
by the microprocessor or some times by additional hardware. 'he 6ranch instructions are
classified into three categories. 'hey are
"a#. 5ump instructions
"b#. Call and return instructions
"c#. 3estart instructions.
5ump instructions specify memory locations e)plicitly and they are ;*byte instructions. 'hese
5ump instructions are of two types. 'hey are , !nconditional 5ump and Conditional 5ump.
Unconditional Eum!-
'his is similar to !nconditional Co to statement in 6ASIC. ?hen this instruction is
e)ecuted the .0*bit address available immediately in the instruction is loaded into the program
counter , so that the ne)t se@uence of instruction e)ecution starts from this location. 'his
!nconditional 5ump instruction enables the programmer to create continuous loops.
5M ".0 bit address#. So, this is a ;*byte instruction where the first byte is op*
code and the second, third bytes specify memory address.
(or e)ample, the instruction 5M 1<,,8, instructs the microprocessor to go to the memory
location1<,,8 unconditionally. Sometimes, the Gump location is specified using a label
also.
Conditional Eum!-
27
'his instruction allows the microprocessor to ma&e decision depending on certain
conditions indicated by flags. 'he 1,1< processor 5ump instruction is associated with four flags.
-amely Carry flag "CL#, Bero flag "B#, Sign flag "S# and arity flag "#. 'he following instructions
shown in 'able ;.; transfer the program se@uence to the memory location specified under the
given conditions.
S. No In$truction D"$cri!tion
. 5C ".0 bit Addr# 5ump on carry "if CLM.#
7 5-C ".0 bit Addr# 5ump on no carry "if CLM,#
; 5B ".0 bit Addr# 5ump on Bero "if BM.#
+ 5-B ".0 bit Addr# 5ump on no Bero "if BM,#
< 5 ".0 bit Addr# 5ump on plus "if 2
=
M,N SM,#
0 5M ".0 bit Addr# 5ump on minus "if 2
=
M.N SM.#
= 54 ".0 bit Addr# 5ump on 4ven arity "if M.#
1 5% ".0 bit Addr# 5ump on %dd arity "if M,#
Ta.l" 0 #ariou$ conditional Fum! in$truction$
'o understand the instructions, let us consider the instruction 5C ".0 bit address#. 'he meaning
of this instruction is, the microprocessor is instructed to Gump the specified .0 bit memory
location if there e)ists a carry after the arithmetic operation else it will e)ecute the ne)t
instruction in the se@uence.
CA,, and RETURN In$truction$
'he microprocessor uses the two instructions CA>> and 34'!3- to implement
subroutines. 8ere CA>> instruction calls a subroutine program which is not a part of the
main program and the 34' instruction at the end of the subroutine program to return the
control to the main program.
E4- CA>> ".0 bit memory address#
34'
RESET )RST* In$truction
'he 1,1< processor provides eight 3S' instructions to transfer the program control to a specific
location on page ,,8. 'hese instructions are .*byte instructions. 'he various 3S'
instructions and their call locations are given in the following 'able ;.+
S. No Mn"monic$ B"4 cod" Call location
In B"4
. 3S' , C= ,,,,
7 3S'. C( ,,,1
; 3S'7 2= ,,.,
+ 3S'; 2( ,,.1
< 3S'+ 4= ,,7,
0 3S'< 4( ,,71
= 3S'0 (= ,,;,
1 3S'= (( ,,;1
28
Ta.l" 7 <ariou$ RST in$truction$ and t%"ir call locations
29
Mac%in" control and I9O In$truction$
'here are si) basic machine control instructions. 'hey are
4I "4nable Interrupt#
2I "2isable Interrupt#
-% "-o %peration#
SIM "Set Interrupt Mas&#
3IM "3ead Interrupt Mas&#
8>' "8alt#
EI )Ena.l" Int"rru!t*- 'his is a one byte instruction used to enable the interrupt. 'his instruction
is used to enable the interrupts when the microprocessor is reset or the interrupt enable
flag is reset after interrupt ac&nowledge. 'his instruction ta&es one machine cycle with
four states. 'he op*code is (68.
DI )Di$a.l" Int"rru!t*- 'his is a one byte instruction which resets the interrupt enable flag to
disable all the interrupts e)cept '3A. It ta&es one machine cycle with four states. 'he op*
code is (;8.
NOP )No O!"ration*- when this instruction is e)ecuted, the microprocessor performs nothing.
Microprocessor spends four states doing nothing. It is a one byte instruction whose op*
code is ,,8.'his instruction is normally used to generate very small time delays of the
order of few micro seconds. 'his -% instruction is also very useful when we are re@uired
to insert a few instructions in the main program additionally .
SIM )S"t Int"rru!t Ma$k*- 'his instruction mas&s the interrupt as desired. 'his is a dual purpose
instruction. 'he first purpose is to set or reset the mas& of the mas&able interrupt. 'he
second purpose is to send the data out through the S%2 pin at pin number + of the
microprocessor.
RIM )R"ad Int"rru!t Ma$k*- 'his instruction copies the status of the interrupts into the
accumulator. It is also used to read the serial data through the SI2 pin
B,T )Balt*- After e)ecution of this instruction the microprocessor goes into the halt state. 'he
processor can be restarted by a valid interrupt or by applying a 34S4' signal. 'he
microprocessor ta&es <' states to implement the halt instruction.
I9O in$truction$J
'here are two important instructions to input the data into the microprocessors accumulator
through the input port and output the data from the accumulator to the output port. 'hey
are
I- "port address#
%!' "port address#
'his port address is an 1*bit address. In both these instructions the default register is
Accumulator.
E4- "i# I- ,.8. 'his instruction will copy the contents into the Accumulator through the port
whose address is ,.8. It ta&es three machine cycles and ta&es ., states. 'he op*code is
268.
30
"ii#%!' ,78. 'his instruction sends the contents of Accumulator to the outport whose
address is ,78. It is a two byte instruction which re@uires ., states. 'he op*code for this
instruction is 2;8.
DETAI,ED INSTRUCTION SET

DATA TRANSFER INSTRUCTIONS
31
32
ARITBMATIC INSTRUCTIONS
33
34
35

36
37
38
39
40

41

42

SOD F Serial output 2ata .6it 2
=
of accumulator is latched in to the S%2 output line made
available to serial peripheral if bit 2
0
M. .
SOE F Serial output enable.If this bit M. ,it enables the serial output.
??? F 2ont care condition
R:.( F 3eset 3S'=.<.If this bit M . ,3S'=.< flip*flop is reset .'his is an additional control to reset
3S'=.<
MSE F Mas& set 4nable.If this bit is high ,it enables the function of bits 2
7
,2
.
and 2
,
.'his is a
master control over all the interrupt mas&ing bits.
M:.( F 2
7
M, ,3S' =.< is enabled
2
7
M. 3S'=.< is mas&ed or disabled
M;.( F 2
.
M, 3S'0.< is enabled
2
.
M. 3S' 0.< mas&ed or disabled.
M(.( F 2
,
M, 3S'<.< is enabled
2
,
M. 3S' <.< is disabled or mas&ed.

ADDRESSIN8 MODES
MaGority of the instructions of 1,1< microprocessor re@uires an operand "either data or
address# on which the intended operation can be performed. Some instructions may re@uire only
one operand and some other instructions re@uire two operands for its instruction e)ecution. 'he
speed of e)ecution mainly depends on the position of the operand in the instruction. 'he scheme
involved in identifying the position of operands in an instruction is &nown as addressing mode.
'here are five addressing modes 1,1< processor.'hey are
"i#. Immediate addressing mode
"ii#. 2irect addressing mode
"iii#. 3egister addressing mode.
"iv#. 3egister indirect addressing mode.
"v#. Implicit addressing mode.
)i*. Imm"diat" Addr"$$ing mod"- 'he mode of addressing in which the operand is a part of the
instruction itself is &nown as Immediate Addressing mode. If the immediate data is 1*bit,
the instruction will be of two bytes. If the immediate data is .0 bit, the instruction is of ;
bytes.
E4- ".#. A2I 2A'A N Add immediate the data to the contents of the accumulator.
"7#.>DI8 1<,,8 J >oad immediate the 8*> pair with the operand 1<,,8
";#. MEI ,18 N Move the data ,1 8 immediately to the accumulator
"+#. S!I ,<8 N Subtract immediately the data ,<8 from the accumulator
)ii* Dir"ct Addr"$$ing mod"- 'he mode of addressing in which the .0*bit address of the
operand is directly available in the instruction itself is called 2irect Addressing mode. i.e.,
the address of the operand "data# is available in the instruction itself. 'his is a ;*byte
instruction.
E4- ".#. >2A /<7<8 N >oad the contents of memory location into Accumulator.
"7#. S'A 1,,,8 N Store the contents of the Accumulator in the location 1,,,8
";#. I- ,.8 N 3ead the data from port whose address is ,.8.
)iii*. R"gi$t"r addr"$$ing mod"$- 'he mode, in which the operand is in one of the general
purpose registers, is &nown as the register addressing mode.
E4- ".#. M%E A, 6N Move the contents of 6 register to A register.
"7#. S!6 2N Subtract the contents of 2 register from Accumulator.
";#. A22 6, CN Add the contents of C register to the contents of 6 register.
43
)i#*. R"gi$t"r indir"ct addr"$$ing mod"$- 'he .0*bit address location of the operand stored in
a register pair "8*># is given in the instruction. 'he address of the operand is given in an
indirect way with the help of a register pair. 8ence it is called 3egister indirect addressing
mode
E4- ".#. >DI8 /<=,8 N >oad immediate the 8*> pair with the address of the location /<=,8
M%E A, M N Move the contents of the memory location pointed by the 8*> pair to
accumulator
)#*. Im!licit Addr"$$ing mod"- 'he mode of instruction which do not specify the operand in the
instruction but it is implicated, is &nown as implicit addressing mode. i.e., the operand is
automatically considered to be in the Accumulator.
E4- ".#.CMAN complement the contents of Accumulator
"7#.CMCN Complement carry
";#. 3>CN 3otate Accumulator left by one bit
"+#. 33CN 3otate Accumulator right by one bit
"<#. S'CN Set carry.
ASSEMB,5 ,AN8UA8E PRO8RAMMIN8 E?AMP,ES-
Addition Program$
E4am!l" 1- Addition of two 1*bit numbers whose sum is 1*bits.
E4!lanation- 'his assembly language program adds two 1*bit numbers stored in two memory
locations .'he sum of the two numbers is 1*bits only.'he necessary algorithm and flow
charts are given below.
A,8ORITBM-
Step.. J Initiali9e 8*> pair with memory address DD,, "sayJ /,,,#.
Step7. J Clear accumulator.
Step;. J Add contents of memory location M to accumulator.
Step+. J Increment memory pointer "i.e. DD,.#.
Step<. J Add the contents of memory indicated by memory pointer to accumulator.
Step0. J Store the contents of accumulator in /,,7.
Step=. J 8alt
PRO8RAM-
44
Addr"$$
o
t%"
m"
mo
r/
loc
ati
on
B"4 ,a."l Mn"monic$ Comm"nt$
O!1 O!"rand
1,,, 7.,, >DI 8, /,,, Initialise memory pointer to point
the first data location /,,,.
1,,; ;4 MEI A, ,, Clear accumulator
1,,+ ,,
1,,< 10 A22 A, M 'he first number is added to
accumulator RAS RAS A M
1,,0 7; I-D 8 Increment the memory pointer to
ne)t location of the 2ata.
1,,= 10 A22 A, M 'he 7
nd
number is added to
contents of accumulator
1,,1 ;7 S'A /,,7 'he contents of accumulator are
stored in memory location
/,,7.
1,,/ ,7
1,,A /,
1,,6 =0 8>' Stop the e)ecution
45
E4- In!ut- E4- )i* /,,, F 7/ 8 E4 -)ii* /,,, F+/ 8
/,,. F .0 8 /,,. F;7 8
R"$ult- E4- "i# /,,7 F ;( 8 E4 -) ii* /,,7 F =6
Flo> C%art
Fig 0.1&
E4am!l" +- Addition of two 1*bit numbers whose sum is .0 bits.
E4!lanation- 'he first 1*bit number is stored in one memory location "say 1<,,# and the second
1*bit number is stored in the ne)t location "1<,.#.Add these two numbers and chec& for
carry. Store the >S6 of the sum in one memory location "1<,7# and the MS6 "carry# in the
other location"1<,;#.
A,8ORITBM-
Step.. J Initiali9e 8*> pair with memory address D "sayJ 1<,,#.
Step7. J Clear accumulator.
Step;. J Add contents of memory location M to accumulator.
Step+. J Increment memory pointer "i.e. 1<,.#.
Step<. J Add the contents of memory indicated by memory pointer to accumulator.
46
Start
Initialise H-L Pair
with XX00
Clear Accumulator
(00) A
Add contents of M to
Accumulator
U Increment memory pointer"DD,.#
U Add contents of M to A
Stop
Copy the contents of Reg
A to memory location
XX0!
Step0. J Chec& for Carry
Step = J Store the sum in 1<,7.
Step1 J Store the Carry in 1<,; location
Step / J 8alt
Flo> C%art


Les
-o



Fig 0.1D
47
Initialise 8*> air with DD,,
Clear Accumulator
",,# A
Add contents of M
to Accumulator
U Increment memory
pointer"DD,.# Q
U Add contents of M to A
Stop
Store the sum in the location
)),7
Start
Is

Carry


e"ists
#
$tore carry in the
XX0% location
$tore &ero in the
XX0% location
PRO8RAM-
Addr"$$
o
t%"
m"
mor
/
loca
tion
B"4 ,a. Mn"monic$ Comm"nt$
O!1
c
o
d
"
O!"rand
1,,, 7.,,, >DI 8, 1<,, 8 Initialise memory pointer to point
the first data location /,,,.
1,,; ;4 MEI A,,, Clear accumulator
1,,+ ,,
1,,< 10 A22 A, M 'he first number is added to
accumulator RAS RASAM
1,,0 ,4 MEI C,,, Initial value of Carry is ,
1,,= ,,
1,,1 7; I-D 8 Increment the memory pointer to
ne)t location of the 2ata.
1,,/ 10 A22 A, M 'he 7
nd
number is added to
contents of accumulator
1,,A ;7 5-C (?2 Is Carry e)ists V -o,go to the label
(?2
1,,6 ,4
1,,C 1,
1,,2 ,C I-3 C Ma&e carry M.
1,,4 ;7 (? S'A 1<,7 8 'he sum is stored in memory
location 1<,7.
1,,( ,7
1,., 1<
1,.. =/ M%E A,C
1,.7 ;7 S'A 1<,; 8 Store the carry at 1<,; location
1,.; ,;
1,.+ 1<
1,.< =0 8>' Stop the e)ecution
48
E4- In!ut- E4 - 1<,, F /= 8 RESU,T- 1<,7 F ;7 8
1<,. F /18 1<,; ** ,. 8
E4am!l" 0- 2ecimal addition of two 1*bit numbers whose sum is .0 bits.
E4!lanation- 2ecimal addition of two 1*bit numbers is same as that of two 1*bit numbers
program. 4)cept that the use of 2AA instruction. 'he first 1*bit number is stored in one
memory location "say 1<,,# and the second 1*bit number is stored in the ne)t
location"1<,.#.Add these two numbers and use the 2AA instruction to get the result in
decimal. Also chec& for carry. Store the >S6 of the sum in one memory location"1<,7# and
the MS6 "carry# in the other location"1<,;#.
A,8ORITBM-
Step.. J Initiali9e 8*> pair with memory address DDDD "sayJ 1<,,#.
Step7. J Clear Carry register C.
Step;. J Move contents of memory location M to accumulator.
Step+. J Increment memory pointer "i.e. 1<,.#.
Step<. J Add the contents of memory indicated by memory pointer to accumulator.
Step0. J Apply the instruction 2AA"2ecimal adGust after addition#
Step=J Chec& for Carry
Step1J Store the sum in DD,7.
Step/J Store the Carry in DD,; location
Step.,J 8alt
Flo> C%art

49
Initialise 8*> air
with DD,,
Clear Carry register
",,# C
Add contents of M
to Accumulator
U Increment memory
pointer"DD,.# Q
U Add contents of M to A
Start
Apply 2AA instruction to
convert 8e) data to decimal
form


Les



-o

Fig .+'
PRO8RAM
Addr"$$ o
t%"
m"m
or/
locat
ion
B"4 ,a."l Mn"monic$ Comm"nt$
O!1
c
o
d
"
O!"rand
1,,, 7., >DI 8, 1<,,
8
Initialise memory pointer to point
the first data location /,,,.
1,,; ,4 MEI C, ,, Clear accumulator
1,,+ ,,
1,,< =4 M%E A, M 'he first number is added to
accumulator RAS RASAM
1,,0 7; I-D 8 Increment the memory pointer to
ne)t location of the 2ata.
1,,= 10 A22 A, M 'he 7
nd
number is added to
contents of accumulator
1,,1 7= 2AA
1,,/ 27 5-C (?2 Is Carry e)istsV -o, go to the label
(?2
,2
1,
1,,C ,C I-3 C Ma&e carry M.
1,,2 ;7 (?2 S'A 1<,7 8 'he contents of accumulator are
stored in memory location
1<,7.
1,,4 ,7
1,,( 1<
1,., =/ M%E A, C Carry is moved to accumulator
1,.. ;7 S'A 1<,; 8 A Carry is stored in the location
1<,;
1,.7 ,;
1,.; 1<
1,.+ =0 8>' Stop the e)ecution
50
Stop
Store the sum in the
location DD,7
Is

Carry


4)istsV
$tores carry in
the XX0% location
$tore &ero in the
XX0% location
E4- In!ut- E4 - 1<,, F 0= 2 RESU,T- 1<,7 F <7 2
1<,. F 1< 2 1<,; F ,. "Carry#
E4am!l" 7- Addition of two .0*bit numbers whose sum is .0 bits or more
E4!lanation- (irst .0*bit number is stored in two consecutive locations "4) 1<,, Q1<,.#
because in each location we can store only one 1*bit number. Store the second .0*bit
number in the ne)t two consecutive locations "(or 4)J 1<,7 Q1<,;#.Add the >S6 of the
first number to the >S6 of the second number and the MS6 of the first number to the MS6
of the second number using the 2A2 instruction. Store the sum in the ne)t two locations
and the carry "if any# in the third location
A,8ORITBM-
Step.J (irst .0 bit number is in locations 1<,, Q 1<,. respectively
Step7J Second .0*bit number is in locations 1<,7 Q 1<,;
Step;J Add the two .0*bit numbers using 2A2 Instruction.
Step+J Sum is stored in locations 1<,+ Q 1<,<.
Step<J Carry "if any# is stored in the location 1<,0.
Step0J 8alt
Flo> C%art
51
Start
Initialise H-L Pair
with '(00
>oad the first .0*bit
number in to 8*> air
)"change this
num*er in to +-)
pair
Load the second ,--*it
num*er in to H-L pair
Add the L$. of Ist num*er
to the L$. of the second
num*er / M$. of the
second num*er to M$. of
the second num*er using
+A+ instruction
Les
-o



Fig +1
PRO8RAM-
ADDRESS BE? 3
C
O
D
E
,ABE, MNEMONIC COMMENTS
OPCO
D
E
OPERAND
1,,, 7A,,,,1< >8>2 1<,, 8 (irst .0*bit number in 8*> pair
1,,. ,,
1,,7 1<
1,,; 46 DC8C 4)change first number to 2*4
air
1,,+ 7A >8>2 1<,7 8
1,,< ,7
1,,0 1<
1,,= ,4 MEI ,, MS6 of the sum is initially ,,
1,,1 ,,
1,,/ ./ 2A2 2 Add two .0 Fbit numbers
1,,A 27 5-C (?2 Is CarryV If yes go to the ne)t line
.4lse go to the 1,,4
>%CA'I%-
1,,6 ,4
1,,C 1,
1,,2 %C I-3 C Increment carry
1,,4 77 (?2 S8>2 1<,+ 8 Store the >S6 of the Sum in 1<,+
Q MS6 in 1<,< locations 1,,( ,+
1,., 1<
1,.. =/ M%E A,C MS6s of the sum is in
Accumulator
1,.7 ;7 S'A 1<,0 8 Store the MS6 "Carry# of the
result in 1<,0 location 1,.; ,0
1,.+ 1<
1,.< =0 8>' Stop e)ecution
52
Stop
Is


Carr
y

$et#
$tore 001 in the location
'(0-
$tore1,1 in the
'(0- location
$tore the L$.s of the sum
in '(02 / '(0( locations

E4- INPUT- 1<,,* .7 8 >S6 of the I
st
-umber RESU,T - 1<,+ * 7<8 >S6 of the Sum
1<,.* .; 8 MS6 of the I
st
-umber 1<,< F 7<8 MS6 of the Sum
1<,7 *.; 8 >S6 of the II
nd
-umber 1<,0 ** ,, Carry .
1<,; *.78 MS6 of the II
nd
number
Su.traction Program$-
E4am!l" (- Subtraction of two 1*bit numbers without borrows.
E4!lanation- Its a simple program similar to addition of two 1* bit numbers, e)cept that we use the
instruction S!6 instead of A22. 'he first 1*bit number is stored in DD,, memory location and the
second 1*bit number is stored in the DD,. location .!se the S!6 instruction and store the result in
the DD,7 location.
A,8ORITBM-
Step.. J Initialise 8*> pair with the address of minuend.
Step7. J Move the minuend into accumulator
Step;. J Increment 8*> pair
Step+. J Subtract the subtrahend in memory location M from the minuend.
Step<. J Store the result in DD,7.
Step0. J Stop the e)ecution
Flo> C%art
53
Start
Initialise H-L Pair with
XX00
Mo3e the contents of
M to Accumulator
Increment memory
pointer4XX0,5
Subtract the subtrahend n
memor! locaton " #rom
the mnuend n A
Stop
Store the result n the
locaton $$02

Figur" ++
PRO8RAM-
ADDRESS BE?
C
O
D
E
,ABE, MNEMONIC COMMENTS
OPCOD
E
OPERAN
D
1,,, 7. >DI 8, 1<,, Initialise 8*> pair and get the
(irst number in to 1<,,
location
1,,. ,,
1,,7 1<
1,,; =4 M%E A,M RAS RMS
1,,+ 7; I-D 8 RMA.S RMS
1,,< /0 S!6 M A RAS F RMS
1,,0 7; I-D 8 -e)t memory location
1,,= == M%E M,A Store the result in the location
1<,7
1,,1 =0 8>' Stop the e)ecution
54
INPUT- E4 - 1<,,* </8 R"$ult- 1<,7 F 7/8
1<,.* ;,8
E4am!l" ;- Subtraction of two 1*bit 2ecimal numbers.
E4!lanation- In this program we cant use the 2AA instruction after S!6 or S66 instruction because it is
decimal adGust after addition only. So, for decimal subtraction the number which is to be subtracted
is converted to .,s complement and then 2AA is applied.
A,8ORITBM-
Step.. J Initialise 8*> pair with the address of second number "DD,.#.
Step7. J (ind its tens complement
Step;. J 2ecrement the 8*> pair for the first number "DD,,#
Step+. J Add the first number to the .,s complement of second number.
Step<. J Store the result in DD,7.
Step0. J Stop the e)ecution
Flo> C%art
Figur" +0
55
Start
Initialise H-L Pair with
XX0, and get the second
num*er
(ind its .,s
complement
Add 6rst num*er to the ,07s
complement of the second
num*er
Apply the 2AA instruction to get
decimal result
Stop
Store the result in the
location DD,7
PRO8RAM-
ADDRESS BE?
C
O
D
E
,AB MNEMONIC COMMENTS
OPCODE OPERAND
1,,, 7. >DI 8,1<,, Initialise 8*> pair and get
theSecond number in to
1<,. location
1,,. ,,
1,,7 1<
1,,; ;4 MEI A,// RAS //
1,,+ //
1,,< /0 S!6 M /s complement of second
number
1,,0 ;C I-3 A .,s complement of second
number
1,,= 76 2CD 8 Address of the first number
1,,1 10 A22 M Add first number to .,s
complement of second
number
1,,/ 7= 2AA
1,,A ;7 S'A 1<,7 Store the result in the location
1<,7
1,,6 ,7
1,,C 1<
1,,2 =0 8>' Stop the e)ecution
56
E4- In!ut- 1<,, *=0 2 R"$ultJ 1<,7 * +. 2
1<,.* ;< 2

E4am!l" ;- Subtraction of two .0 Fbit numbers.
E4!lanation- It is very similar to the addition of two .0*bit numers.8ere we use S!6 QS66
instructions to get the result .'he first .0*bit number is stored in two consecutive locations
and the second .0*bit number is stored in the ne)t two consecutive locations.'he lsbs are
subtracted using S!6 instruction and the MS6s aare subtracted using S66
instruction.'he result is stored in different locations.
A,8ORITBM-
Step.. J Store the first number in the locations 1<,, Q 1<,..
Step7. J Store the second number in the locations 1<,7 Q1<,;.
Step+. J Subtract the second number from the first number with borrow.
Step<. J Store the result in locations 1<,+ Q 1<,<.
Step0. J Store the borrow in location 1<,0
Step =J Stop the e)ecution
Flo> C%art
57
Initiali8e H-L Pair
with XX00
>oad the first .0*bit number in
to 8*> air A
)"change this
num*er in to +-)
pair
Load the second ,--*it
num*er in to H-L pair
Start
Les
-o
-o
58
$u*tract L$. of ! nd
num*er from the L$. of the
Ist num*er / M$. of the !
nd num*er from M$. of the
6rst num*er
Is
borrow

Set V
$tore 001 in the location
XX0-
$tore 1,1 in the
XX0- location
$tore the result in XX02 /
XX0( locations
Fig +7

PROGRAM:
E4- INPUT - 1<,,* (( 8 >S6 of the I
st
-umber RESU,T- 1<,+ * ..8 >S6
1<,. * (( 8 MS6 of the I
st
-umber 1<,< F .. 8 MS6
1<,7 *44 8 >S6 of the II
nd
-umber
1<,; F44 8 MS6 of the II
nd
number
Multi!lication Program$
E4am!l" :- Multiplication of two 1*bit numbers. roduct is .0*bits.
E4!lanation- 'he multiplication of two binary numbers is done by successive addition. ?hen
multiplicand is multiplied by . the product is e@ual to the multiplicand, but when it is
multiplied by 9ero, the product is 9ero. So, each bit of the multiplier is ta&en one by one
and chec&ed whether it is . or , .If the bit of the multiplier is . the multiplicand is added to
the product and the product is shifted to left by one bit. If the bit of the multiplier is , , the
product is simply shifted left by one bit. 'his process is done for all the 1*bits of the
multiplier.
ADDRESS BE? ,ABE MNEMONIC COMMENTS
OPCOD
E
OPERAN
D
1,,, 7A, >8>2 1<,, 8 (irst .0*bit number in 8*> pair
1,,; 46 DC8C 4)change first number to 2*4 air
1,,+ 7A >8>2 1<,7 8 Cet the second .0*bit number in 8*>
pair
1,,< ,7
1,,0 1<
1,,= =6 M%E A, 4 Cet the lower byte of the (irst number
in to Accumulator
1,,1 /< S!6 > Subtract the lower byte of the second
number
1,,/ 0( M%E >, A Store the result in >* register
1,,A M%E A, 2 Cet higher byte of the first number
1,,A /C S66 8 Subtract higher byte of second number
with borrow
1,,6 0= M%E 8, A
1,,C 77 S8>2 1<,+ Store the result in memory locations
with >S6 in 1<,+ Q MS6 in
1<,<
1,,2 ,+
1,%4 1<
1,%( =0 8>' Stop e)ecution
59
Stop
A,8ORITBM-
Step . J Initialise 8*> pair with the address of multiplicand."say 1<,,#
Step 7 J 4)change the 8*> pair by 2*4 pair. so that multiplicand is in 2*4 pair.
Step ; J >oad the multiplier in Accumulator.
Step + J Shift the multiplier left by one bit.
Step < J If there is carry add multiplicand to product.
Step 0 J 2ecrement the count.
Step = J If count ,N Co to step +
Step 1 J Store the product i.e. result in memory location.
Step / J Stop the e)ecution

Flow Chart
60
Start
%oad the multpler n to Accumulator &
multplcand n '() par
Initial 3alue of
product900
Count*08
-o
Les


-o

Les




Figur" +(
PRO8RAM-
61
Sh#t product le#t b! one bt &Sh#t
multpler le#t b! one bt
+roduct * +roduct , "ultplcand
Count 9 count -,
Is carry
e"ists
from
multiplie
r #
$tore result
Stop
Is
count
9 0 #
ADDRESS BE? ,ABE MNEMONIC COMMENTS
%C%2
4
%43A-2
1,,, 7A,, >8>2 8, 1<,, >oad the multiplicand in to 8*> pair
1,,; 46 DC8C 4)change the multiplicand in to 2*4 pair
1,,+ ;A >2A 1<,7 Multiplier in Accumulator
1,,< ,7
1,,0 1<
1,,= 7. >DI 8.,,,, Initial value in 8*> pair is ,,
1,,1 ,,
1,,/ ,,
1,,A ,4 MEI C,,1 Count M,1
1,,6 ,1
1,,C 7/ >%% 2A2 8 Shift the partial product left by one bit.
1,,2 .= 3A> 3otate multiplier left by one bit
1,,4 27 5-C (?2 Is Multiplier bit M.V -o go to label (?2
1,,( .7
1,., 1,
1,.. ./ 2A2 2 roduct Mroduct AMultiplicand
1,.7 ,2 (?2 2C3 C C%!-'MC%!-'*.
1,.; C7 5-B >%%
1,.+ ,C
1,.< 1,
1,.0 77 S8>2 1<,; Store the result in the locations 1<,; Q
1<,+
1,.= ,;
1,.1 1<
1,./ =0 8>' Stop the e)ecution
INPUT -
Address 2ata
1<,, 1A8 F >S6 of Multiplicand
1<,. ,, 8 F MS6 of Multiplicand
1<,7 <7 8 * Multiplier
R"$ult- 1<,; ;+ 8 F >S6 of roduct
1<,+ 7C 8 F MS6 of roduct
62

Di#i$ion Program$
E4am!l" :- Di#i$ion o a 1;1 .it num."r ./ a &1.it num."r.
E4!lanation- 'he division of a .0$1*bit number by a 1*bit number follows the successive
subtraction method. 'he divisor is subtracted from the MS6s of the dividend .If a borrow
occurs, the bit of the @uotient is set to . else ,.(or correct subtraction process the
dividend is shifted left by one bit before each subtraction. 'he dividend and @uotient are in
a pair of register 8*>.'he vacancy arised due to shifting is occupied by the @uotient .In the
present e)ample the dividend is a .0*bit number and the divisor is a 1*bit number. 'he
dividend is in locations 1<,, Q1<,..Similarly the divisor is in the location 1<,7.'he
@uotient is stored at 1<,; and the remainder is stored at 1<,+ locations.
A,8ORTBM-
S'4.. J Initialise 8*> pair with address of dividend.
S'47. J Cet the divisor from 1<,7 to register A Q then to 3eg.6
S'4;. J Ma&e count CM,1
S'4+. J Shift dividend and divisor left by one bit
S'4 <J Subtract divisor from dividend.
S'40. J If carry M . J goto step 1 else step=.
S'4=. J Increment @uotient register.
S'41. J 2ecrement count in C
S'4/. J If count not e@ual to 9ero go to step +
S'4.,J Store the @uotient in 1<,;
S'4..J Store the remainder in 1<,+
S'4.7J Stop e)ecution.
63
Flo>c%art

-o
Les



-o Les



Fig.+;
64
S-A.-
Initialise 8*> pair with address of
dividend
Copy the divisor in to 3eg. A
U Shift dividend left by one bit
U Shift Iuotient left by one
1 MS6s of dividend M
1 MS6s of dividend *divisor
Is
Coun
t M,V
:uotient 9 :uotient ;,
Count M Count*.
store th @uotient in 1<,;
Qremainder in 1<,+
Move the divisor in to 3eg. 6
Move count M,1 in to C register
/s "S0s
o#
'1dend
2 '1sor
3
Stop
PRO8RAM-
Ex: Input & Result
ADD BE? 3
C
O
D
E
,ABE, MNEMONIC COMMENTS
OPCOD
E
OPERAN
D
1,,, 7. >8>2 8, 1<,, Initiali9e the 8*> pair for
dividend 1,,. ,,
1,,7 1<
1,,; ;A >2A 1<,7 8 >oad the divisor from location
1<,7 to accumulator 1,,+ ,7
1,,< 1<
1,,0 += M%E 6,A Move 2ivisor to 3eg.6 from
A
1,,= ,4 MEI C,,1 Count M,1
1,,1 ,1
1,,/ 7/ 6AC: 2A2 8 Shift dividend and @uotient
left by one bit
1,,A =C M%E A,8 MS6 of dividend in to
accumulator
1,,6 /, S!6 6 Subtract divisor from MS6
bits of divisor
1,,C 2A 5C (?2 Is MS6 part of dividend W
divisor V -o,goto label
(?2
1,,2 ..
1,,4 1,
1,,( 0= M%E 8,A MS6 of the dividend in
3eg.8
1,., 7C I-3 > Increment @uotient
1,.. ,2 (?2 2C3 C 2ecrement count
1,.7 C7 5-B 6AC: If count is not 9ero Gump
to1,,/ location 1,.; ,/
1,.+ 1,
1,.< 77 S8>2 1<,;8 Store @uotient in 1<,; and
remainder in 1<,+
locations
1,.0 ,;
1,.= 1<
1,.1 =0 8>' Stop e)ecution
Address 2ata
1<,, 0+ >S6 of 2ividend
1<,. ,, MS6 of 2ividend
1<,7 ,= 2ivisor
1<,; ,4 Iuotient
1<,+ ,7 3emainder
65
,arg"$t G Small"$t num."r$ in an Arra/
E4am!l" &- 'o find the largest number in a data array
E4!lanation- 'o find the largest number in a data array of - numbers "say#first the count is
placed in memory location "1<,,8# and the data are stored in consecutive locations.
"1<,.O.onwards#.'he first number is copied to Accumulator and it is compared with the
second number in the memory location. 'he larger of the two is stored in Accumulator.
-ow the third number in the memory location is again compared with the accumulator.
And the largest number is &ept in the accumulator. !sing the count, this process is
completed , until all the numbers are compared .(inally the accumulator stores the
smallest number and this number is stored in the memory location.1<DD.
A,8ORTBM-
Step.J Store the count in the Memory location pointed by 8*> register.
Step7J Move the I st number of the data array in to accumulator
Step;J Compare this with the second number in Memory location.
Step+J 'he larger in the two is placed in Accumulator
Step<J 'he number in Accumulator is compared with the ne)t number in memory .
Step 0J 'he larger number is stored in Accumulator.
Step =N 'he process is repeated until the count is 9ero.
Step 1J (inal result is stored in memory location.
Step /J Stop the e)ecution
66
Flo> C%art
Les

-o

-o

-o
Les





Fig +:
67
S-A.-
Initialise H-L pair
<et the count in Register C
Cet >arger number in
Accumulator
/s
=um*er in
Accumulator
> =e"t
num*er #
<et 6rst num*er in
Accumulator
2ecrement Count
store the result in the
location 1<DD
S-4+
/s count *
0
3
PRO8RAM
A22 84D F
C
%
2
4
>A64> M-4M%-IC C%MM4-'S
%C%2
4
%43A-
2
1,,, 7.,,,,1
<
>DI 8, 1<,, I-I'IA>IS4 8*> AI3
1,,; =4 M%E C,M Count in the C register
1,,+ 7; I-D 8 (irst number in 8*> pair
1,,< +4 M%E A,M Move first number in to
Accumulator
1,,0 ,2 2C3 C 2ecrement the count
1,,= /. >%%. I-D 8 Cet the ne)t number
1,,1 64 CM M Compare the ne)t number
with previous number
1,,/ 27 5-C >%%7 Is ne)t number Wprevious
ma)imumV-o,go to
the loop7
1,,A ,2
1,,6 1,
1,,C =4 M%E A,M If,yes move the large
number in to
Accumulator
1,,2 ,2 >%%7 2C3 C 2ecrement the count
1,,4 C7 5-B >%%. If count not e@ual to
9ero,repeat
1,,( ,=
1,.. 1,
1,.7 =1
1,.; ;7 S'A 1<DD Store the largest number in
the location 1<DD
1,.+ DD
1,.< 1<
1,.0 =0 8>' Stop the e)ecution
68
E4 - In!ut J 1<,,* -"Say -M= # R"$ult J 1<,1 * =(
1<,.*,<
1<,7*,A
1<,;*,1
1<,+*.+
1<,< *=(
1<,0*7<
1<,=*72
E4am!l" D - 'o find the smallest number in a data array.
E4!lanation- 'o find the smallest number in a data array of - numbers "say#first the count is
placed in memory location "1<,,8# and the data are stored in consecutive locations.
"1<,.O.onwards#.'he first number is copied to Accumulator and it is compared with the
second number in the memory location.'he smaller of the two is stored in
Accumulator.-ow the third number in the memory location is again compared with the
accumulator.and the smallest number is &ept in the accumulator.!sing the count,this
process is completed until all the numbers are compared .(inally the accumulator stores
the smallest number and this number is stored in the memory location.1<DD.
A,8ORTBM -
Step.J Store the count in the Memory location pointed by 8*> register.
Step7J Move the I st number of the data array in to accumulator
Step;J Compare this with the second number in Memory location.
Step+J 'he smaller in the two is placed in Accumulator
Step<J 'he number in Accumulator is compared with the ne)t number in memory .
Step 0J 'he smaller number is stored in Accumulator.
Step =N 'he process is repeated until the count is 9ero.
Step 1J (inal result is stored in memory location.
Step /J Stop the e)ecution
69
Flo> C%art
Les

-o

70
S-A.-
Initialise H-L pair
<et the count in Register C
Cet first number in to
Accumulator
Cet smaller number in
Accumulator
/s
=um*er in
Accumulator
? =e"t
num*er #

-o
Les


Fig.+&
71
2ecrement Count
store the result at 8555
S-4+
/s count *
0 3
PRO8RAM
ADD BE? 3
C
O
D
E
,ABE, MNEMONIC COMMENTS
OPCOD
E
OPERAN
D
1,,, 7. >DI 8, 1<,, Initialise the 8*> pair.
1,,. ,,
1,,7 1<
1,,; =4 M%E C,M Count in the C register
1,,+ 7; I-D 8 (irst number in 8*> pair
1,,< +4 M%E A,M Move first number in to
Accumulator
1,,0 ,2 2C3 C 2ecrement the count
1,,= /. >%%. I-D 8 Cet the ne)t number
1,,1 64 CM M Compare the ne)t number
with previous number
1,,/ 27 5C >%%7 Is ne)t number Xprevious
smallest VIf yes go to
the loop7
1,,A ,2
1,,6 1,
1,,C =4 M%E A,M -o,move the smaller
number in to
Accumulator
1,,2 ,2 >%%7 2C3 C 2ecrement the count
1,,4 C7 5-B >%%. If count not e@ual to
9ero,repeat
1,,( ,=
1,.. 1,
1,.7 =1
1,.; ;7 S'A 1<DD Store the smallest number in
the location 1<DD
1,.+ DD
1,.< 1<
1,.0 =0 8>' Stop the e)ecution
72
E4- In!ut - 1<,, * -""Say -M=# R"$ult - 1<,1 F ,+
1<,.*,/
1<,7*,A
1<,;*,1
1<,+*.+
1<,< *=(
1<,0*,+
1<,=*72
Stack and Su.routin"$
Stac& is a set of memory locations in the 3ead$?rite memory which is used for temporary
storage of binary information during the e)ecution of a program. It is implemented in the
>ast*in*first*out ">I(%# manner. i.e., the data written first can be accessed last, %ne can
put the data on the top of the stac& by a special operation &nown as !S8. 2ata can be
read or ta&en out from the top of the stac& by another special instruction &nown as %.
Stac& is implemented in two ways. In the first case, a set of registers is arranged in a
shift register organi9ation. %ne can !S8 or % data from the top register. 'he whole
bloc& of data moves up or down as a result of push and pop operations respectively. In the
second case, a bloc& of 3AM area is allocated to the stac&. A special purpose register
&nown as stac& pointer "S# points to the top of the stac&. ?henever the stac& is empty, it
points to the bottom address. If a !S8 operation is performed, the data are stored at the
location pointed to by S and it is
decremented by one. Similarly if the % operation is performed, the data are ta&en out of the
location pointed at by S and S is incremented by one. In this case the data do not move
but S is incremented or decremented as a result of push or pop operations respectively.
0.17.1 A!!lication o Stack- Stac& provides a powerful data structure which has applications in
many situations. 'he main advantage of the stac& is that,
?e can store data "!S8# in it with out destroying previously stored data. 'his is not true in the
case of other registers and memory locations.
stac& operations are also very fast
'he stac& may also be used for storing local variables of subroutine and for the transfer of
parameter addresses to a subroutine. 'his facilitates the implementation of re*entrant
subroutines which is a very important software property.
'he disadvantage is, as the stac& has no fi)ed address, it is difficult to debug and document a
program that uses stac&.
0.17.+ Stack o!"ration- %perations on stac& are performed using the two instructions namely
!S8 and %. 'he contents of the stac& are moved to certain memory locations after
!S8 instruction. Similarly, the
contents of the memory are
transferred bac& to registers by
% instruction.
(or e)ample let us consider a
Stac& whose stac& top is +<,0 8.
'his is stored in the .0*bit Stac&
pointer register as shown in
Fig.0.+D
73
Figur".+D T%" PUSB o!"ration o t%" Stack
>et us consider two registers "register pair# 6 Q C whose contents are 7< Q 07.
3eg. 6 3eg. C


After !S8 operation the status of the Stac& is as shown in Fig 0.0'
Figur" .0' At"r PUSB o!"ration t%" $tatu$ o t%" $tack
>et us now consider % operationJ 'he Fig$ 0.01 G 0.0+ e)plains before and after the %
operation in detail
7< 07
74
.
Figur" 0.01 T%" POP o!"ration o t%" Stack
Figur" 0+ At"r POP o!"ration t%" $tatu$ o t%" $tack
6efore the operation the data .< and .C are in the locations +<,7 Q +<,; and after the pop
operation the data is copied to 6*C pair and now the S register points to +<,+
location.'his is shown in (ig.;.;7
Programming E4am!l" FOR PUSB G POP
75
?rite a program to initiali9e the stac& pointer "S# and store the contents of the register pair 8*>
on stac& by using !S8 instruction. !se the contents of the register pair for delay counter
and at the end of the delay retrieve the contents of 8*> using %.
Memory
>ocation
>abel Mnemonics %perand Comments
1,,,
1,,;
1,,0
1,,=
.
.
.
.
1.,,A
>DI
>DI
!S8
24>AL
.
.
.
%
S, +<,0 8
8,7<0< 8
8
CA>>
.
.
.
8
Initiali9e
Stac&
pointer
ush the
conten
ts.
76
Su.routin": It is a set of instructions written separately from the main program to e)ecute a
function that occurs repeatedly in the main program.
(or e)ample, let us assume that a delay is needed three times in a program. ?riting delay
programs for three times in a main program is nothing but repetition. So, we can write a
subroutine program called delay and can be called any number of times we need
Similarly, in 1,1< microprocessor we do not find the instructions for multiplication and
division. (or this purpose we write separate programs. So, in any main program if these
operations are needed more than once, the entire program will become lengthy and
comple). So, we write subroutine programs M!> Q 2IE separately from main program and
use the instruction CA>> M!> "or# CA>> 2IE in the main program. 'his can be done any
number of times. At the end of every subroutine program there must be an instruction
called 34'. 'his will ta&e the control bac& to main program.
'he 1,1< microprocessor has two instructions to implement the subroutines. 'hey are CA>> and
34'. 'he CA>> instruction is used in the main program to call a subroutine and 34'
instruction is used at the end of the subroutine to return to the main program. ?hen a
subroutine is called, the contents of the program counter, which is the address of the
instruction following the CA>> instruction is stored on the stac& and the program e)ecution
is transferred to the subroutine address. ?hen the 34' instruction is e)ecuted at the end
of the subroutine, the memory address stored on the stac& is retrieved and the se@uence
of e)ecution is resumed in the main program.
Diagrammatic r"!r"$"ntation
>et us assume that the e)ecution of the main program started at 1,,, 8. It continues until a
CA>> subroutine instruction at 1,7, 8 is encountered. 'hen the program e)ecution
transfers to 1,=, 8. At the end of the subroutine 1,=6 8. 'he 34' instruction is present.
After e)ecuting this 34', it comes bac& to main program at 1,7. 8 as shown in the
following Fig. 0.07

Fig.00 Diagrammatic r"!r"$"ntation o $u.routin" !rogram "4"cution
77
'he same is e)plained using the assembly language program e)ample.
Program E4am!l"-
Su.routin" Program-
M"mor/
Addr"$$
Mn"monic$ O!"rand Comm"nt$
1,=,
Y
Y

Y
Y
1,=6

1,=C
1,=(
Instructions
34'
-e)t Subroutine
34'
6eginning of the Subroutine.
4nd of the program
Instructions of ne)t subroutine if
any
4nd of the subroutine.
M"mor/
Addr"$$
Mn"monic$ O!"rand Comm"nt$
1,,,
Y
Y
Y
1,7,
1,7.
1,77
1,7;
Y
Y
Y
1,7(
>DI
CA>>
-e)t instruction
Y
Y
Y
8>'
S, 1+,, 8
1,=, 8
Initiali9e the Stac& pointer at 1+,, 8
Call a subroutine program stored at
the location 1,=, 8. "It is a
three by Instruction#
'he address of the ne)t instruction
following CA>> instruction.
4nd of the main program
.
78
D"la/ !rogram$-
In many situations it may be desired to provide some delay between the e)ecution of two
instructions by a microprocessor. 'he delay can be produced by either hardware chip li&e
17<; or by writing a software program using registers of the processor. 8ere we will
discuss the software delay program. 'his delay program is not a part of the main program.
8ence it is called delay sub*routine program. (or small delays we can use only one
register. 6ut for longer delays one has to use two or three registers. 'he techni@ue
involved here is, a register is loaded with a number and then decremented by using the
instruction 2C3 until it becomes 9ero. 'he time of e)ecution of the microprocessor is
e@ual to the delay time produced.
(or e)ample, we have constructed a display system where the >42s receive the input from a
microprocessor. Since the microprocessor is a very fast device it sends the signal at very
high speeds there by our eye cannot recogni9e the display pattern. So, if you provide
some delay between two input signals, the display can be visuali9ed clearly. Similarly to
observe the rotations of a stepper motor, a delay is needed between every two e)citation
signals applied to the motor.
2elay Subroutine with one registerJ
Program
Addr"$$ ,a."l Mac%in"
cod"
Mn"monic$ O!"rand Comm"nt$
/,,, MEI A, (( Cet (( in register A
/,,7 >%% 2C3 A 2ecrement register A.
/,,; 5-B >%% 8as the content of
register 6
becomes 9eroV
-o, Gump to
>%%. Les,
proceed ahead.
/,,0 34' 3eturn to main program
Calculation o D"la/ tim" or t%" a.o#" !rogram-
In the above program register A is loaded by ((8 6"7<< decimal# and it is decremented in a loop until it
becomes 9ero. 'he delay produced by this program is as follows
?e should &now the number of times each instruction of the above program is being
e)ecuted. 'he number of states re@uired for the e)ecution of each instruction is as
followsJ

In$truction$ Stat"$
MEI A, ((8 =
"loop# 2C3 A +
5-B loop =$.,
34' .,
79

Total T Stat"$H0(&7
'he time re@uired for one '*state in I-'4> 1,1< microprocessor is nearly ;;,n.sec
2elay time isM ;<1+ ) ;;;n.sec
M ;.<1+ ) ,.;;; ) .,
*;
seconds
M ...17=7 ) .,
*;
seconds
M .. ./;+=7 milliseconds
D"la/ Su.routin" >it% t>o r"gi$t"r$
Program-
Addr"$$ ,a."l Mac%in"
Cod"
Mn"monic O!"rand Comm"nt$
1+,, MEI 6, .,8 Cet desired number in register 6
1+,7 >%%. MEI C, <08 Cet desired number in register
1+,+ >%%7 2C3 C 2ecrement C.
1+,< 5-B >%%7 Is RCS 9eroV -o, go to >%%7. Les,
proceed further
1+,1 2C3 6 2ecrement register 6
1+,/ 5-B >%%. Is R6S 9eroV -o, go to >%%.. Les,
proceed further
1+,C 34' 3eturn to main program.
D"la/ Su.routin" u$ing r"gi$t"r !air
Program-
80
Addr"$
$
,a."l Mac%in
"
Cod"
Mn"monic O!"rand Comm"nt$
1,,, >DI 2, (((( Cet (((( in register pair 2*4
>%% 2CD 2 2ecrement count
M%E A, 2 Move the contents of register 2 to
accumulator
%3A 4 Chec& if 2 and 4 are 9ero.
5-B >%% If 2*4 is not 9ero, Gump to >%%
34' 3eturn to main program
D"la/ Su.routin" u$ing t%r"" r"gi$t"r$
Program-
81
(rom the above discussion it is clear that with increase of '*states re@uired for a delay
subroutine ,the delay time also increases.
111111111111111114111111111111111111


Addr"$
$
,a."l Mac%in
"
Cod"
Mn"monic O!"rand Comm"nt$
1+,, MEI A, /18 Cet control word
1+,7 %!' ,; Initiali9e port foe >42 2isplay
1+,+ MEI 6, <,8
1+,0 MEI C, ((8
1+,1 MEI 2, ((8
1+,A 2C3 2 2elay Subroutine with three
registers
1+,6 5-B >%%;
1+,4 2C3 C
1+,( 5-B >%%7
1+.7 2C3 6
1+.; 5-B >%%.
1+.0 MEI A, ,.
1+.1 %!' ,. %utput for >42
1+./ 8>' Stop.
82



83
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