Ezf2812 Techref

eZdsp
TM
F2812
2003 DSP Development Systems
Reference
Technical
eZdsp
TM
F2812
Technical Reference
506265-0001 Rev. F
September 2003
SPECTRUM DIGITAL, INC.
12502 Exchange Dr., Suite 440 Stafford, TX. 77477
Tel: 281.494.4505 Fax: 281.494.5310
sales@spectrumdigital.com www.spectrumdigital.com
IMPORTANT NOTICE
Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any
product or service without notice. Customers are advised to obtain the latest version of relevant
information to verify data being relied on is current before placing orders.
Spectrum Digital, Inc. warrants performance of its products and related software to current
specifications in accordance with Spectrum Digitals standard warranty. Testing and other quality
control techniques are utilized to the extent deemed necessary to support this warranty.
Please be aware, products described herein are not intended for use in life-support appliances,
devices, or systems. Spectrum Digital does not warrant, nor is it liable for, the product described
herein to be used in other than a development environment.
Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein. Nor does Spectrum
Digital warrant or represent any license, either express or implied, is granted under any patent right,
copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any
combination, machine, or process in which such Digital Signal Processing development products or
services might be or are used.
WARNING
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can
radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable
protection against radio frequency interference. Operation of this equipment in other environments
may cause interference with radio communications, in which case the user, at his own expense, will
be required to take any measures necessary to correct this interference.
TRADEMARKS
eZdsp is a trademark of Spectrum Digital, Inc.
Copyright 2003 Spectrum Digital, Inc.
Contents
1 Introduction to the eZdsp
TM
F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Provides a description of the eZdsp
TM
F2812, key features, and board outline.
1.0 Overview of the eZdsp
TM
F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1 Key Features of the eZdsp
TM
F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 Functional Overview of the eZdsp
TM
F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
2 Operation of the eZdsp
TM
F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Describes the operation of the eZdsp
TM
F2812. Information is provided on the DSKs various
interfaces.
2.0 The eZdsp
TM
F2812 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1 The eZdsp
TM
F2812 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.1 Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2 eZdsp
TM
F2812 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3 eZdsp
TM
F2812 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.3.1 P1, JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3.2 P2, Expansion Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.3.3 P3, Parallel Port/JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.4 P4,P8,P7, I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.5 P5,P9, Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.3.6 P6, Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.7 Connector Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.4 eZdsp
TM
F2812 Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.4.1 JP1, XMP/MCn Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.4.2 JP4, JP5, Voltage Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.4.2.1 JP4, +3.3/5 Volts for P8, P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.4.2.2 JP5, +3.3/5 Volts for P4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.4.3 JP7,JP8,JP11,JP12, Boot Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.4.4 JP9, PLL Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.5 LEDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.6 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
A eZdsp
TM
F2812 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Contains the schematics for the socketed and unsocketed versions of the eZdsp
TM
F2812
B eZdsp
TM
F2812 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Contains the mechanical information about the socketed and unsocketed versions of the eZdsp
TM
F2812
List of Figures
Figure 1-1, Block Diagram eZdsp
TM
F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Figure 2-1, eZdsp
TM
F2812 PCB Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Figure 2-2, eZdsp
TM
F2812 Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Figure 2-3, eZdsp
TM
F2812 Connector Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Figure 2-4, Connector P1 Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Figure 2-5, Connector P2 Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Figure 2-6, Connector P4/P8/P7 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Figure 2-7, Connector P5/P9 Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Figure 2-8, Connector P6 Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Figure 2-9, eZdsp
TM
F2812 Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Figure 2-10, eZdsp
TM
F2812 Jumper Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Figure 2-11, eZdsp
TM
F2812 Voltage Jumper Positions(Bottom side) . . . . . . . . . . . . . . 2-16
List of Tables
Table 2-1, External Chip Select and Usages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Table 2-2, eZdsp
TM
F2812 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Table 2-3, P1, JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Table 2-4, P2, Expansion Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Table 2-5, P4/P8, I/O Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Table 2-6, P7, I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Table 2-7, P5/P9, Analog Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Table 2-8, Connector Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Table 2-9, eZdsp
TM
F2812 Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Table 2-10, JP1, XMP/MCn Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Table 2-11, JP4, +3.3/5 Volts for P8, P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Table 2-12, JP5, +3.3/ Volts for P4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Table 2-13, JP7,JP8, JP11, JP12, Boot Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Table 2-14, JP9, PLL Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Table 2-15, LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Table 2-16, Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
About This Manual
This document describes board level operations of the eZdsp
TM
F2812 based on the
Texas Instruments TMS320F2812 Digital Signal Processor.
The eZdsp
TM
F2812 is a stand-alone module permitting engineers and software
developers evaluation of certain characteristics of the TMS320F2812 DSP to
determine processor applicability to design requirements. Evaluators can create
software to execute onboard or expand the system in a variety of ways.
Notational Conventions
This document uses the following conventions.
The eZdsp
TM
F2812 will sometimes be referred to as the eZdsp.
eZdsp will include the socketed or unsocket version
Program listings, program examples, and interactive displays are shown in a special
italic typeface. Here is a sample program listing.
equations
!rd = !strobe&rw;
Information About Cautions
This book may contain cautions.
This is an example of a caution statement.
A caution statement describes a situation that could potentially damage your software,
hardware, or other equipment. The information in a caution is provided for your
protection. Please read each caution carefully.
Related Documents
Texas Instruments TMS320C28x DSP CPU and Instruction Set Reference Guide,
literature #SPRU430
Texas Instruments TMS320C28x Assembly Language Tools Users Guide,
literature #SPRU513
Texas Instruments TMS320C28x Optimizing C/C++ Compiler Users Guide,
literature #SPRU514
Texas Instruments Code Composer Studio Getting Started Guide,
literature #SPRU509
1-1
Chapter 1

Introduction to the eZdsp
TM
F2812
This chapter provides a description of the eZdsp
TM
for the TMS320F2812
Digital Signal Processor, key features, and block diagram of the circuit
board.
Topic Page
TM
F2812 1-2
TM
F2812 1-2
TM
F2812 1-3
Spectrum Digital, Inc
1-2 eZdsp
TM
F2812 Technical Reference
TM
F2812
The eZdsp
TM
F2812 is a stand-alone card--allowing evaluators to examine the
TMS320F2812 digital signal processor (DSP) to determine if it meets their application
requirements. Furthermore, the module is an excellent platform to develop and run
software for the TMS320F2812 processor.
The eZdsp
TM
F2812 is shipped with a TMS320F2812 DSP. The eZdsp
TM
F2812
allows full speed verification of F2812 code. Two expansion connectors are provided
for any necessary evaluation circuitry not provided on the as shipped configuration.
To simplify code development and shorten debugging time, a C2000 Tools Code
Composer driver is provided. In addition, an onboard JTAG connector provides
interface to emulators, operating with other debuggers to provide assembly language
and C high level language debug.
TM
F2812
The eZdsp
TM
F2812 has the following features:
TMS320F2812 Digital Signal Processor
150 MIPS operating speed
18K words on-chip RAM
128K words on-chip Flash memory
64K words off-chip SRAM memory
30 MHz. clock
2 Expansion Connectors (analog, I/O)
Onboard IEEE 1149.1 JTAG Controller
5-volt only operation with supplied AC adapter
TI F28xx Code Composer Studio tools driver
On board IEEE 1149.1 JTAG emulation connector
1-3
TM
F2812
Figure 1-1 shows a block diagram of the basic configuration for the eZdsp
TM
F2812.
The major interfaces of the eZdsp are the JTAG interface, and expansion interface.
TMS320F28xx
ANALOG TO
DIGITAL
CONVERTER
PARALLEL
Figure 1-1, BLOCK DIAGRAM eZdsp
TM
F2812
A
N
A
L
O
G
E
X
P
A
N
S
I
O
N
I
/
O
E
X
P
A
N
S
I
O
N
JTAG
PORT/JTAG
CONTROLLER
P
A
R
A
L
L
E
L
P
O
R
T
EXTERNAL
JTAG
30 Mhz.
XTAL1/OSCIN
64K x 16
SRAM
XZCS6AND7n
1-4 eZdsp
TM
2-1
Chapter 2
Operation of the eZdsp
TM
F2812
This chapter describes the operation of the eZdsp
TM
F2812, key
interfaces and includes a circuit board outline.
Topic Page
2.0 The eZdsp
TM
F2812 Operation 2-2
2.1 The eZdsp
TM
F2812 Board 2-2
2.1.1 Power Connector 2-3
2.2 eZdsp
TM
F2812 Memory 2-3
2.2.1 Memory Map 2-4
2.3 eZdsp
TM
F2812 Connectors 2-5
2.3.1 P1, JTAG Interface 2-6
2.3.2 P2, Expansion Interface 2-7
2.3.3 P3, Parallel Port/JTAG Interface 2-9
2.3.4 P4,P8,P7, I/O Interface 2-9
2.3.5 P5,P9, Analog Interface 2-11
2.3.6 P6, Power Connector 2-13
2.3.7 Connector Part Numbers 2-14
2.4 eZdsp
TM
F2812 Jumpers 2-14
2.4.1 JP1, XMP/MCn Select 2-15
2.4.2 JP4, JP5 Voltage Jumpers 2-16
2.4.2.1 JP4, +3.3/5 Volts for P8, P4 2-17
2.4.2.2 JP5, +3.3/5 Volts for P2 2-17
2.4.3 JP7,JP8,JP11,JP12, Boot Mode Select 2-18
2.4.4 JP9, PLL Disable 2-18
2.5 LEDs 2-19
2.6 Test Points 2-19
2-2 eZdsp
TM
2.0 The eZdsp
TM
F2812 Operation
This chapter describes the eZdsp
TM
F2812, key components, and operation.
Information on the eZdsps various interfaces is also included. The eZdsp
TM
F2812
consists of four major blocks of logic:
Analog Interface Connector
I/O Interface Connector
JTAG Interface
Parallel Port JTAG Controller Interface
2.1 The eZdsp
TM
F2812 Board
The eZdsp
TM
F2812 is a 5.25 x 3.0 inch, multi-layered printed circuit board, powered
by an external 5-Volt only power supply. Figure 2-1 shows the layout of both the
socketed and unsocketed version of the F2812 eZdsp.
Figure 2-1, eZdsp
TM
F2812 PCB Outline
2-3
2.1.1 Power Connector
The eZdsp
TM
F2812 is powered by a 5-Volt only power supply, included with the
unit. The unit requires 500mA. The power is supplied via connector P6. If expansion
boards are connected to the eZdsp, a higher amperage power supply may be
necessary. Section 2.3.6 provides more information on connector P6.
2.2 eZdsp
TM
F2812 Memory
The eZdsp includes the following on-chip memory:
128K x 16 Flash
2 blocks of 4K x 16 single access RAM (SARAM)
1 block of 8K x 16 SARAM
2 blocks of 1K x 16 SARAM
In addition 64K x 16 off-chip SRAM is provided. The processor on the eZdsp can be
configured for boot-loader mode or non-boot-loader mode.
The eZdsp can load ram for debug or FLASH ROM can be loaded and run. For larger
software projects it is suggested to do a initial debug with on eZdsp F2812 module
which supports a total RAM environment. With careful attention to the I/O mapping in
the software the application code can easily be ported to the F2812.
The table below shows the external chip select signal and its use.
Table 1: External Chip Select and Usage
Chip Select
Signal
Use
XZCS0AND1n Expansion header
XZCS2n Expansion Header
XZCS6AND7n External SRAM

2-4 eZdsp
TM
2.2.1 Memory Map
The figure below shows the memory map configuration on the eZdsp
TM
F2812.
Note: The on-chip flash memory has a security key which can prevent visibility when
enabled.
Figure 2-2, eZdsp
TM
F2812 Memory Space
2-5
2.3 eZdsp
TM
F2812 Connectors
The eZdsp
TM
F2812 has five connectors. Pin 1 of each connector is identified by a
square solder pad. The function of each connector is shown in the table below:
The diagram below shows the position of each connector
Table 2: eZdsp
TM
F2812 Connectors
Connector Function
P1 JTAG Interface
P2 Expansion
P3 Parallel Port/JTAG
Controller Interface
P4/P8/P7 I/O Interface
P5/P9 Analog Interface
P6 Power Connector
Figure 2-3, eZdsp
TM
F2812 Connector Positions
P1
P5/P9
P3
P2
P6
P4/P8/P7
2-6 eZdsp
TM
2.3.1 P1, JTAG Interface
The eZdsp
TM
F2812 is supplied with a 14-pin header interface, P1. This is the
standard interface used by JTAG emulators to interface to Texas Instruments DSPs.
The positions of the 14 pins on the P1 connector are shown in the diagram below as
viewed from the top of the eZdsp.
The definition of P1, which has the JTAG signals is shown below.
Table 3: P1, JTAG Interface Connector
Pin # Signal Pin # Signal
1 TMS 2 TRST-
3 TDI 4 GND
5 PD (+5V) 6 no pin
7 TDO 8 GND
9 TCK-RET 10 GND
11 TCK 12 GND
13 EMU0 14 EMU1
Fig 2-4, P1 Pin Locations
1
2
P1
JTAG

1
2
3
4
5 7
8
9
10
11
12
13
14
2-7
2.3.2 P2, Expansion Interface
The positions of the 60 pins on the P2 connector are shown in the diagram below as
viewed from the top of the eZdsp.
WARNING !
The TMS320F2812 supports +3.3V Input/Output levels
which are NOT +5V tolerant. Connecting the eZdsp to
a system with +5V Input/Output levels will damage the
TMS320F2812. If the eZdsp is connected to another
target then the eZdsp must be powered up first and
powered down last to prevent lactchup conditions.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

P2
Figure 2-5, Connector P2 Pin Locations
39
40
15
16
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
2-8 eZdsp
TM
The definition of P2, which has the I/O signal interface is shown below.
* Default is No Connect (NC). User can jumper to +3.3V or +5V on backside of eZdsp
with JP5.
Table 4: P2, Expansion Interface Connector
Pin # Signal Pin # Signal
1 +3.3V/+5V/NC * 2 +3.3/+5V/NC *
3 XD0 4 XD1
5 XD2 6 XD3
7 XD4 8 XD5
9 XD6 10 XD7
11 XD8 12 XD9
13 XD10 14 XD11
15 XD12 16 XD13
17 XD14 18 XD15
19 XA0 20 XA1
21 XA2 22 XA3
23 XA4 24 XA5
25 XA6 26 XA7
27 XA8 28 XA9
29 XA10 30 XA11
31 XA12 32 XA13
33 XA14 34 XA15
35 GND 36 GND
37 XZCS0AND1n 38 XZCS2n
39 XREADY 40 10K Pull-up
41 XRnW 42 10K Pull-up
43 XWE 44 XRDn
45 +3.3V 46 XNMI/INT13
47 XRSn/RSn 48 No connect
49 GND 50 GND
51 GND 52 GND
53 XA16 54 XA17
55 XA18 56 XHOLDn
57 XHOLDAn 58 No connect
59 No connect 60 No connect
2-9
2.3.3 P3, Parallel Port/JTAG Interface
The eZdsp
TM
F2812 uses a custom parallel port-JTAG interface device. This device
incorporates a standard parallel port interface that supports ECP, EPP, and
SPP8/bidirectional communications. The device has direct access to the integrated
JTAG interface. Drivers for C2000 Code Composer tools are shipped with the eZdsp
modules
2.3.4 P4/P8/P7, I/O Interface
The connectors P4, P8, and P7 present the I/O signals from the DSP. The layout of
these connectors are shown below.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 17 18 19 20

Figure 2-6, P4/P8/P7 Connectors
15 16 P4
P8
P7
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
2-10 eZdsp
TM
The pin definition of P4/P8 connectors are shown in the table below.
* Default is No Connect (NC). User can jumper to +3.3V or +5V on backside of eZdsp
with JP4.
Table 5: P4/P8, I/O Connectors
P4
Pin #
P4 Signal
P8
Pin #
P8 Signal
P8
Pin #
P8 Signal
1 +3.3V/+5V/NC * 1 +3.3V/+5V/NC * 2 +3.3V/+5V/NC *
2 XINT2/ADCSOC 3 SCITXDA 4 SCIRXDA
3 MCLKXA 5 XINT1n/XBIOn 6 CAP1/QEP1
4 MCLKRA 7 CAP2/QEP2 8 CAP3/QEPI1
5 MFSXA 9 PWM1 10 PWM2
6 MFSRA 11 PWM3 12 PWM4
7 MDXA 13 PWM5 14 PWM6
8 MDRA 15 T1PWM/T1CMP 16 T2PWM/T2CMP
9 No connect 17 TDIRA 18 TCLKINA
10 GND 19 GND 20 GND
11 CAP5/QEP4 21 No connect 22 XINT1N/XBIOn
12 CAP6/QEPI2 23 SPISIMOA 24 SPISOMIA
13 T3PWM/T3CMP 25 SPICLKA 26 SPISTEA
14 T4PWM/T4CMP 27 CANTXA 28 CANRXA
15 TDIRB 29 XCLKOUT 30 PWM7
16 TCLKINB 31 PWM8 32 PWM9
17 XF/XPLLDISn 33 PWM10 34 PWM11
18 SCITXDB 35 PWM12 36 CAP4/QEP3
19 SCIRXDB 37 T1CTRIP/PDPINTAn 38 T3CTRIP/PDPINTBn
20 GND 39 GND 40 GND

2-11
The pin definition of P7 connector is shown in the table below.
2.3.5 P5/P9, Analog Interface
The position of the 30 pins on the P5/P9 connectors are shown in the diagram below
as viewed from the top of the eZdsp.
Table 6: P7, I/O Connector
P7
Pin #
P7 Signal
1 C1TRIPn
2 C2TRIPn
3 C3TRIPn
4 T2CTRIPn/EVASOCn
5 C4TRIPn
6 C5TRIPn
7 C6TRIPn
8 T4CTRIPn/EVBSOCn
9 No connect
10 GND
P9
Figure 2-7, Connector P5/P9 Pin Locations
7 5 3 1
20 18 16 14 12 10 8 6 4 2
19 17 15 13 11 9
ANALOG
1 2 3 4 5 6 7 8 9 10
P5
2-12 eZdsp
TM
The definition of P5/P9 signals are shown in the table below.
* Connect VREFLO to AGND or VREFLO of target system for proper ADC operation.
Table 7: P5/P9, Analog Interface Connector
P5
Pin #
Signal
P9
Pin #
Signal
P9
Pin #
Signal
1 ADCINB0 1 GND 2 ADCINA0
4 ADCINB3 7 GND 8

ADCINA3
5 ADCINB4 9 GND 10

ADCINA4
9 ADCREFM 17 GND 18 VREFLO *
10 ADCREFP 19 GND 20 No connect
2-13
2.3.6 P6, Power Connector
Power (5 volts) is brought onto the eZdsp
TM
F2812 via the P6 connector. The
connector has an outside diameter of 5.5 mm. and an inside diameter of 2 mm. The
position of the P6 connector is shown below.
The diagram of P6, which has the input power is shown below.
Figure 2-8, Connector P6 Location
P
O
W
E
R
TP1
PC Board
P6
+5V
Ground
Front View
Figure 2-9, eZdsp
TM
F2812 Power Connector
2-14 eZdsp
TM
2.3.7 Connector Part Numbers
The table below shows the part numbers for connectors which can be used on the
eZdsp
TM
F2812. Part numbers from other manufacturers may also be used.
*SSW or SSQ Series can be used
2.4 eZdsp
TM
F2812 Jumpers
The eZdsp
TM
F2812 has 8 jumpers available to the user which determine how
features on the eZdsp
TM
F2812 are utilized. The table below lists the jumpers and their
function. The following sections describe the use of each jumper.
Table 8: eZdsp
TM
F2812 Suggested Connector Part Numbers
Connector Male Part Numbers Female Part Numbers
P1 SAMTEC TSW-1-10-07-G-T SAMTEC SSW-1-10-01-G-T
P2 SAMTEC TSW-1-20-07-G-T SAMTEC SSW-1-20-01-G-T
Table 9: eZdsp
TM
F2812 Jumpers
Jumper # Size Function
Position As
Shipped From
Factory
JP1 1 x 3 XMP/MCn 2-3
JP4 1 x 3 +3.3/5 Volts to P8,P4 Not connected
JP5 1 x 3 +3.3/5 Volts to P2 Not Connected
JP7 1 x 2 Boot Mode 3 2-3
JP9 1 x 3 PLL Disable 1-2
WARNING!
be installed in either the 1-2 or 2-3 position
Unless noted otherwise, all 1x3 jumpers must
2-15
The diagram below shows the positions of six jumpers on the component side of the
eZdsp
TM
F2812.
2.4.1 JP1, XMP/MCn Select
Jumper JP1 is used to select the XMP/MCn option. The 1-2 selection allows the DSP to
operate in the Microcontroller mode. The 2-3 selection allow the DSP to operate in the
Microprocessor mode. The positions are shown in the table below.
* as shipped from factory
Table 10: JP1, XMP/MCn Select
Position Function
1-2 Microprocessor mode
2-3 * Microcomputer mode
Figure 2-10, eZdsp
TM
F2812 Jumper Positions
JP1
DS2
JP12
JP7
TP2
DS1
JP8
JP11
JP9
TP1
2-16 eZdsp
TM
2.4.2 JP4, JP5 Voltage Jumpers
Jumpers JP4 and JP5 are an unpopulated jumpers on the bottom side of the board that
provide either +3.3 volts or +5 volts to pins on the expansion connectors. These
jumpers are shipped uninstalled to prevent accidental damage by connecting wires or
circuitry to the expansion connector. The user may connect these jumpers by installing
a jumper wire or zero ohm resistor. The position of these jumpers are shown in the
figure below.
Figure 2-11, eZdsp
TM
F2812 Voltage Jumper Positions (Bottom Side)
JP5
JP4
2-17
2.4.2.1 JP4, +3.3/5 Volts for P8, P4
Jumper JP4 allows the user to provide either +3.3 or +5 volts to pins 1 and 2 of
expansion connector P8, and pin 1 of P4. The settings for this jumper are shown in the
table below
* As shipped from factory
2.4.2.2 JP5, +3.3/5 Volts for P2
Jumper JP5 allows the user to provide either +3.3 or +5 volts to pins 1 and 2 of
expansion connector P2. The settings for this jumper are shown in the table below.
* As shipped from factory
Table 11: JP4, +3.3/5 Volts for P8, P4
Position Function Jumper Position
1-2
Connect +5 Volts
to P8, pins 1,2,
and P4 pin1
2-3
Connect +3.3
Volts to P8, pins
1,2, and P4 pin1
No connect *
Table 12: JP5, +3.3/5 Volts for P2
Position Function Jumper Position
1-2
Connect +5 Volts to P2, pins
1,2
2-3
Connect +3.3 Volts to P2,
pins 1,2
No connect *
3.3V 5V
JP4
JP4
3.3V
5V
JP4
3.3V 5V
3.3V 5V
JP5
JP5
3.3V
5V
JP5
3.3V 5V
2-18 eZdsp
TM
2.4.3 JP7, JP8, JP11, JP12, Boot Mode Select
Jumpers JP7, JP8, JP11, JP12 are used to determine what mode the DSP will use for
bootloading on power up. To set a signal high, place the jumper in the 1-2 position.
For a low signal, use the 2-3 position.The options are shown in the table below.
* factory default
2.4.4 JP9, PLL Disable
Jumper JP9 is used to enable/disable the use of the Phase Lock Loop (PLL) logic on
the DSP. The selection of the 1-2 position enables the use of the PLL. If the 2-3
position is used the PLL is disabled. This signal is latched at reset and may be used as
XF after reset. The positions are shown in the table below.
* as shipped from the factory
Table 13: JP7, JP8, JP11, JP12, Boot Mode Select
JP7, BOOT3
SCITXDA
JP8, BOOT2
MDXA
JP11, BOOT1
SPISTEA
JP12, BOOT0
SPICLKA
MODE
1 X X X FLASH
0 1 X X SPI
0 0 1 1 SCI
0 0 1 0 H0 *
0 0 0 1 OTP
0 0 0 0 PARALLEL
Table 14: JP9, PLL Disable
Position Function
1-2 * PLL Enabled
2-3 PLL disabled
2-19
2.5 LEDs
The eZdsp
TM
F2812 has two light-emitting diodes. DS1 indicates the presence of
+5 volts and is normally on when power is applied to the board. DS2 is under software
control and is tied to the XF pin on the DSP through a buffer. These are shown in the
table below.
2.6 Test Points
The eZdsp
TM
F2812 has two test points. The signals they are tied to are shown in the
table below.
Table 15: LEDs
LED # Color Controlling Signal
DS1 Green +5 Volts
DS2 Green XF bit (XF high = on)
Table 16: Test Points
Test Point Signal
TP1 Ground
TP2 Analog Ground
2-20 eZdsp
TM
A-1
Appendix A
eZdsp
TM
F2812
Schematics
The schematics for the eZdsp
TM
F2812 can be found on the CD-ROM that
accompanies this board. The schematics were drawn on ORCAD.
The schematics are correct for both the socketed and unsocketed version
of the eZdsp
TM
.
Design Notes:
1. The TMS320F2812 X1/CLKIN pin is +1.8 volt input. The clock input is
buffered with a SN74LVC1G14 whose supply is +1.8 volts. This provides
+3.3 volts to the +1.8 volt clock translation. Refer to sheet 4 of the
schematics.
WARNING !
The TMS320F2812 supports +3.3V Input/Output levels
which are NOT +5V tolerant. Connecting the eZdsp to
a system with +5V Input/Output levels will damage the
TMS320F2812. If the eZdsp is connected to another
target then the eZdsp must be powered up first and
powered down last to prevent lactchup conditions.
A-2 eZdsp
TM
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F
A-8 eZdsp
TM
B-1
Appendix B
eZdsp
TM
F2812
MechanicaI Information
This appendix contains the mechanical information about the socketed and
unsocketed versions of the eZdsp
TM
F2812
B-2 eZdsp
TM
T
h
i
s

d
r
a
w
i
n
g

i
s

n
o
t

t
o

s
c
a
l
e
B-3
T
h
i
s

d
r
a
w
i
n
g

i
s

n
o
t

t
o

s
c
a
l
e
B-4 eZdsp
TM
Printed in U.S.A., September 2003
506265-0001 Rev. F

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