8 Nguyenvanhao dt901 6576 PDF

B GIO DC V O TO
TRNG.
n
IU KHIN MOTOR
BC V VN DNG
KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

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LI NI U
Ngy nay k thut vi iu khin tr nn quen thuc trong ngnh k thut
v c trong cc ng dng i thng. Hu ht cc dy truyn t ng ln v cc
sn phn dn dng ta u thy s sut hin ca vi iu khin. Vi iu khin c
nh sn xut tch hp rt nhiu cc nhiu tnh nng vi cc b ngoi vi c tch
hp ngay trn vi iu khin, cng vi kh nng x l nhiu hot ng phc tp,
tt c c tch hp trn mt con chip nh gn, chnh v vy s gp nhiu thun
li hn trong thit k board, khi board mch s nh gn v p hn d thit k
hn rt nhiu. Cng vi s pht trin ca khoa hc k thut l s pht trin ca vi
iu khin v cc ng dng ca n trong k. chnh v vy em la chn ti:
IU KHIN MOTOR BC, v vn dng n thc hin ti trn.
Trong qu trnh lm n tt nghip, do s hn ch v thi gian, ti liu v
trnh c hn nn khng trnh khi c thiu st. Em rt mong c s ng
gp kin ca thy c trong hi ng v cc bn n tt nghip ca em
c hon thin hn.

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Chng 1.
TNG QUAN V CC PHN T
1.1. Vi iu khin
Thng thng c 4 h vi iu khin 8 bit chnh l 6811 ca Motorola, 8051
ca Intel, z8 ca Xilog v Pic 16 ca Microchip Technology. Mi mt loi trn
y u c mt tp lnh v thanh ghi ring duy nht, nn chng thng khng
tng thch ln nhau. Ngoi ra cng c nhng b vi iu khin 16 bit v 32 bit
c sn xut bi cc hng khc nhau. Vi tt c nhng b vi iu khin khc
nhau th tiu chun la chn l:
* p ng c nhu cu tnh ton ca bi ton mt cch hiu qu, y
chc nng cn thit v thp nht v mt gi thnh. Trong khi phn tch cc nhu
cu ca mt d n da trn b vi iu khin chng ta phi bit b vi iu khin
no l 8 bit, 16 bit hay 32 bit c th p ng tt nht nhu cu ca bi ton mt
cch hiu qu. Nhng tiu chun l:
- Tc : tc ln nht m vi iu khin h tr l bao nhiu.
- Kiu ng v: ng v kiu DIP 40 chn hay QFP. y l yu cu quan
trng xt v khng gian, kiu lp rp v to mu th cho sn phm cui cng.
- Cng sut tiu th: iu ny c bit kht khe i vi cc sn phm dng
pin, c quy.
- Dung lng b nh Rom v Ram trn chp.
- S chn vo ra v b nh thi trn chp.
- Kh nng d dng nng cp cho hiu sut cao hoc gim cng sut tiu th.
- Gi thnh cho mt n v: iu ny quan trng quyt nh gi thnh sn
phm m mt b vi iu khin c s dng.

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*) C sn cc cng c pht trin phn mm nh cc trnh bin dch, trnh

hp ng v g ri.
*) Ngun cc b vi iu khin sn c nhiu v tin cy. Kh nng sn sng
p ng v s lng trong hin ti tng lai.
Hin nay cc b vi iu khin 8 bit h 8051 l c s lng ln nht cc nh
cung cp a dng nh Intel, Atmel, Philip Nhng v mt tnh nng v cng
nng th c th xem PIC vt tri hn rt nhiu so vi 89 vi nhiu module c
tch hp sn nh ADC10 BIT, PWM 10 BIT, PROM 256 BYTE,
COMPARATER, VERF COMPARATER, mt c im na l tt c cc vi iu
khin PIC s dng th u c chun PI tc chun cng nghip thay v chun PC
(chun dn dng). Ngoi ra PIC cn c rt nhiu nh sn xut phn mm to ra
cc ngn ng h tr cho vic lp trnh ngoi ngn ng Asembly ra cn c th s
dng ngn ng C th s dng CCSC, HTPIC hay s dng Basic th c
MirkoBasic v cn nhiu chng trnh khc na h tr cho vic lp trnh
bn cnh ngn ng kinh in l asmbler. Nn trong ti ny ti la chn s
dng vi iu khin PIC lm b iu khin chnh, v y l PIC16F877A.
1.1.1. S khi v bng m t chc nng cc chn ca PIC16F877A

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Hnh 1.1. PIC 16F877A

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Hnh 2. S khi ca PIC16F877A

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Bng m t chc nng cc chn ca PIC16F877A

Pin Name
OSC1/CLKIN
DIP
Pin#
13
PLCC QFT
Pin#
Pin#
14
30
I/O/
Buffer
P
Type
Type
ST/CMOS(
4)
Description
u vo ca xung dao
ng thch anh/ng
vo xung clock ngoi
u ra ca xung dao
OSC2/CLKOUT
18
ng thch anh. Ni
vi thch anh hay cng
hng trong ch dao
ng
ca
thch
anh.Trong ch RC,
ng ra ca chn OSC2.
Ng vo ca Master
Clear(Reset) hoc ng
MCLR /Vpp
RA0/AN0
RA1/AN1
18
19
20
I/P
I/O
I/O
ST
TTL
TTL
vo in th c lp
trnh. Chn ny cho
php tn hiu Reset
thit b tc ng mc
thp.
PORTA l port vo ra
hai chiu. RA0 c th
lm ng vo tung t
th 0.
RA1 c th lm ng
vo tung t th 1

================================================================================
RA2 c th lm ng
RA2/AN2/VREF
I/O
TTL
21
vo tung t 2 hoc
in p chun tng t
m.
RA3 c th lm ng
RA3/AN3/VREF +
22
I/O
TTL
vo tung t 3 hoc
in p chun tng t
dng.
RA4/T0CKI
23
I/O
ST
RA4 c th lm ng
vo xung clock cho b
nh thi Timer0.
RA5/ SS /AN4
24
I/O
TTL
RA5 c th lm ng
vo tng t th 4
RB0/INT
33
36
I/O
TTL/ST(1)
PORTB l port hai

chiu.
RB1
34
37
I/O
TTL
RB2
35
38
10
I/O
TTL
RB0 c th lm chn
ngt ngo
RB3 c th lm ng
RB3/PGM
36
39
11
I/O
TTL
vo ca in th c
lp trnh mc thp.

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Interrupt-on-change
pin.
Interrupt-on-change
pin.
RB4
37
41
14
I/O
TTL
RB5
38
42
15
I/O
TTL
RB6/PGC
39
43
16
I/O
TTL/ST(2)
RB7/PGD
Interrupt-on-change pin
40
44
17
I/O
TTL/ST(3)
hoc
In-Crcuit Debugger pin
.
Serial
clock.
programming
Interrupt-on-change pin
hoc
In-Crcuit Debugger pin
.
Serial
data .
programming
PORTC l port vo ra
hai chiu.
RC0/T1OSO/T1C
KI
15
16
32
I/O
ST
RC0 c th l ng vo
ca b dao ng
Timer1 hoc ng xung
clock cho Timer1
RC1/T1OSI/CCP2
16
18
35
I/O
ST
RC1 c th l ng vo
ca b dao ng
Timer1 hoc ng vo

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Capture2/ng
ra
compare2/ng
vo
PWM2.
RC2/CCP1
17
19
36
I/O
ST
RC3/SCK/SCL
18
20
37
I/O
ST
RC4/SDI/SDA
23
25
42
I/O
ST
RC2 c th ng vo
capture1/ng
ra
compare1/ng
PWM1
vo
RC3 c th l ng vo
xung
Clock ng b ni
tip/ng ra trong c hai
ch SPI v I2C
RC4 c th l d liu
bn trong SPI(ch
SPI) hoc d liu
I/O(ch I 2 C).
RC5/SDO
RC6/TX/CK
24
25
26
27
43
44
I/O
I/O
ST
ST
RC5 c th l d liu
ngoi SPI(ch SPI)
RC6 c th l chn
truyn khng ng b
USART hoc ng b
vi xung ng h
RC7/RX/DT
26
29
I/O
ST
RC7 c th l chn
nhn khng ng b
USART hoc ng b

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vi d liu.
RD0/PSP0
19
21
38
I/O
ST/TTL(3)
RD1/PSP1
20
22
39
I/O
ST/TTL(3)
RD2/PSP2
21
23
40
I/O
ST/TTL(3)
RD3/PSP3
22
24
41
I/O
ST/TTL(3)
RD4/PSP4
27
30
I/O
ST/TTL(3)
RD5/PSP5
28
31
I/O
ST/TTL(3)
RD6/PSP6
29
32
I/O
ST/TTL(3)
RD7/PSP7
30
33
I/O
ST/TTL(3)
PORTD l port vo ra
hai chiu hoc l
parallel slave port khi
giao tip vi bus ca
b vi x l.
PORTE l port vo ra
hai chiu.
RE0/ RD /AN5
25
I/O
ST/TTL(3)
RE0 c th iu khin
vic c parrallel slave
port hoc l ngoc vo
tng t th 5.
RE1/ WR /AN6
RE2/ CS /AN7
10
10
11
26
27
I/O
I/O
ST/TTL(3)
ST/TTL(3)
RE1 c th iu khin
vic ghi parallel slave
port hoc l ng vo
tng t th 6.
RE2 c th iu khin
vic chn parallel slave
port hoc l ng vo
tng t th 7
Vss
VDD
12,
31
13, 34
7, 28
Cung cp ngun dng

cho cc mc logicv
nhng chn I/O.

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11,
12, 35
6, 29
1,17,2
8, 40
12,13
32
NC
33, 4
Nhng chn ny khng

c ni bn trong v
n c trng
Ghi ch: I = input; O = output; I/O = input/output; P = power

- = Not used; TTL = TTL input; ST = Schmitt Trigger input
1. L vng m c ng vo Trigger Schmitt khi c cu hnh nh ngt
ngoi.
2. L vng m c ng vo Trigger Schmitt khi c s dng trong ch 9
Serial Programming.
3. L vng m c ng vo Trigger Schmitt khi c cu hnh nh ng vo
ra mc ch chung v l ng vo TTL khi s dng trong ch Parallel Slave
Port (cho vic giao tip vi cc bus ca b vi x l).
4. L vng m c ng vo Trigger Schmitt khi c cu hnh trong ch
dao ng RC v mt ng vo CMOS khc.
1.1.2. T chc b nh
C 2 khi b nh trong cc vi iu khin h PIC16F87X, b nh chng
trnh v b nh d liu, vi nhng bus ring bit c th truy cp ng thi.

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Hnh 3. Ngn xp v bn b nh chng trnh PIC16F877A
1.1.2.1. T chc ca b nh chng trnh

Cc vi iu khin h PIC16F877A c b m chng trnh 13 bit c kh
nng nh v khng gian b nh chng trnh ln n 8Kb.Cc IC PIC16F877A
c 8Kb b nh chng trnh FLASH, cc IC PIC16F873/874 ch c 4 Kb.Vect
RESET t ti a ch 0000h v vect ngt ti a ch 0004h.

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1.1.2.2. T chc b nh d liu

B nh d liu c chia thnh nhiu dy v cha cc thanh ghi mc ch
chung v cc thanh ghi chc nng c bit. BIT RP1 (STATUS <6>) v RP0
(STATUS <5>) l nhng bit dng chn cc dy thanh ghi.
RP1:RP0
Bank
00
01
10
11
Chiu di ca mi dy l 7Fh (128 byte). Phn thp ca mi dy dng

cha cc thanh ghi chc nng c bit.Trn cc thanh ghi chc nng c bit l
cc thanh ghi mc ch chung, c chc nng nh RAM tnh. Thng th nhng
thanh ghi c bit c s dng t mt dy v c th c nh x vo nhng dy
khc gim bt on m v kh nng truy cp nhanh hn.
1.1.2.3. Cc thanh ghi mc ch chung
Cc thanh ghi ny c th truy cp trc tip hoc gin tip thng qua thanh
ghi FSG (File Select Register).

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Hnh 4. Cc thanh ghi ca PIC16F877A

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1.1.2.4. Cc thanh ghi chc nng c bit

Cc thanh ghi chc nng c bit (Special Function Resgister) c s dng
bi CPU v cc b nh ngoi vi iu khin cc hot ng c yu cu ca
thit b. Nhng thanh ghi ny c chc nng nh RAM tnh. Danh sch nhng
thanh ghi nay c trnh by bng di. Cc thanh ghi chc nng c bit c
th chia thnh hai loi: phn trung tm (CPU) v phn ngoi vi.
1.1.2.5. Cc thanh ghi trng thi
Hnh 5. Thanh ghi trng thi (a ch 03h, 83h, 103h, 183h)

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Thanh ghi trng thi cha cc trng thi s hc ca b ALU, trng thi
RESET v nhng bits chn dy thanh ghi cho b nh d liu. Thanh ghi trng
thi c th l ch cho bt k lnh no, ging nh nhng thanh ghi khc. Nu
thanh ghi trang thi l ch cho mt lnh m nh hng n cc c Z, DC hoc C,
v sau nhng bit ny s c v hiu ho. Nhng bit ny c th t hoc xo
tu theo trng thi logic ca thit b. Hn na hai bit TO v PD th khng cho
php ghi, v vy kt qu ca mt tp lnh m thanh ghi trng thi l ch c th
khc hn d nh. V d, CLRF STATUS s so 3 bit cao nht v t bit Z. Lc
ny cc bits ca thanh ghi trng thi l 000u u1uu (u = unchanged). Ch c cc
lnh BCF, BSF, SWAPF v MOVWF c s dng thay i thanh ghi trng
thi, bi v nhng lnh ny khng lm nh hng n cc bit Z, DC hoc C t
thanh ghi trng thi. i vi nhng lnh khc th khng nh hng n nhng
bits trng thi ny.

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1.1.3. Cc cng ca PIC 16F877A

1.1.3.1. PORTA v thanh ghi TRISA
Hnh 6. S khi ca chn RA3:RA0 v RA5

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Hnh 7. S khi ca chn RA4/T0CKI
1.1.3.2. PORTB v thanh ghi TRISB

PORTB c rng 8 bit, l port vo ra hai chiu. Ba chn ca PORTB c
a hp vi chc nng lp trnh mc in th thp (Low Voltage Programming ):
RB3/PGM, RB6/PGC v RB7/PGD. Mi chn ca PORTB c mt in tr ko
ln yu th bn trong. Mt bit iu khin c th m tt c nhng in tr ko ny
ln. iu ny c thc hin bng cch xo bit RBPU (OPTION_REG<7>).
Nhng in tr ny b cm khi c mt Power-on Reset. Bn chn ca PORTB:
RB7 n RB4 c mt ngt thay i c tnh .Ch nhng chn c cu hnh
nh ng vo mi c th gy ra ngt ny. Nhng chn vo (RB7:RB4) c so
snh vi gi tr c cht trc trong ln c cui cng ca PORTB. Cc kt
qu khng ph hp ng ra trn chn RB7:RB4 c OR vi nhau pht ra
mt ngt Port thay i RB vi c ngt l RBIF (INTCON<0>). Ngt ny c th

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nh thc thit b t trng thi ngh (SLEEP). Trong th tc phc v ngt ngi
s dng c th xo ngt theo cch sau:
a) c hoc ghi bt k ln PORTB. iu ny s kt thc iu kin khng ho hp.
b) Xo bit c RBIF.
Hnh 8. S khi cc chn RB3:RB0

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Hnh 9. S khi cc chn RB7:RB4
1.1.3.3. PORTC v thanh ghi TRISC

PORTC c rng l 8 bit, l port hai chiu. Thanh ghi d liu trc tip
tng ng l TRISC. Cho tt c cc bit ca TRISC l 1 th cc chn tng ng
PORTC l ng vo. Cho tt c cc bit ca TRISC l 0 th cc chn tng ng
PORTC l ng ra. PORTC c a hp vi vi chc nng ngoi vi, nhng chn
ca PORTC c m Trigger Schmitt ng vo. Khi b I2C c cho php, chn

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3 v 4 ca PORTC c th cu hnh vi mc I2C bnh thng, hoc vi mc

SMBus bng cch s dng bit CKE (SSPSTAT<6>). Khi nhng chc nng ngoi
vi c cho php, chng ta cn phi quan tm n vic nh ngha cc bits ca
TRIS cho mi chn ca PORTC. Mt vi thit b ngoi vi ghi ln bit TRIS th
to nn mt chn ng ra, trong khi nhng thit b ngoi vi khc ghi ln bit
TRIS th s to nn mt chn ng vo. Khi nhng bit TRIS ghi b tc ng
trong khi thit b ngoi vi c cho php, nhng lnh c thay th ghi (BSF,
BCF, XORWF) vi TRISC l ni n cn phi c trnh. Ngi s dng cn
phi ch ra vng ngoi vi tng ng m bo cho vic t TRIS bit l ng.

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Hnh 10. S khi ca cc chn RC<4:3>

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Hnh 11. S khi ca cc chn RC<2:0> v RC<7:5>
1.1.3.4. PORTD v thanh ghi TRISD

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PORTD l port 8 bit vi m Trigger Schmitt ng vo. Mi chn c th

c cu hnh ring l nh mt ng vo hoc ng ra. PORTD c th c cu
hnh nh port ca b vi x l rng 8 bit (parallel slave port) bng cch t bit
iu khin PSPMIDE (TRISE <4>). Trong ch ny, m ng vo l TTL.
Hnh 12. S khi ca PORTD (trong ch l port I/O)
1.1.3.5. PORTE v thanh ghi TRISE

PORTE c ba chn (RE0/RD/AN5, RE1/WR/AN6, v RE2/CS/AN7) mi
chn c cu hnh ring l nh nhng ng vo hoc nhng ng ra. Nhng chn
ny c m Trigger Schmitt ng vo. Nhng chn ca PORTE ng vai tr nh
nhng ng vo iu khin vo ra cho Port ca vi x l khi bit PSPMODE
(TRISE <4>) c t. Trong ch ny, ngi s dng cn phi chc chn rng
nhng bit TRISE <2:0> c t, v chc rng nhng chn ny c cu hnh

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nh nhng ng vo s. Cng bo m rng ADCON1 c cu hnh cho vo ra

s. Trong ch ny, nhng m ng vo l TTL.
Nhng chn ca PORTE c a hp vi nhng ng vo tng t, Khi
c chn cho ng vo tng t, nhng chn ny s c gi tr "0". TRISE iu
khin hng ca nhng chn RE ch khi nhng chn ny c s dng nh
nhng ng vo tng t. Ngi s dng cn phi gi nhng chn c cu hnh
nh nhng ng vo khi s dng chng nh nhng ng vo tng t.
Hnh 13. S khi ca PORTE (trong ch I/O port)
1.1.4. Hot ng cu nh thi

1.1.4.1. B nh thi TIMER0
B nh thi/b m Timer0 c cc c tnh sau:

================================================================================
B nh thi / b m 8 bit
Cho php c v ghi
B chia 8 bit lp trnh c bng phn mm
Chn xung clock ni hoc ngoi
Ngt khi c s trn t FFh n 00h
Chn sn cho xung clock ngoi
S khi ca b nh thi Timer0 v b chia dng chung vi WDT c
a ra trong hnh 14.
Hnh 14. S khi ca b nh thi Timer0 v b chia dng chung vi WDT
Ch nh thi (Timer) c chn bng cch xo bit T0CS

(OPTION_REG<5>). Trong ch nh thi, b nh thi Timer0 s tng dn

================================================================================
sau mi chu k lnh (khng c b chia). Nu thanh ghi TmR0 c ghi th s

tng s b ngn li sau hai chu k lnh.
Ch m (Counter) c chn bng cch xo bit T0CS
(OPTION_REG<5>). Trong ch m, Timer0 s tng dn mi cnh ln
xung ca chn RA4/T0CKI. S tng sn c xc nh bi bit Timer0 Source
Edge Select, T0SE (OPTION_RE<4>). B chia ch c dng chung qua li gia
b nh thi Timer0 v b nh thi Watchdog. B chia khng cho php c hoc
ghi
Ngt Timer0
Ngt TMR0 c pht ra khi thanh ghi TMR0 trn t FFh n 00h. S trn
ny s t bit T0IF (INTCON<2>). Ngt ny c th c giu i bng cch xa
bit T0IE (INTCON<5>) . Bit T0IF cn phi c xa trong chng trnh bi th
tc phc v ngt ca b nh thi Timer0 trc khi ngt ny c cho php li.
S dng Timer0 vi xung clock ngoi
Khi b chia khng c s dng, clock ngoi t vo th ging nh b chia
ng ra. S ng b ca chn T0CKI vi clock ngoi c thc hin bng cch
ly mu b chia ng ra trn chn Q2 v Q4. V vy thc s cn thit chn
T0CKI mc cao trong t nht 2 chu k my v mc thp trong t nht 2 chu
k my.
B chia
Thit b PIC16F87X ch c mt b chia m c dng chung bi b nh
thi TIMER0 v b nh thi Watchdog. Mt khi b chia c n nh cho b
nh thi 0 th khng
B nh thi TIMER1 l mt b nh thi/b m 16 bit gm hai thanh ghi
TMR1H (Byte cao) v TMR1L (byte thp) m c th c hoc ghi. Cp thanh ghi
ny tng s m t 0000h n FFFFh v bo trn s xut hin khi c s chuyn
s m t FFFFh xung 0000h. Ngt, nu c php c th pht ra khi c s m

================================================================================
trn v c t bit c ngt TMR1IF. Ngt c th c php hoc cm bng

cch t hoc xo bit cho php ngt TMR1IE.
B nh thi Timer1 c th c cu hnh hot ng mt trong hai ch sau:
nh thi mt khong thi gian (timer)
m s kin (Counter)
Vic la chn mt trong hai ch c xc nh bng cch t hoc xo
bit iu khin TMR1ON.
---- ---- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Bit7
Bit0
Bit 7-6
Khng c nh ngha
Bit 5-4
bit chn b chia clock cho timer1
Bit 3
bit iu khin cho php b dao ng Timer1
Bit 2
bit iu khin clock ngoi Timer
Bit 1
bit chn ngun clock cho Timer1
Bit 0
bit iu khin hot ng ca Timer1
Ch Timer
Ch Timer c chn bng cch xo TMR1CS. Trong ch ny,
Ngun clock t vo Timer l mch dao ng FOSC/4. Bit iu khin ng b
khng b tc ng v clock ngoi lun lun ng b.

================================================================================
Hnh 15. Cnh tng timer1
Ch counter
Trong ch ny, b nh thi tng s m qua clock ngoi. Vic tng xy
ra sau mi sn ln ca xung clock ngoi. B nh thi phi c mt sn ln
trc khi vic m bt u.
Hnh 16. S khi b nh thi timer1

B nh thi TIMER2 l b nh thi 8 bit vi mt chia v mt b potscaler.
N thng dng chung vi b CCP trong ch PWM (s c cp phn
sau). Thanh ghi TMR2 c th c hoc ghi v c xo khi c bt k tn hiu
reset no ca thit b
B nh thi TIMER2 c mt thanh ghi chu k 8 bit, PR2. B nh thi tng
s m ln t 00h n gi tr c ghi trong thanh ghi TR2 v sau reset li gi
tr 00h trong chu k k tip. PR2 l thanh ghi c th c hoc ghi.
Gi tr trng hp trong thanh ghi TMR2 c i qua b postscaler 4 bit
pht ra mt ngt TMR2 (c t bit c ngt TMR2IF). B nh thi TIMER2
c th c tt (khng hot ng) bng cch xo bt iu khin TMR2ON
gin thiu cng sut tiu tn ngun.

================================================================================
Hnh 17. S khi ca TIMER2

================================================================================
Hnh 18. T2CON: Thanh ghi iu khin Timer2 (a ch 12h)
Mt c im khc ca vi iu khin Pic16F877A l c b dao ng ch

trn chip iu, n s gip trnh c nhng sai s khng cn thit trong vic to
xung dao ng, vi iu khin Pic16F877A c kh nng t Reset bng b WDT,
v c thm 256 byte EEPROM. Nhng gi thnh ca Pic t hn so vi 8051.
1.2. Thit b hin th LCD
Ngy nay, thit b hin th LCD (Liquid Crystal Display) c s dng trong
rt nhiu cc ng dng ca VK. LCD c rt nhiu u im so vi cc dng hin
th khc nh n c kh nng hin th k t a dng, trc quan (ch, s v k t
ha), d dng a vo mch ng dng theo nhiu giao thc giao tip khc nhau,
tn rt t ti nguyn h thng v gi thnh r ... Trong ti ny ti s dng
HD44780 ca Hitachi, mt loi thit b hin th LCD rt thng dng nc ta.
1.2.1. Hnh dng kch thc.
C rt nhiu loi LCD vi nhiu hnh dng v kch thc khc nhau, trn
hnh 3.1. l hai loi LCD thng dng.
Hnh 3.1. Hnh hai loi LCD thng dng.

================================================================================
Hnh 3.2. S chn ca LCD
Hnh 3.3. LCD loi DM 1602A.

Khi sn xut LCD, nh sn xut tch hp chp iu khin (HD44780) bn
trong lp v v ch a cc chn giao tip cn thit. Cc chn ny c nh s
th t v t tn nh hnh 3.2.
1.2.2. Cc chn chc nng.
Bng 3.1. Cc chn chc nng ca HD44780.
Chn s Tn
Chc nng
Vss
Chn ni t cho LCD, khi thit k mch ta ni chn ny

vi GND ca mch iu khin.
Vdd
Chn cp ngun cho LCD, khi thit k mch ta ni chn

ny vi 5V ca mch iu khin.
Vo
Chn ny dng iu chnh tng phn ca LCD.
RS
Chn chn thanh ghi (Register select). Ni chn RS vi

logic 0 (GND) hoc logic 1 (Vcc) chn thanh ghi.

================================================================================
+ Logic 0: Bus DB0-DB7 s ni vi thanh ghi lnh IR

ca LCD ( ch ghi - write) hoc ni vi b m
a ch ca LCD ( ch c - read)
+ Logic 1: Bus DB0-DB7 s ni vi thanh ghi d liu
DR bn trong LCD.
5
RW
Chn chn ch c/ghi (Read/Write). Ni chn R/W

vi logic 0 LCD hot ng ch ghi, hoc ni
vi logic 1 LCD ch c.
Chn cho php (Enable). Sau khi cc tn hiu c t

ln bus DB0-DB7, cc lnh ch c chp nhn khi c 1
xung cho php ca chn E.
+ ch ghi: D liu bus s c LCD chuyn vo
(chp nhn) thanh ghi bn trong n khi pht hin mt
xung (low-to-high transition) ca tn hiu chn E.
+ ch c: D liu s c LCD xut ra DB0-DB7
khi pht hin sn ln (low-to-high transition) chn E v
c LCD gi bus n khi no chn E xung mc thp.
714
DB0DB7 8 ng ca bus d liu dng trao i thng tin vi

MPU. C 2 ch s dng 8 ng bus ny:
+ Ch 8 bit: D liu c truyn trn c 8 ng, vi
bit MSB l bit DB7.
+ Ch 4 bit: D liu c truyn trn 4 ng t DB4
ti DB7, bit MSB l DB7.
15
15 l Catot, in p khong Uak=4,2V
16
Chn ni t ca n Back light
1.2.3. S khi ca HD44780.

hiu r hn chc nng cc chn v hot ng ca chng, ta tm hiu s
qua chp HD44780 thng qua cc khi c bn ca n.
*) Cc thanh ghi:

================================================================================
Chp HD44780 c 2 thanh ghi 8 bit quan trng l: Thanh ghi lnh IR
(Instructor Register) v thanh ghi d liu DR (Data Register).
- Thanh ghi IR: iu khin LCD, ngi dng phi ra lnh thng qua
tm ng bus DB0-DB7. Mi lnh c nh sn xut LCD nh a ch r rng.
Ngi dng ch vic cung cp a ch lnh bng cch np vo thanh ghi IR.
Ngha l, khi ta np vo thanh ghi IR mt chui 8 bit, chp HD44780 s tra bng
m lnh ti a ch m IR cung cp v thc hin lnh .
VD: Lnh hin th mn hnh c a ch lnh l 00001100 (DB7DB0)

================================================================================
Hnh 3.3. S khi ca HD44780.

- Thanh ghi DR: Thanh ghi DR dng cha d liu 8 bit ghi vo vng
RAM, DDRAM hoc CGRAM ( ch ghi) hoc dng cha d liu t 2
vng RAM ny gi ra cho MPU ( ch c). Ngha l, khi MPU ghi thng tin
vo DR, mch ni bn trong chp s t ng ghi thng tin ny vo DDRAM hoc
CGRAM. Hoc khi thng tin v a ch c ghi vo IR, d liu a ch ny
trong vng RAM ni ca HD44780 s c chuyn ra DR truyn cho MPU.

================================================================================
Vy bng cch iu khin chn RS v R/W chng ta c th chuyn qua li gi 2

thanh ghi ny trong khi giao tip vi MPU. Bng 3.2. tm tt li cc thit lp i
vi hai chn RS v R/W theo mc ch giao tip.
Bng 3.2. Bng chc nng chn RS v R/W theo mc ch s dng.
RS
RW
ngha
Ghi vo thanh ghi IR ra lnh cho LCD (VD:

cn display clear, )
c c bn DB7 v gi tr ca b m a ch
DB0-DB6
Ghi vo thanh ghi DR
c d liu t DR
*) C bo bn BF (Busy Flag):
Khi thc hin cc hot ng bn trong chp, mch ni bn trong cn mt
khong thi gian hon tt. Khi ang thc thi cc hot ng bn trong chp nh
th, LCD b qua mi giao tip vi bn ngoi v bt c BF (thng qua chn DB7
khi c thit lp RS=0, R/W=1) ln bo cho MPU bit n ang bn. D nhin,
khi xong vic, n s t c BF li mc 0.
*) B m a ch AC (Address Counter):
Nh trong s khi, thanh ghi IR khng trc tip kt ni vi vng RAM
(DDRAM v CGRAM) m thng qua b m a ch AC. B m ny li ni vi
2 vng RAM theo kiu r nhnh. Khi mt a ch lnh c np vo thanh ghi
IR, thng tin c ni trc tip cho 2 vng RAM nhng vic chn la vng
RAM tng tc c bao hm trong m lnh. Sau khi ghi vo (hoc c t)
RAM, b m AC t ng tng ln (hoc gim i) 1 n v v ni dung ca AC
c xut ra cho MPU thng qua DB0-DB6 khi c thit lp RS=0 v R/W=1
(xem bng 3.2). Lu : Thi gian cp nht AC khng c tnh vo thi gian
thc thi lnh m c cp nht sau khi c BF ln mc cao (not busy), cho nn

================================================================================
khi lp trnh hin th, bn phi delay mt khong tADD khong 4S-5S (ngay
sau khi BF=1) trc khi np d liu mi.
*) Vng RAM hin th DDRAM (Display Data RAM):
y l vng RAM dng hin th, ngha l ng vi mt a ch ca RAM
l mt k t trn mn hnh v khi bn ghi vo vng RAM ny mt m 8 bit,
LCD s hin th ti v tr tng ng trn mn hnh mt k t c m 8 bit m bn
cung cp nh hnh 3.3.
Hnh 3.4. Mi lin h gia a ch ca DDRAM v v tr hin th ca LCD.

Vng RAM ny c 80x8 bits nh, ngha l cha c 80 k t m 8 bits.
Nhng vng RAM cn li khng dng cho hin th c th dng nh vng RAM
a mc ch. Lu l truy cp vo DDRAM, ta phi cung cp a ch cho AC
theo m HEX.
*) Vng ROM cha k t CGROM (Character Generator ROM):
Vng ROM ny dng cha cc mu k t loi 5x8 hoc 5x10 im nh/k
t, v nh a ch bng 8 bit. Tuy nhin, n ch c 208 mu k t 5x8 v 32 mu

================================================================================
k t kiu 5x10 (tng cng l 240 thay v 256 mu k t). Ngi dng khng th
thay i vng ROM ny.
Hinh 3.5. Mi lin h gia a ch ca ROM v d liu to mu k t.

*) Vng RAM cha k t ha CGRAM (Character Generator RAM):
Nh trn bng m k t, nh sn xut dnh vng c a ch byte cao l 0000h
ngi dng c th to cc mu k t ha ring. Tuy nhin dung lng vng
ny rt hn ch: Ta ch c th to 8 k t loi 5x8 im nh, hoc 4 k t loi
5x10 im nh. ghi vo CGRAM, xem hnh 3.6.
1.2.4. Tp lnh ca LCD.
Trc khi tm hiu tp lnh ca LCD, sau y l mt vi ch khi giao tip
vi LCD:

================================================================================
* Tuy trong s khi ca LCD c nhiu khi khc nhau, nhng khi lp
trnh iu khin LCD ta ch c th tc ng trc tip c vo 2 thanh ghi DR v
IR thng qua cc chn DBx, v ta phi thit lp chn RS, R/W ph hp
chuyn qua li gi 2 thanh ghi ny. (xem bng 3.2)
Hnh 3.6. Mi lin h gia a ch ca CGRAM, d liu CGARM, v m k t.

* Vi mi lnh, LCD cn mt khong thi gian hon tt, thi gian ny c
th kh lu i vi tc ca MPU, nn ta cn kim tra c BF hoc i (delay)
cho LCD thc thi xong lnh hin hnh mi c th ra lnh tip theo.
* a ch ca RAM (AC) s t ng tng (gim) 1 n v, mi khi c lnh
ghi vo RAM. (iu ny gip chng trnh gn hn)
* Cc lnh ca LCD c th chia thnh 4 nhm nh sau:

================================================================================
Cc lnh v kiu hin th. VD : Kiu hin th (1 hng/2 hng), chiu di d

liu (8 bit/4 bit),
Ch nh a ch RAM ni.
Nhm lnh truyn d liu trong RAM ni.
Cc lnh cn li .
Bng 3.3. Tp lnh ca LCD.
Thi
Tn lnh
Hot ng
gian
chy
Clear
Display
M lnh: DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DBx = 0
0
0
0
0
0
0
1
Lnh Clear Display (xa hin th) s ghi mt khong trng (m hin
th k t 20H) vo tt c nh trong DDRAM, sau tr b m
a ch AC=0, tr li hin th gc nu n b thay i, ngha l: Tt
hin th, con tr di v gc tri (hng u tin), ch tng AC.
Return
home
Entry
mode set
DBx = 0
0
0
0
0
0
1
*
Lnh Return home tr b m a ch AC v 0, tr li kiu hin th 1.52 ms
gc nu n b thay i. Ni dung ca DDRAM khng thay i.
DBx = 0
0
0
0
0
1 [I/D] [S]
I/D: Tng (I/D=1) hoc gim (I/D=0) b m a ch hin th AC 1
n v mi khi c hnh ng ghi hoc c vng DDRAM. V tr
con tr cng di chuyn theo s tng gim ny.
S: Khi S=1 ton b ni dung hin th b dch sang phi (I/D=0) hoc
sang tri (I/D=1) mi khi c hnh ng ghi vng DDRAM. Khi
S=0: khng dch ni dung hin th. Ni dung hin th khng dch
khi c DDRAM hoc c/ghi vng CGRAM.
37s

================================================================================
Hnh 3.7. Hot ng dch tri v dch phi ni dung hin th

M lnh: DBx = DB7 DB6 DB5 DB4 DB3
DBx = 0
0
0
0
1
D: Hin th mn hnh khi D=1 v ngc li.
dung DDRAM khng thay i.
C: Hin th con tr khi C=1 v ngc li. V
DB2 DB1 DB0

[D] [C] [B]
Khi tt hin th, ni
tr v hnh dng con
tr, xem hnh 3.8.

B: Nhp nhy k t ti v tr con tr khi B=1 v ngc li. Xem
thm hnh 8. v kiu nhp nhy. Chu k nhp nhy khong 409,6ms
khi mch dao ng ni LCD l 250kHz.
Display
on/off
control
37s
Hnh 3.8. Kiu con, kiu k t v nhp nhy k t

Cursor
or
DBx = 0
0
0
1 [S/C] [R/L] *
*

================================================================================
display
Lnh Cursor or display shift dch chuyn con tr hay d liu hin
shift
th sang tri m khng cn hnh ng ghi/c d liu. Khi hin th

kiu 2 dng, con tr s nhy xung dng di khi dch qua v tr th
40 ca hng u tin. D liu hng u v hng 2 dch cng mt
37s
lc. Chi tit s dng xem bng sau:
Function
DBx = 0
0
1 [DL] [N] [F]
*
*
DL: Khi DL=1, LCD giao tip vi MPU bng giao thc 8 bit (t bit
DB7 n DB0). Ngc li, giao thc giao tip l 4 bit (t bit DB7
n bit DB0). Khi chn giao thc 4 bit, d liu c truyn/nhn 2
ln lin tip vi 4 bit cao gi/nhn trc, 4 bit thp gi/nhn sau.
N: Thit lp s hng hin th. Khi N=0: hin th 1 hng, N=1: hin
th 2 hng.
set
F: Thit lp kiu k t. Khi F=0: kiu k t 5x8 im nh, F=1: kiu

k t 5x10 im nh.
* Ch :
Ch thc hin thay i Function set u chng trnh. V sau
khi c thc thi 1 ln, lnh thay i Function set khng c LCD
chp nhn na ngoi tr thit lp chuyn i giao thc giao tip.
Khng th hin th kiu k t 5x10 im nh kiu hin th 2
hng.
37s
Set
DBx= 0 1 [ACG][ACG][ACG][ACG][ACG][ACG]
CGRAM Lnh ny ghi vo AC a ch ca CGRAM. K hiu [ACG] ch 1 bit
address
ca chui d liu 6 bit. Ngay sau lnh ny l lnh c/ghi d liu t
CGRAM ti a ch c ch nh.
Set
37s

================================================================================
DDRAM
address
DBx = 1 [AD] [AD] [AD] [AD] [AD] [AD] [AD]

Lnh ny ghi vo AC a ch ca DDRAM, dng khi cn thit lp
ta hin th mong mun. Ngay sau lnh ny l lnh c/ghi d
liu t DDRAM ti a ch c ch nh. Khi ch hin th
37s
1 hng, a ch c th t 00H n 4FH. Khi ch hin th 2

hng, a ch t 00h n 27H cho hng th nht, v t 40h n 67h
cho hng th 2.
DBx= [BF] [AC] [AC] [AC] [AC] [AC] [AC] [AC]
(RS=0, R/W=1)
Read BF
and
address
Nh cp trc y, khi c BF bt, LCD ang lm vic v lnh

tip theo (nu c) s b b qua nu c BF cha v mc thp. Cho
nn, khi lp trnh iu khin, bn phi kim tra c BF trc khi ghi
d liu vo LCD. Khi c c BF, gi tr ca AC cng c xut ra
cc bit [AC]. N l a ch ca CG hay DDRAM l ty thuc vo
lnh trc .
0s
DBx = [Write data]
(RS=1, R/W=0)
Write
ata to
CG or
DDRAM
Khi thit lp RS=1, R/W=0, d liu cn ghi c a vo cc chn

DBx t mch ngoi s c LCD chuyn vo trong LCD ti a ch
c xc nh t lnh ghi a ch trc (lnh ghi a ch cng
xc nh lun vng RAM cn ghi). Sau khi ghi, b m a ch AC
t ng tng/gim 1 ty theo thit lp Entry mode. Lu l thi
gian cp nht AC khng tnh vo thi gian thc thi lnh.
DBx = [Read data] (RS=1, R/W=1)
Read data
Khi thit lp RS=1, R/W=1,d liu t CG/DDRAM c chuyn ra
from CG
MPU thng qua cc chn DBx (a ch v vng RAM c xc
or
nh bng lnh ghi a ch trc ). Sau khi c, AC t ng
DDRAM
tng/gim 1 ty theo thit lp Entry mode, tuy nhin ni dung hin
th khng b dch bt chp ch Entry mode.
37s
tADD
4s
37s
tADD
4s

================================================================================
1.2.5. c tnh ca cc chn giao tip.

LCD s b hng nghim trng, hoc hot ng sai lch nu bn vi phm
khong c tnh in sau y:
Bng 3.4. c tnh in lm vic in hnh.
c tnh in lm vic in hnh: (o trong iu kin hot ng Vcc = 4.5V

n 5.5V, T = -30 n +75C).
Bng 3.5. Min lm vic bnh thng.
1.3. IC ULN2003
i vi nhng ng dng m mi cun dy ca ng c dn dng nh hn
500mA, mch darlington h ULN200x ca Allegro Microsystems hoc h
DS200x ca National Semiconductor hay MC1413 ca Motorola s dn ng cho
cun dy hoc cc ti cm ng khc trc tip t tn hiu vo logic. Hnh 3.8 l
cc ng vo v ng ra ca chip ULN2003, dy 7 transistor darlington.

================================================================================
* S cc chn IC ULN2003
Hnh 3.8. S cc chn ca IC ULN2003
in tr nn trn mi transistor darlington phi thch hp vi tn hiu ra

TTL lng cc chun. Cc pht ca mi darlington NPN c ni vi chn 8, l
chn ni t. Mi transistor c bo v bng hai diode, mt ni gia cc pht v
cc thu bo v transistor khi in p ngc, mt ni cc thu vi chn 9, nu
chn 9 ni vi ngun ca ng c th diode ny s bo v transistor khi nh
nhn ca t cm.

================================================================================
+ Cc thng s c bn ca ICULN2003
Chc nng cc chn ca IC ULN2003

IC UNL2003 c 8 u vo (t chn 1 -> 7) c chc nng nhn cc tn hiu
dng vo cn khuych i.
IC UNL2003 c 8 u ra (t chn 9 -> 16), tn hiu qua cc chn -c
khuych i theo yu cu, v lm nhim v kt ni vi thit b cn h tr dng.
Chn 8 th-ng -c ni mt, chn 9 hoc 10 -c cp ngun +5V
1.4. MOTOR Bc
ng c bc c th c m t nh l mt ng c in khng dung
chuyn mch. C th cc mu trong ng c l stator, v rotor l nam chm vnh
cu, hoc trong trng hp ca ng c t bin tr, n l khi rng lm bng vt
liu nh c t tnh. Tt c cc mch o phi c iu khin bn ngoi bi b
iu khin, c bit cc ng c v b iu khin c thit k ng c c th
gi nguyn v tr c nh no cng nh l quay n bt k v tr no. Hu ht cc
ng c bc c th chuyn ng tn s m thanh, cho php chng quay kh

================================================================================
nhanh, v vi b iu khin thch hp, chng c th khi ng v dng li cc

v tr bt k.
Hnh 1.9. Mt s hnh dng v cu trc ng c bc

1.4.1. Cu to
Hnh 1.9. Cu to ng c bc
ng c bc c chia lm hai loi
chnh
gm nam chm vnh cu v bin t tr, ngoi ra c loi hn hp, nhng khng
khc g lm so vi loi nam chm vnh cu. ng c bin t tr thng c
3 mu,
vi
mt dy v
chung, trong
khi ng c
nam
chm vnh cu thng c hai mu phn bit, c hoc khng c nt trung tm.
Nt trung tm c
dng trong
ng
c
nam chm
vnh cu n cc. ng c bc phong ph v gc quay. Cc ng c km
nht quay 90 mi bc, trong khi cc ng c nam chm vnh cu x l
cao
thng
quay 1.8 n 0.72 mi bc.
Vi mt b
iu
khin, hu ht cc loi ng c nam chm vnh cu v hn hp u c th chy
ch na bc v mt vi b iu khin c th iu khin cc phn bc nh

================================================================================
hn hay cn gi l vi bc. i vi c ng c nam chm vnh cu hoc ng

c bin t tr, nu ch mt mu ca ng c c kch, rotor ( khng ti)
s nhy n mt gc c nh v sau gi nguyn gc cho n khi
moment xon vt qua gi tr moment xon gi (hold torque) ca ng c.
Hnh 1.1.
ng c bin t tr
c 3 cun dy, c ni nh trong biu hnh 1.1,
vi mt u ni chung cho
tt c cc cun. Khi s dng, dy ni chung (C) thng
c ni vo cc dng ca ngun v cc cun c kch theo th t lin tc.
Du thp trong hnh 1.1 l rotor ca ng c
bin
t tr
quay 30 mi bc. Rotor trong ng c
ny c 4 rng v stator c 6 cc,
mi cun qun quanh hai cc i din. Khi cun 1 c kch in rng X ca rotor
b ht vo cc 1. Nu dng qua cun 1 b ngt v ng dng qua cun 2, rotor s quay
30 theo chiu kim ng h v rng Y s ht vo cc 2. quay ng c ny mt
cch lin tc,
chng ta ch cn cp in lin tc lun
phin
cho 3 cun. Theo logic t ra, trong bng di y 1 c ngha l c dng in i qua
cc cun, v chui iu khin sau s quay ng c theo chiu kim ng h 24 bc
hoc 2 vng:
Cun 1 1001001001001001001001001
Cun 2 0100100100100100100100100
Cun 3 0010010010010010010010010
Hng thi gian -->
Phn iu khin mc trung bnh cung cp chi tit v phng php to ra cc dy
tn hiu iu khin

================================================================================
Hnh dng ng c c m t trong hnh 1.1, quay 30 mi bc, dng s rn

g rotor v s cc stator ti thiu. S dng nhiu cc v nhiu rng hn cho php ng
c quay vi gc nh hn. To mt rng trn b mt cc cc v cc rng trn rotor
mt cch ph hp cho php cc bc nh n vi .
Hnh 1.2.
ng c bc n cc, c nam chm vnh cu v ng c hn hp, vi 5, 6
hoc 8 dy ra thng c qun nh s hnh 1.2, vi mt u ni trung tm trn
cc cun. Khi dng, cc u ni trung tm thng c
ni vo cc dng ngun
cp,
v hai u cn li ca mi mu ln lt ni t o chiu t trng to bi
cun . thun tin, khi kho st ng c n cc, chng ta ch kho st
ng c nam chm vnh cu, vic iu khin ng c hn hp n cc hon
ton tng t.
Mu 1 nm cc trn v
di ca stator, cn mu 2 nm hai cc bn phi v bn tri ng c. Rotor l mt
nam chm vnh cu vi 6 cc, 3 Nam v 3 Bc, xp xen k trn vng trn. x l
gc
bc mc cao hn, rotor phi c
nhiu cc i xng hn.
ng c 30 mi bc trong hnh l mt trong nhng thit k ng c nam chm
vnh cu thng dng nht, mc d ng c c
bc 15 v 7.5 l kh ln.
Ngi ta cng to ra c ng c nam chm vnh cu vi mi bc l 1.8 v
vi ng c hn hp mi bc nh nht c th t c l 3.6 n 1.8 , cn tt
hn na, c th t n 0.72 . Nh trong hnh
1.2, dng in
i qua t u trung tm
ca
mu 1 n u a to ra cc Bc trong stator
trong khi cc cn li ca stator
l
cc
Nam.
Nu in mu 1 b ngt v kch mu 2, rotor s quay 30 , hay 1 bc. quay
ng c mt cch lin tc, chng ta ch cn t in p vo hai mu ca ng c theo
dy.

================================================================================
Mu 1a 1000100010001000100010001
Mu 1a 1100110011001100110011001
Mu 1b 0010001000100010001000100
Mu 1b 0011001100110011001100110
Mu 2a 0100010001000100010001000
Mu 2a 0110011001100110011001100
Mu 2b 0001000100010001000100010
Mu 2b 1001100110011001100110011
Hng thi gian -->
Nh rng hai na ca mt mu khng bao gi c kch cng mt lc. C hai
dy nu trn s quay ng c nam chm vnh cu mt bc mi thi im. Dy
bn tri ch cp in cho mt mu ti mt thi im, nh m t trong hnh trn;
V vy, n dng t nng lng hn. Dy bn phi i hi cp in cho c hai
mu mt lc v ni chung s to ra mt moment xoy ln hn dy bn tri 1.4 ln
trong
khi phi cp in gp 2 ln. V tr bc c to ra
bi hai
chui
trn khng ging nhau; kt qu, kt hp 2 chui trn cho php iu khin na
bc, vi vic dng ng c mt cch ln lt ti nhng v tr nu mt trong hai
dy trn. Chui kt hp nh sau:
Mu 1a 11000001110000011100000111
Mu 1b 00011100000111000001110000
Mu 2a 01110000011100000111000001
Mu 2b 00000111000001110000011100
Hng thi gian -->

================================================================================
Hnh 1.3
ng c nam chm vnh cu hn hp hai cc c cu trc c kh ging y

nh
ng c n cc, nhng hai mu ca ng c c ni n gin hn, khng c
u trung tm. V vy, bn thn ng c th n gin hn, nhng mch iu khin
o cc mi cp cc trong ng c th phc tp hn. Minh ho hnh 1.3 ch ra cch
ni ng c, trong khi phn rotor y ging y nh hnh 1.2. Mch iu khin
cho ng c i hi mt mch iu khin cu H cho mi mu; iu ny s c trnh
by
chi
tit
trong phn Cc mch iu khin. Tm li, mt cu H cho php cc ca ngun p n
mi u ca mu c iu khin mt cch c lp. Cc dy iu khin cho
mi
bc n ca loi ng c ny c nu bn di, dng + v - i din cho cc
cc ca ngun p c p vo mi u ca ng c:
u 1a + - - + - - - + - - - + - - u 1b - - + - - - + - - - + - - - + u 2a - + - - - + - - - + - - + - u 2b - - - + - - - + - - - + - - - +
++--++--++--++---++--++--++--++
-++--++--++--+++--++--++--++--+
Hng thi gian -->

Ch rng nhng dy ny ging nh trong ng c nam chm vnh cu n cc,
mc l thuyt, v rng mc mch ng ngt cu H, h thng iu khin cho
hai loi ng c ny l ging nhau. Ngoi
ra
lu
l
c rt nhiu chip iu khin cu H
c mt u vo iu khin v mt u khc iu khin hng. C loi chip

================================================================================
cu H k trn, dy iu khin di y s quay ng c ging nh dy iu khin nu

pha trn:
Enable 1 1010101010101010 1111111111111111
Hng 1 1x0x1x0x1x0x1x0x 1100110011001100
Enable 2 0101010101010101 1111111111111111
Hng 2 x1x0x1x0x1x0x1x0 0110011001100110
Hng thi gian -->
phn bit mt ng c nam chm vnh cu hai cc vi nhng ng c 4 dy
bin t tr, ta
o in tr gia cc cp dy. Ch l mt vi ng c nam chm vnh cu
c 4 mu c lp, c xp thnh 2 b. Trong mi b, nu hai mu c ni tip vi n
hau, th l ng c hai cc in
th cao. Nu chng c ni song song, th l ng c hai cc dng in th thp.
Nu chng c ni tip vi mt u trung tm, th dng nh vi ng c n cc in
th thp.
ng c nhiu pha
Hnh 1.4
Mt b phn cc ng c
khng c ph bin nh nhng loi trn l ng c nam chm vnh cu m cc
cun c qun ni tip thnh mt vng kn nh hnh 1.4.
Thit
k ph bin nht i vi loi ny s dng dy ni 3 pha v 5 pha. B iu khin
cn
cu H cho mi mt u ra ca ng c, nhng nhng ng c ny c th cung cp
moment xon ln hn so vi cc loi ng c bc khc cng kch thc. Mt vi

================================================================================
ng
c 5 pha c th x l cp cao c c bc 0.72 (500 bc mi vng).
Vi mt ng c 5
pha nh trn s quay mi bc mi vng bc, nh trnh by
di y:
u 1 + + + - - - - - + + + + + - - - - - + +
u 2 - - + + + + + - - - - - + + + + + - - u 3 + - - - - - + + + + + - - - - - + + + +
u 4 + + + + + - - - - - + + + + + - - - - u 5 - - - - + + + + + - - - - - + + + + + Hng thi gian -->
y, ging nh trong trng hp ng c hai cc, mi u hoc c ni vo
cc dng hoc cc m ca h thng cp in ng c. Ch rng, ti mi bc, ch
c mt u thay i cc. S thay i ny lm ngt in mt mu ni vo u
(bi v c hai u ca mu c cng in cc) v t in p vo mt mu ang trong
trng
thi ngh trc . Hnh dng ca ng c nh hnh 1.4, dy iu khin s iu khin
ng c quay 2 vng. phn bit ng c 5 pha vi cc loi ng c
c 5 dy dn chnh, cn nh rng, nu in tr gia 2 u lin tip ca mt ng c 5
pha l R, th in tr gia hai u khng lin tip s l 1.5R. V cng cn ghi nhn
rng mt vi ng c 5 pha c 5 mu chia, vi 10 u dy dn chnh. Nhng dy ny
c th ni thnh hnh sao nh hnh minh ho trn, s dng mch iu khin gm 5
na cu H, ni cch khc mi mu c th c iu khin bi mt vng cu H y
ca n. trnh vic tnh ton l thuyt vi cc linh kin in t, c th dng chip
mch cu tch hp y tnh ton gn ng.

================================================================================
Chng 2.
THIT K H THNG IU KHIN MOTOR BC
2.1. S khi
Vi yu cu ca ti l thit k h thng iu khin ng c bc bng
cch s dng chp vi iu khin iu khin tc ng c, em xin a ra s
khi nh sau:
Hnh 2.1. S khi h thng iu khin ng c bc

2.2. Thit k cc khi
2.2.1. B x l
B x l lm nhim v nhn tn hiu iu khin t bn ngoi nh s bc,
tc , hin th thng s trn mn hnh LCD, iu khin cho ng c quay theo
thng s nhp vo. Nh phn tch trong chng 1, y ti s dng vi iu
khin PIC16F877A. y l vi iu khin c 40 chn, vi 5 cng vo ra l Port A

================================================================================
(RA0RA5), Port B (RB0RB7), Port C (RC0RC7), Port D (RD0RD7), Port E

(RE0RE2). N c 8K Flash ROM v 368 Bytes RAM.
Hnh 2.2. S nguyn l ca PIC16F877A trong mch
2.2.2. Khi hin th

LCD_DM 1602A Hin th d dng trong vic iu khin.

================================================================================
Hnh
S dng mn hnh tinh th lng LCD (Liquid Crytal Display) loi 2 dng, 16 k
t LCD1602. Mn hnh LCD rt ph bin trn th trng v vic lp trnh cho
n rt n gin thm vo l n c mt thm m rt cao. S dng ngun nui
thp (t 2, 5 n 5V). C th hot ng hai ch 4 bit hoc 8 bit (trong ti
ny em s dng ch 4 bit).
2.2.3. Cc khi khc
iu khin ngoi: nhp cc thng s nh tc , s bc, chiu quay
cho ng c, y em s dng phm nhn nh hnh 2.5.
.
Hnh 2.5. S nguyn l ca tng phm nhn

================================================================================
B n nh dng: (ULN 2003) Nhm mc ch h tr dng cho Motor

bc, lun gi cho dng cp vo motor l < 500mA
Khi ngun: Cung cp ngun nui cho ton b h thng.
S khi b ngun
Dng IC 7805 to ngun +5V n nh cp ton mch cho mch. T C2 v C3
lc nhiu, diode D3 c nhim v bo ngun. S nguyn l nh hnh di:
Hnh S nguyn l ngun nui ca mch

2.2.4. Motor bc
Motor bc l i tng iu khin, y em s dng loi motor lng
cc, c gc quay l 1.8 mi bc.

================================================================================
2.3. S mch h thng iu khin Motor bc

2.3.1. S mch nguyn l
S h thng iu khin nh trong hnh 2.6. Cc thng s nh tc , s

bc, chiu quay c nhp vo t cc phm bm, a vo b x l (vi iu
khin PIC 16F877A) qua Port B. Da vo cc thng s ny b iu khin thc
hin hin th trn mn hnh LCD qua cc chn RC0-RC5, ng thi xut d liu
iu khin motor qua cc chn RD4-RD7, d liu iu khin ny thng qua
ULN2003 iu khin motor quay theo thng s nhp vo.
LCD1
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
7
8
9
10
11
12
13
14
RS
RW
E
6 4
5
5 6
1
2
3
VSS
VDD
VEE
LM016L
U1
13
14
2
3
4
5
6
7
8
9
10
1
OSC1/CLKIN
OSC2/CLKOUT
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RC0/T1OSO/T1CKI
RE0/AN5/RD
RC1/T1OSI/CCP2
RE1/AN6/WR
RC2/CCP1
RE2/AN7/CS
RC3/SCK/SCL
RC4/SDI/SDA
MCLR/Vpp/THV
RC5/SDO
RC6/TX/CK
RC7/RX/DT
R1
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
1k
33
34
35
36
37
38
39
40
15 1
16 2
17 3
18 4
23 5
24 6
25
26
19
20
21
22
27
28
29
30
PIC16F877A
+88.8
R8
1k
R9
1k
Hnh 2.6.
2.3.2. S mch in

================================================================================

================================================================================
Chng 3.
LU THUT TON & LP TRNH
3.1. Lu thut ton

================================================================================
3.2 PHN MM
#include <16F877A.h>
#include <math.h>
#FUSES NOWDT, HS, NOPUT, NOPROTECT, NODEBUG, NOBROWNOUT,
NOLVP, NOCPD, NOWRT
#use delay(clock=4000000)
int32 i,n,x,y,z,h,m,k;
int32 l,integral,a;
void dkthuan();
void dknguoc();
void stat();
void TANG_GIAM();
void stop();
void lua_chon();
void main()
{ x=0;h=0; m=0;
y=0;n=0; z=0;
LCD_init();
LCD_putcmd(0x01);
printf(lcd_putchar,"Dieu khien: ");
LCD_putcmd(0xC0);
printf(LCD_putchar,"MOTOR BUOC");
delay_ms(5000);

================================================================================
LCD_putcmd(0x01);
LCD_putcmd(0x80);
printf(LCD_putchar,"toc do:");
LCD_putcmd(0x88);
LCD_putchar(h +0x30);
LCD_putcmd(0x89);
LCD_putchar(k +0x30);
LCD_putcmd(0x8A);
LCD_putchar(m +0x30);
LCD_putcmd(0x8D);
printf(LCD_putchar,"V/P");
LCD_putcmd(0xC0);
printf(LCD_putchar,"so buoc:");
LCD_putcmd(0xC8);
LCD_putchar(x +0x30);
LCD_putcmd(0xC9);
LCD_putchar(y +0x30);
LCD_putcmd(0xCA);
LCD_putchar(z +0x30);
LCD_putcmd(0xCD);
printf(LCD_putchar,"B");
while(true)
{
//stop();

================================================================================
TANG_GIAM();
stat();
}
}
//=======//========//======//=====//===========================
Void TANG_GIAM()
{
If(input(pin_b4))
{x=x+1;
delay_ms(100);
if(x>=10)
{x=0;
LCD_putcmd(0xC8);
LCD_putchar(x +0x30);}
else
{LCD_putcmd(0xC8);
LCD_putchar(x +0x30);}
}
If(input(pin_b3))
{y=y+1;
delay_ms(100);
if(y>=10)
{y=0;
LCD_putcmd(0xC9);
LCD_putchar(y +0x30);}

================================================================================
else
{
LCD_putcmd(0xC9);
LCD_putchar(y +0x30);}
}
If(input(pin_b2))
{z=z+1;
delay_ms(100);
if(z>=10)
{z=0;
LCD_putcmd(0xCA);
LCD_putchar(z +0x30);}
else
{
LCD_putcmd(0xCA);
LCD_putchar(z +0x30);}
}
If(input(pin_b5))
{h=h+1;
delay_ms(100);
if(h>=10)
{h=0;
LCD_putcmd(0x88);
LCD_putchar(h +0x30);}

================================================================================
else
{LCD_putcmd(0x88);
LCD_putchar(h +0x30);}
}
If(input(pin_b6))
{k=k+1;
delay_ms(100);
if(k>=10)
{k=0;
LCD_putcmd(0x89);
LCD_putchar(k +0x30);}
else
{
LCD_putcmd(0x89);
LCD_putchar(k +0x30);}
}
If(input(pin_b7))
{m=m+1;
delay_ms(100);
if(m>=10)
{m=0;
LCD_putcmd(0x8A);
LCD_putchar(m +0x30);}
else
{

================================================================================
LCD_putcmd(0x8A);
LCD_putchar(m +0x30);}
}
}
void stat()
{
If(input(pin_b1))
{
dkthuan();
}
If(input(pin_b0))
{
dknguoc();
}
}
void stop()
{ output_d(0);
delay_ms(100);
}
void dknguoc()

================================================================================
{n=x*100+y*10+z;l=h*100+k*10+m;a=600/l;
for (i=0;i<=n;(++i))
{
output_d(0x80);
delay_ms(a);
output_d(0x40);
delay_ms(a);
output_d(0x20);
delay_ms(a);
output_d(0x10);
delay_ms(a);
}
}
void dkthuan()
{n=x*100+y*10+z;l=h*100+k*10+m;a=600/l;
for (i=0;i<=n;++i)
{
output_d(0x10);
delay_ms(a);
output_d(0x20);

================================================================================
delay_ms(a);
output_d(0x40);
delay_ms(a);
output_d(0x80);
delay_ms(a);
}
}

================================================================================
Ti liu tham kho
1. Nguyn Tng C-ng, Phan Quc Thng, Cu trc v lp trnh h Vi

iu khin 8051, Nh xut bn khoa hc v K Thut.
2 Nguyn Mnh Giang, Cu trc, lp trnh ghp ni v ng dng ca Vi
iu Khin, nh xut bn Lao ng X Hi.
3. Phm Minh H(2004), K thut mch in t, Nh xut bn Khoa hc
v k thut.
4. Ng Din Tp, Vi iu Khin trong o l-ng v iu khin t ng,
Nh xut bn Khoa Hoc v K Thut, H Ni.
5. H Vi iu Khin 8051, Tng Vn ON, nh Xut bn Lao ng v X
Hi.
6. Cc bn c th truy cp cc trang Web rt hay ca Vit Nam nh- :
www.dientuvietnam.net
www.picvietnam.com
www.dientuvienthong.net
www.vagam.dieukhien.net
www.duyphi.phpnet.us/index.htm

================================================================================
DIP
Pin#
Pin Name
RA0/AN0
PLCC
Pin#
RA1/AN1
QFT
Pin#
I/O/P
Type
19
Buffer
Type
I/O
20
TTL
21
RA3/AN3/VREF +
22
I/O
TTL
RA4/T0CKI
23
I/O
ST
RA5/ SS /AN4
24
I/O
TTL
Pin Name
DIP
Pin#
PLCC
Pin#
QFT
Pin#
I/O/P
Type
RA1 c th lm ng vo
tung t th 1
TTL
I/O
RA2/AN2/VREF
PORTA l port vo ra hai

chiu. RA0 c th lm ng
vo tung t th 0.
TTL
I/O
Buffer
Type
Description
RA2 c th lm ng vo
tung t 2 hoc in p
chun tng t m.
RA3 c th lm ng vo
tung t 3 hoc in p
chun tng t dng.
RA4 c th lm ng vo
xung clock cho b nh
thi Timer0.
RA5 c th lm ng vo
tng t th 4
Description
PORTB l port hai chiu.
RB0/INT
33
36
I/O
TTL/ST(1)
RB1
34
37
I/O
TTL
RB0 c th lm chn ngt ngo

================================================================================
RB2
35
38
10
I/O
TTL
RB3 c th lm ng vo ca
in th c lp trnh mc
thp.
RB3/PGM
36
39
11
I/O
TTL
RB4
37
41
14
I/O
TTL
Interrupt-on-change pin.
RB5
38
42
15
I/O
TTL
Interrupt-on-change pin.
RB6/PGC
39
43
16
I/O
TTL/ST(2)
Interrupt-on-change pin hoc

In-Crcuit Debugger pin .
Serial programming clock.
RB7/PGD
40
44
17
I/O
TTL/ST(3)
Interrupt-on-change pin hoc

In-Crcuit Debugger pin .
Serial programming data .
Pin Name
DIP
Pin#
PLCC
Pin#
QFT
Pin#
I/O/P
Type
Buffer
Type
Description
PORTC l port vo ra hai chiu.
RC0/T1OSO/T1CKI
15
16
32
I/O
ST
RC0 c th l ng vo ca b dao
ng Timer1 hoc ng xung clock
cho Timer1
RC1/T1OSI/CCP2
16
18
35
I/O
ST
RC1 c th l ng vo ca b dao
ng Timer1 hoc ng vo
Capture2/ng ra compare2/ng vo
PWM2.
RC2 c th ng vo capture1/ng ra
compare1/ng vo PWM1

================================================================================
RC2/CCP1
17
19
36
I/O
ST
RC3/SCK/SCL
18
20
37
I/O
ST
RC3 c th l ng vo xung
RC4/SDI/SDA
23
25
42
I/O
ST
Clock ng b ni tip/ng ra trong

c hai ch SPI v I2C
RC4 c th l d liu bn trong
SPI(ch SPI) hoc d liu
I/O(ch I 2 C).
RC5/SDO
RC6/TX/CK
RC7/RX/DT
24
26
43
I/O
ST
25
27
44
I/O
ST
26
29
I/O
ST
RC5 c th l d liu ngoi SPI(ch

SPI)
RC6 c th l chn truyn khng

ng b USART hoc ng b vi
xung ng h
RC7 c th l chn nhn khng

ng b USART hoc ng b vi
d liu.
DIP
Pin#
PLCC
Pin#
QFT
Pin#
I/O/P
Type
Buffer
Type
RD0/PSP0
19
21
38
I/O
ST/TTL(3)
RD1/PSP1
20
22
39
I/O
ST/TTL(3)
RD2/PSP2
21
23
40
I/O
ST/TTL(3)
RD3/PSP3
22
24
41
I/O
ST/TTL(3)
RD4/PSP4
27
30
I/O
ST/TTL(3)
RD5/PSP5
28
31
I/O
ST/TTL(3)
RD6/PSP6
29
32
I/O
ST/TTL(3)
Pin Name
Description
PORTD l port vo ra hai
chiu hoc l parallel slave
port khi giao tip vi bus
ca b vi x l.

================================================================================
RD7/PSP7
Pin Name
RE0/ RD /AN5
30
33
I/O
ST/TTL(3)
DIP
Pin#
PLCC
Pin#
QFT
Pin#
I/O/P
Type
Buffer
Type
25
I/O
ST/TTL(3)
Description
PORTE l port vo ra hai
chiu.
RE0 c th iu khin vic
c parrallel slave port
hoc l ngoc vo tng t
th 5.
RE1/ WR /AN6
10
26
I/O
ST/TTL(3)
RE2/ CS /AN7
10
11
27
I/O
ST/TTL(3)

ghi parallel slave port hoc
l ng vo tng t th 6.

chn parallel slave port
hoc l ng vo tng t
th 7

================================================================================

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B GIO DC V O TO

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

*) C sn cc cng c pht trin phn mm nh cc trnh bin dch, trnh

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

Hnh 1.1. PIC 16F877A

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

Hnh 2. S khi ca PIC16F877A

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

Bng m t chc nng cc chn ca PIC16F877A

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

PORTB l port hai

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

Cung cp ngun dng

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

Nhng chn ny khng

Ghi ch: I = input; O = output; I/O = input/output; P = power

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

Hnh 3. Ngn xp v bn b nh chng trnh PIC16F877A

1.1.2.1. T chc ca b nh chng trnh

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

1.1.2.2. T chc b nh d liu

Chiu di ca mi dy l 7Fh (128 byte). Phn thp ca mi dy dng

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

Hnh 4. Cc thanh ghi ca PIC16F877A

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

1.1.2.4. Cc thanh ghi chc nng c bit

Hnh 5. Thanh ghi trng thi (a ch 03h, 83h, 103h, 183h)

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

1.1.3. Cc cng ca PIC 16F877A

Hnh 6. S khi ca chn RA3:RA0 v RA5

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

Hnh 7. S khi ca chn RA4/T0CKI

1.1.3.2. PORTB v thanh ghi TRISB

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

Hnh 8. S khi cc chn RB3:RB0

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

Hnh 9. S khi cc chn RB7:RB4

1.1.3.3. PORTC v thanh ghi TRISC

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

3 v 4 ca PORTC c th cu hnh vi mc I2C bnh thng, hoc vi mc

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

Hnh 10. S khi ca cc chn RC<4:3>

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

Hnh 11. S khi ca cc chn RC<2:0> v RC<7:5>

1.1.3.4. PORTD v thanh ghi TRISD

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

PORTD l port 8 bit vi m Trigger Schmitt ng vo. Mi chn c th

Hnh 12. S khi ca PORTD (trong ch l port I/O)

1.1.3.5. PORTE v thanh ghi TRISE

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

nh nhng ng vo s. Cng bo m rng ADCON1 c cu hnh cho vo ra

Hnh 13. S khi ca PORTE (trong ch I/O port)

1.1.4. Hot ng cu nh thi

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

Hnh 14. S khi ca b nh thi Timer0 v b chia dng chung vi WDT

Ch nh thi (Timer) c chn bng cch xo bit T0CS

KHOA IN T VIN THNG - TRNG I HC DN LP HI PHNG

sau mi chu k lnh (khng c b chia). Nu thanh ghi TmR0 c ghi th s