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PHILIPS TECHNICAL TRAINING
PLASMA PANEL REPAIR
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ADDRESS ELECTRODES
BARRIER RIBS
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DISPLAY ELECTRODES
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FRONT GLASS PLATE
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NEON XENON GAS
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CHARGE / DISCHARGE CYCLE
Uses Neon Xenon gases
A voltage is applied between the Address
Electrodes and display electrodes to stimulate
ultraviolet radiation UV
UV stimulation causes color phosphors to glow
These form picture elements
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PANEL Module Introduction PANEL Module Introduction
4. BLOCK DIAGRAM
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SDI BUILT PANELS IN PHILIPS SETS ARE THE
ONLY PANELS FEATURED IN THIS TRAINING
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PDP model name,
with or without PSU
10 1 3 03 26 0577
Type: 02 - 48
Line No: 1 -9
Year
Month: 01 - 12
Date: 01 - 31
Serial No: 0001 - 9999
Serial No
101303260577
Power supply
settings
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PDP LABEL
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42 INCH V4 PANEL USED IN BP SET WITH SSB REMOVED
Y DRIVER POWER SUPPLY
X-DRIVER LOGIC BOARD
E BOARDS
Y BUFFERS
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50HDV3
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50HDV4
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Panel Location FM242 / FTP1.1 YD06 / YB04 Panels
42 INCH SDV2 MODULE LAYOUT
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Panel module label Voltage label Serial No.
1 Logic Main
2 X-main
3 Y-main
8 Logic-buffer G
9 FFC Logic + Y-main
10 FFC Logic + X-main
4 Y-buffer upper
5 Y-buffer low
6 Logic-buffer E
7 Logic-buffer F
11 Logic + Logic buffer
12 Logic + Logic buffer
13 Logic + Logic buffer
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2
3
4
5
6 7 8
9
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11 12 13
PSU
SUB-
PSU
42 INCH SDV3 MODULE LAYOUT
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SubL
PSU
Y-main Board
X-main board
Logic-buffer (E) Logic-buffer (F) Logic-buffer (G
Logic-buffer (H) Logic-buffer (I) Logic-buffer (J)
Y
-
b
u
f
f
e
r

u
p
Y
-
b
u
f
f
e
r

d
o
w
n
Logic-main board
SUB PSU
SubR
TCPs
50 INCH HD V3 MODULE LAYOUT
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PICTURE OF 50 HD V3
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.SMPS(Switching Mode Power Supply) : Supplies voltage and current to operate assemblies mounted to
each board and Panel.
.X Main Board : According to the timing provided from Logic board, switches FETs and generates driving
waveform which is provided to X electrode of Panel through Connector.
.Y Main Board :
According to the timing provided from Logic board, switches FETs and generate driving waveform which is
provided to Y electrode of Panel sequentially through Scan Driver IC of Scan Buffer.
.Logic Main Board : Processes image signal and generates Address driving output signal & XY driving
signal
.Logic Buffer Board(E,F,G) (+ Logic Buffer H, I, J if HD Display)
Transfers data signal and control signal to COF.
.Scan Buffer(Upper,Lower) : A board allows scan waveform to Y terminal, which is consisted of Upper
Board and Lower Board.
(Y-Buffer(Upper,Lower) )
.AC Noise Filter : Blocks noise and spikes and noise on the AC line.
.COF(Chip on Flexible) or (TCP Tape Carrier Package) : It allows Va pulse to address electrode within
address period and forms address discharge according to the electric potential difference between Va pulse
and the Scan pulse allowed to Y electrode. It is manufactured in COF form and one COF is consisted of four
DATA Drive IC .
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TCP DRIVER
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V2
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PANEL DEFECTS
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Defect : panel damage
Symptom : Panel crack or break. No image
appears in some cause depending on the
damaged parts and damage level.
Defect: Exhaust pipe damage
Symptom. : Crack in break if exhaust pipe an
image is partially lacking or the panel noise
occurs depending on the damaged parts and
after a certain time.
Or very loud noise from the panel.
Cause
Manufacturing : Flatness/palette pin
interruption
Operation : overload of panel corner /
careless handling
Panel : Flatness / assembly error
Cause : Carelessly panel handling
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Check exhaust Tip for Cracks with naked eyes to check vacuum state.
If there is problem then replace the module by new one .
In case of vacuum breakdown, module makes a shaking noise because of inside gas ventilation.
(there may be a small crack which could not see with naked eyes. And this noise is different from Capacitor noise. )
1.2 Exhaust tip Crack
CRACKED NORMAL
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Logic Main, Logic Buffer,
FFC, TCP
Some vertical lines appear to be
linked on Display
Address Short
Logic Main. Logic Buffer,
FFC, TCP
Some vertical lines dont exist on
the Display.
Address Open
Scan Buffer, FPC of X / Y Some horizontal lines appear to be
linked on Display.
Sustain Short
Scan Buffer, FPC of X / Y Some horizontal lines dont exist
on the Display
Sustain open
Y-Main, X-Main, Logic
Main
Abnormal Image (not open or
short) is on Display
Abnormal
Display
Y-Main, X-Main, Logic
Main, connections
Operating voltages exist, but no
Display
No Display
PSU Operating Voltages dont exist No voltage output
Related Board Description Symptom
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Vertical stripe = Address open Vertical stripe = Address Short
Defect: Address output error
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Defect horizontal stripe: Sustain Open Defect horizontal stripe: Sustain Short
Symptom : One or more line do not
light up in Sustain direction
Symptom : Combined or adjacent lines
are short in sustain direction. The line
appear brighter than other at Ramp
gradation pattern or low gradation patter
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Address and Sustain Open Address Block and Line Open
Defect: Dielectric material layer damage
Symptom:
Phosphor damage caused by the damage of address bus dielectric layer
appears in the panel discharge/non discharge area. sustain also open/short
occurs by the damage of address sustain printout
Cause : layer uneven / abnormal voltage / foreign material repair failed.
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Defect: Full White low discharge . Defect: Weak discharge
Symptom : Low discharge caused by unstable cells
occurring at full white pattern if high (60 degree) or
normal temperature.
Symptom : Normal discharge but cells appear
darker due to weak light emission occurring
mainly at low (5 degree) Full White/ Red/
Green/ Blue pattern or gradation pattern
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DEFECTIVE TCP
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DISASSEMBLY TIPS
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CONNECTOR BETWEEN Y
UPPER AND LOWER ON
42HDV4 PANEL
42HDV4 PANEL
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Removal
Pull out the FPC from connector by holding
the lead of the FPC with hands
Assembling
Push the lead of FPC with same strength until to be connected
completely.
Be careful do not damage the connector pin during connecting
DISASSEMBLY OF THE Y BUFFER
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Disassembling
Pull out the connector clamp Pull Flat cable out press down lightly Move away from connector
Assembling
Put the Flat cable into the connector press down lightly until locking click
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X BOARD CONNECTION
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PRESS ON THE RIBBON CONNECTOR TO ENSURE
THAT IT IS PROPERLY SEATED
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1 2 3 4 5 6 7
1) Remove the screws in order of 2-3-5-6-7-1-4 from
heat sink and then get rid of heat sink.
2) Remove the TPC, FFC and power cable from the
connectors.
3) Remove all of the screws from defected board.
4) Remove the defected board.
5) Replace the new board and then screw tightly.
6) Get rid of the foreign material from the connector.
7) Connect the TCP,FFC and power cable to the
connector.
8) Reassemble the TCP heat sink.
9) Screw in order of 4-1-7-6-5-3-2.
If you screw too tightly, it is possible to get damage
on the Driver IC of TCP.
Be care when using electric Screwdriver!
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42HDV3 SCREW REMOVAL AND REPLACEMENT
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Disassembling of TCP
Assembling of TCP
Open the clamp carefully Lift the TCP out from connector
Put the TCP into the connector carefully and check alignment Close the clamp completely, until locking click
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TCP DRIVER
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TROUBLESHOOTING
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FIRST DETERMINE IF THE PROBLEM IS THE
THE SMALL SIGNAL BOARD OR THE PDP
PANEL PROBLEM
OPERATE PANEL IN INTERNAL (STAND ALONE)
CHECK POWER SUPPLY VOLTAGES
CHECK Y-BUFFER AND X-BOARD OUTPUTS
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Trouble Shooting on No Display and Abnormal Display 42SDV2
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SCOPE WITH DUAL TIME BASE DELAYED SWEEP REQUIRED
HIGH FREQUENCY REJ ECTION SWITCH MAY BE NEEDED TO
TRIGGER ON THE V-SYNC
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V2 PANEL IN SERVICE POSITION WITH SSB/SCAVIO REMOVED
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SHORT PINS 1 AND 2 OF CN8002
SHORT PIN 11(STANDBY) TO
GROUND TO SWITCH THE SET ON
OR
USE TEST JIG 3122 785 90760
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V2
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SHORT J8002 TO SWITCH
THE POWER SUPPLY VA
AND VS SUPPLIES.
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V2
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TP 13 V-SYNC
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This test point location may change with a different logic board.
V-SYNC IS NECESSARY TO TRIGGER THE SCOPE
THE SCOPE MAY NOT TRIGGER WITHOUT A
HF REJ ECTION SWITCH
V2
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V3
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WITHOUT ADAPTER
CONNECT PIN 9 CN9005 TO PIN10 CN9004
CONNECT PIN 4 TO PIN 7 OF CN9005
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1. Check Input Voltage Range of the defect
occurrence area is between 100V AC ~ 240V AC
2. Insert Jumper at J8003, J8004 BJ8902
3. Insert Power (AC) at CN8001
4. Check if the LED turn on or not as sequence.
(LED8001LED8002BD8903)
5. If all the LEDs (LED8001, LED8002, BD8903)
are ON, the PSU is not defective.
6. If one of the LEDs (LED8001, LED8002,
BD8903) is OFF, the PSU is defective.
CN8001
J8003
J8004
Right Position
BJ8902
LED8002
BD8903
LED8001
Protection & LED indication for Fault Finding
CHECKING THE V4 POWER SUPPLY UNLOADED
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BJ 8902
BJ 8901
Alarm led
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PSU troubleshoot
As verification, this is possible to disable
protection: by puting jumper BJ 8901 (on alarm
board)
This disables the protection circuits so that the
power supply operation can be checked
Caution: in this case there is a risk of more damages
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V4
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BJ 8902
SWITCHES ON THE VS SUPPLY WHEN THE LOGIC BOARD IS
NOT CONNECTED
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Error codes can be read by counting the blinking rate of BD8903 LED located on the Alarm board.
BD8903
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V4
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13 TIMES D5VL OVP, UVP
4 TIMES D3V3 OVP, UVP
3 TIMES VSCAN OVP, UVP
2 TIMES 12V OVP, UVP
11 TIMES 5V2 OVP or Active DC_PROT
10 TIMES PFC_OK UVP (>330V)
9 TIMES Over Temperature (<105)
8 TIMES VE OVP, UVP
7 TIMES VSET OVP, UVP
6 TIMES VG OVP, UVP
5 TIMES VS OVP, UVP
1 TIME VA OVP, UVP
LED Signature Detect Error condition
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V4
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DC VOLTAGES AND CURRENTS 42SDV4 ONLY
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V4
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PLACE J UMPER HERE ON THE LOGIC BOARD TO
TURN THE SCREEN WHITE
V4
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TEST WAVEFORMS
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V Sync on Channel A CN201 2ms/Div/2V 5
6 Y Output on Out 4 100V/Div
X-Output TP Out 7
By use of Delayed Time Base
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SCOPE SETTINGS 42SDV2
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UPPER PULSE IS SYNC
LOWER IS OUTPUT OF Y
BUFFER
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42SDV2
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Y-BUFFER
X-BOARD
42HDV4 Y BUFFER USING x100 PROBE
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ALIGNMENTS
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NO ALIGNMENTS ARE NECESSARY WHEN REPLACING
THE FOLLOWING PANELS
X-BOARD
Y-BUFFER BOARDS
LOGIC BOARD
LOGIC DRIVER BOARDS (E)
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POWER SUPPLY
THE POWER SUPPLY SHOULD BE CHECKED AND
ADJ USTED IF NECESSARY ACCORDING TO THE CHART
LOCATED ON THE PLASMA PANEL
EACH POWER SUPPLY IS SET TO OPTIMIZE EACH PANEL
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VOLTAGE CHART
LOCATED IN THE UPPER RIGHT HAND CORNER
VIEW FROM THE BACK OF THE SET
SOME PANELS HAVE A DIFFERENT LOCATION
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POWER BOARD ALIGNMENTS 42SDV4
SUB POWER BOARD
D3V3 VR9005 CHECK CHART
D6V VR9004 CHECK CHART
MAIN POWER BOARD
VSCAN VR8005 CHECK CHART
VSET VR8003 CHECK CHART
D3V3 VR8006 CHECK CHART
VSB VR8002 CHECK CHART
VE VR8008 CHECK CHART
VS VR8004 CHECK CHART
PFC VR8001 DO NOT ADJ UST
VA VR8007 CHECK CHART
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After changing PSU, Check and
Adjust the
voltage of 8 points.
If turn right, voltage up
If turn left, voltage down
1.VS
2.VA
3.VSET
4.VSCAN
5.VE
6.D3V3
7.D5V
8.12VL
VSCAN
VE
Voltage
Up
VSET
VS
VA
12V
D5VL D3V3
Voltage
Down
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V4
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CONDITION CAUSED BY MISADJ USTED POWER SUPPLY
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Y-DRIVER BOARD
THE Y-DRIVER ADJ USTMENTS SHOULD BE CHECKED
AND ADJ USTED IF NECESSARY TO OPTIMIZE PICTURE
PERFORMANCE
A DUAL TIME BASE OSCILLOSCOPE IS REQUIRED TO
MAKE ACCURATE ADJ USTMENTS
TO OBTAIN A STABLE WAVEFORM, SYNC THE
SCOPE TO THE V-SYNC ON THE LOGIC PANEL
THE Y-DRIVER MAY HAVE CHANGED IN PRODUCTION
MATCH THE PICTURE OF YOURS WITH THE ONE IN
THE SERVICE MANUAL TO VERIFY THAT THE
CORRECT ADJ USTMENTS ARE BEING PERFORMED
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HIGHLIGHT THE WAVEFORM TO EXPAND
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THE PREVIOUS EXAMPLE IS A WAVEFORM VIEWED
WITH A TEKTRONIX
OSCILLOSCOPE
EACH OSCILLOSCOPE WORKS A LITTLE
DIFFERENT
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1) Make Full White on Screen.
2) Observe waveform using Oscilloscope.
check OUT4 TP in Y-buffer(upper).
Observe the waveform of the third waveform of 1TV-
Field.
Adjust the division of oscilloscope like the left picture
Adjust the period of Vset as 10S,
that of -Vsc(1) as 20s,
that of -Vsc(2) as 5s,
turning VR (Variable Resistor)
(only,when you adjust each period of -Vsc(1) & -Vsc(2)
adjust Vertical Division of oscilloscope as '2V or 5V')
VR for Vset : VR5003 (Y_main)
VR for -Vsc(1) : VR5001 (Y_main)
VR for -Vsc(2) : VR5002 (Y_main)
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42SDV2
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VR5002
Raising Ramp Flat Time
VR5003
Falling Ramp Flat Time
VR5004
VSCH
V Scan High
VR5001
3th Falling Ramp Flat Time
Y test point
V-Sync test point
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1. VR5004 Adjustment : Vsch TP => 40volt
2. VR5002 Adjustment : Rising Ramp flat time: Typ. 10usec
4. VR5001 Adjustment : 3th SF Falling Ramp flat time => Typ. 30usec
3. VR5003 Adjustment : Falling Ramp flat time => Typ. 30usec
TP:Vsch
VR5004
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42SDV3
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10 VR5001 Falling_Ramp_3rd
20 VR5003 Falling_Ramp_1st
10 VR5002 Rising_Ramp 42HDV3
10 (10 ~ 15) Falling_Ramp_3rd
10 (10 ~ 15) Falling_Ramp_1st
30 (30 ~ 40) Rising_Ramp 37SDV4
30 VR5001 Falling_Ramp_3rd
30 VR5003 Falling_Ramp_1st
10 VR5002 Rising_Ramp 42SDV3
20 Falling_Ramp_3rd
35 Falling_Ramp_1st
50 Rising_Ramp 50HDV3
Default Adjusting Location No Wave Form
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PLACE J UMPER HERE ON THE LOGIC BOARD TO
TURN THE SCREEN WHITE
VSYNC
OR VTOGG
GND
42HDV4
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Y DRIVE TEST POINT
42HDV4
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42HDV4
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15V
RISING ADJ
X100 PROBE USED
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50uS
100V
VR5002 FALLING ADJ
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REFER TO THE PDP REPAIR MANUAL FOR ALL ADJ USTMENTS
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WHEN REPLACING THE SSB, BE SURE TO
SET THE SCREEN NUMBER AND TYPE
THESE SHOULD BE LISTED IN THE SCREEN
SERVICE MANUAL
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SCREEN DIVERSITY
WHEN CHANGING THE SSB, IT IS IMPORTANT TO
PROGRAM THE SCREEN DIVERSITY CODE AS SHOWN
ON THE OPTION CODE LABEL.
IF THE WRONG CODE HAS BEEN ENTERED CAUSING
THE SCREEN TO BE BLANK, THE DIVERSITY CODE
CAN BE RESET BY ENTERING 0 6 2 5 9 8 MENU FOLLOWED
BY THE CORRECT CODE.
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