Chapter 1: Introduction To PIC18

The PIC18 Microcontroller
Chapter 1: Introduction to PIC18

Han-Way Huang
Minnesota State University Mankato Minnesota State University, Mankato
H. Huang Transparency No.1-1
Copyright @ 2005 Thomson Delmar Learning
What is a computer?
Software
Hardware Hardware
Computer Hardware Organization
Processor
Control Uni t
Common Bus (address, data, & control )
Datapath
Arithmeti c
Logi c Uni t
Memory
Regi sters
Program
Storage
Data
Storage
Output
Uni ts
Input
Uni ts
Fi gure 1.1 Computer Organizati on
Th The processor
Registers -- storage locations in the processor
Arithmeticlogicunit Arithmetic logic unit
Control unit
program counter contains the address of the next instruction to be executed p g
status register flags the instruction execution result
The microprocessor
A processor implemented on a very large scale integration (VLSI) chip
Peripheral chips are needed to construct a product
The Microcontroller
The processor and peripheral functions implemented on one VLSI chip
Features of the PIC18 microcontroller Features of the PIC18 microcontroller
- 8-bit CPU
- 2 MB program memory space
- 256 bytes to 1KB of data EEPROM
- Up to 3968 bytes of on-chip SRAM
- 4 KB to 128KB flash program memory
- Sophisticated timer functions that include: input capture, output compare,
PWM, real-time interrupt, and watchdog timer
- Serial communicationinterfaces: SCI SPI I2C andCAN Serial communication interfaces: SCI, SPI, I2C, and CAN
- Background debug mode (BDM)
- 10-bit A/D converter
M t ti bilit - Memory protection capability
- Instruction pipelining
- Operates at up to 40 MHz crystal oscillator
Embedded Systems Embedded Systems
- A product that uses one or more microcontrollers as controller (s).
- End users are only interested in the functionality of the product but not on
the microcontroller itself.
- Cell phones, home security system, automobiles, and many other products
are examples of embedded products.
Semiconductor memoryy
Random-access memory (RAM): same amount of time is required to access
any location on the same chip
R d l (ROM) l b db t t itt t b th Read-only memory (ROM): can only be read but not written to by the
processor
Random-access memory
Dynamic random-access memory (DRAM): need periodic refresh
Static random-access memory (SRAM): no periodic refresh is required
Read-only memory
Mask-programmed read-only memory (MROM): programmedwhenbeing Mask programmed read only memory (MROM): programmed when being
manufactured
Programmable read-only memory (PROM): can be programmed by the end
user
Erasable programmable ROM(EPROM) Erasable programmable ROM (EPROM)
1. electrically programmable many times
2. erased by ultraviolet light (through a window)
3 bl i b lk( h l hi i ti ) 3. erasable in bulk (whole chip in one erasure operation)
Electrically erasable programmable ROM (EEPROM)
2. electrically erasable many times
3. can be erased one location, one row, or whole chip in one operation
Flash memory
2. electrically erasable many times
3. can only be erased in bulk (either a block or the whole chip)
Computer software
- Computer programs are known as software
- A program is a sequence of instructions
Machine instruction
- A sequence of binary digits which can be executed by the processor
d d d dd b f h b i - Hard to understand, program, and debug for human being
Assembly language
- Defined by assembly instructions
- An assembly instruction is a mnemonic representation of a machine
instruction
A bl t b t l t db f it b t d - Assembly programs must be translated before it can be executed --
translated by an assembler
- Programmers need to work on the program logic at a very low level and cant
achieve high productivity.
g p y
High-level language High-level language
- Syntax of a high-level language is similar to English
- A translator is required to translate the program written in a
high-level language -- done by a compiler
- Allows the user to work on the program logic at higher level.
Source code Source code
- A program written in assembly or high-level language
Object code
- The output of an assembler or compiler
Source code and object code examples
address object code line no. Source code j
----------------------------------------------------------------------------------------------
00001E 0E06 00010 movlw 0x06
000020 6E11 00011 movwf 0x11,A ,
000022 0E07 00012 movlw 0x07
000024 6E12 00013 movwf 0x12,A
000026 0E08 00014 movlw 0x08 0000 6 0 08 000 ov w 0 08
000028 6E13 00015 movwf 0x13,A
00002A 0E05 00016 movlw 0x05
00002C 5E10 00017 subwf 0x10,F,A 00002C 5E10 00017 subwf 0x10,F,A
00002E 5E11 00018 subwf x11,F,A
Radix Specification p
- Hexadecimal (or hex) number is specified by adding the prefix 0x or by
enclosing the number with single quotes and preceding it by an H.
0x02 0x1234 H`2040 arehexnumbers - 0x02, 0x1234, H 2040 are hex numbers
- Decimal numbers are enclosed by single quotes and preceded by letter D.
- D`10 and D`123 are decimal numbers
- Octal and binary numbers are similarly specified.
- O`234 is an octal number; B01011100 is a binary number.
Memory Addressing
- Memory consists of a sequence of directly addressable locations.
A l i i f d i f i i - A location is referred to as an information unit.
- A memory location can be used to store data, instruction, and the status of
peripheral devices.
- A memory location has two components: an address and its contents. y p
Address Contents
Figure 1.2 The components of a memory location
The PIC18 Memory Organization
- DataMemoryandProgramMemoryareseparated Data Memory and Program Memory are separated
- Separation of data memory and program memory makes possible the
simultaneous access of data and instruction.
- Data memory are used as general-purpose registers or special function registers
- On-chip Data EEPROM are provided in some PIC18 MCUs p p
Separation of Data Memory and Program Memory
Inside the c chip
Program
Memory
Space
Data
Memory
21-bit progamaddress 12-bit register address
Space
(a portion
of this
space is on
th
PIC18
CPU
Space
(Special
function
registers and
l the c
chip)
general
purpose
RAM)
16-bit instruction bus
8-bit data bus
Figure 1.3 The PIC18 memory spaces
PIC18 Data Memory
- Implemented in SRAM and consists of general-purpose registers and
special-function registers. Both are referred to as data registers.
- A PIC18 MCU may have up to 4096 bytes of data memory. C 8 CU ay aveupto 096byteso data e o y.
- Data memory is divided into banks. Each bank has 256 bytes.
- General-purpose registers are used to hold dynamic data.
- Special-function registers are used to control the operation of peripheral
functions.
- Only one bank is active at any time. The active bank is specified by the BSR
register register.
- Bank switching is an overhead and can be error-prone
- PIC18 implements the access bank to reduce the problem caused by bank
switching.
- Access bank consists of the lowest 96 bytes and the highest 160 bytes of the
data memory space.
Access RAM
000h
05Fh
BSR<3:0>
=0000
GPRs
05Fh
060h
0FFh
100h
1FFh
GPRs
Bank 0
Bank 1
0000
=0001
200h
2FFh
300h
GPRs
GPRs
A RAM l
000h
Access Bank
Bank 2
Bank 3
=0010
=0011
3FFh
400h
GPRs
Access RAM low
Access RAM high
SFRs
000h
05Fh
060h
0FFh
Bank 4
to
B k13
GPRs
DFFh
E00h
EFFh
Bank 13
Bank 14
=1110
Note. 1. BSR is the 4-bit bank select register.
Unused
SFRs
EFFh
F00h
F5Fh
F60h
FFFh
Bank 15
=1111
Figure 1.4 Data memory map for PIC18 devices (redraw with permission of Microchip)
Program Memory Organization Program Memory Organization
- The program counter (PC) is 21-bit long, which enables the user program to
access up to 2 MB of program memory.
- The PIC18 has a 31-entry return address stack to hold the return address for
subroutine call.
- After power-on, the PIC18 starts to execute instructions from address 0.
- The location at address 0x08 is reserved for high-priority interrupt service
routine.
- Thelocationat address0x18isreservedfor low-priorityinterrupt service The location at address 0x18 is reserved for lowpriority interrupt service
routine.
- Up to 128KB (at present time) of program memory is inside the MCU chip.
P t f th i l t d t id f th MCU hi - Part of the program memory is located outside of the MCU chip.
P C<20:0>
21
stack level 1
stack level 31
.
.
.
stack level 31
000000
h
000008h
R eset V ector
H igh P riority I nterrupt V ector
000018h
L ow P riority I nterrupt V ector
y

S
p
a
c
e
On-chip and external
yxxxxxh
U
s
e
r

M
e
m
o
r
y
program memory
1F F F F F h
U nimplemented
program memory
R ead '0'
1F F F F F h
F igure 1.5 P I C18 P rogram memory Organization (redraw with permission of
M icrochip)
N o t e . y c a n b e 0 o r 1 w he r e a s x c a n b e 0 - F
The PIC18 CPU Register The PIC18 CPU Register
- The group of registers from 0xFD8 to 0xFFF are dedicated to the general
control of MCU operation.
h i li di bl - The CPU registers are listed in Table 1.2.
- The WREG register is involved in the execution of many instructions.
- TheSTATUSregister holdsthestatusflagsfor theinstructionexecutionandis The STATUS register holds the status flags for the instruction execution and is
shown in Figure 1.6.
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The PIC18 Pipelining p g
- The PIC18 Divide most of the instruction execution into two stages: instruction
fetch and instruction execution.
Uptotwoinstructionsareoverlappedintheir execution Oneinstructionisin - Up to two instructions are overlapped in their execution. One instruction is in
fetch stage while the second instruction is in execution stage.
- Because of pipelining, each instruction appears to take one instruction cycle to
complete complete.
MOVLW 55h
fetch 1 execute 1
TCY0 TCY1
TCY2 TCY3 TCY4
TCY5
MOVWF PORTB
BRA sub_1
BSF PORTA,BIT3
fetch 2 execute 2
fetch 3 execute 3
fetch 4 flush
Instruction @address sub_1 fetch sub_1 execute
sub_1
Note: All instructions are single cycle, except for any program branches.
Figure 1.7 An example of instruction pipeline flow
Instruction Format Instruction Format
- Format for byte oriented instructions
0 7 8
9 10 15
opcode d a f
0 7 8
9 10 15
d =0 for result destination to be WREG register.
d =1 for result destination to be file register (f)
a =0 to force Access Bank
a =1 for BSR to select bank
f =8-bit file register address
Figure 1.8 Byte-oriented file register operations (redraw with permission of
Microchip)
Byte-to-byte Operations
opcode f (source file register)
0 12 15
11
0
12 15
11
1111 f (destination file register)
0
12 15
11
Figure 1.9 Byte to byte move operations (2 words) (redraw with permission of Microchip)
Bit-oriented file register operations
opcode b a f
0 7
8
11
15
12
9
b =3-bit position of bit in the file register (f).
a =0 to force Access Bank
a =1 for BSR to select bank
Figure 110 Bit oriented file register operations (redraw with permission of
Figure 1.10 Bit-oriented file register operations (redraw with permission of
Microchip)
Literal operations Literal operations
- A literal is a number to be operated on directly by the CPU
0 7
8 15
opcode k
0 7
8 15
k =8-bit immediate value
Figure 1.11 Literal operations (redraw with permission of Microchip)
Control operations
- These instructions are used to change the program execution sequence and
making subroutine calls.
opcode n<7:0>(literal)
0 7
8 15
0 7
8 15
GOTO label
1111 n<19:8>(literal)
n =20-bit immediate value
0 7
8 15
S opcode n<7:0>(literal)
1111 n<19:8>(literal)
0 7
8 15
S =fast bit
S
CALL funct_name
0 10 11
15
0 7
8 15
BRA label
Figure 1.12 Control operations (redraw with permission of Microchip)
opcode n<7:0>(literal) BC label
Access Bank Access Bank
- In Figures 1.8 to 1.12, PIC18 uses 8 bits to specify a data register (f field).
- Eight bits can specify only 256 registers.
- This limitation forces the PIC18 to divide data registers (up to 4096 bytes) into
banks.
- Only one bank is active at a time. y
- When operating on a data register in a different bank, bank switching is
needed.
Bankswitchingincursoverheadandmaycauseprogramerrors - Bank switching incurs overhead and may cause program errors.
- Access bank is created to minimize the problems of bank switching.
- Access bank consists of the lowest 96 bytes in general-purpose registers and the
highest 160 bytes of special function registers.
- When operands are in the access bank, no bank switching is needed.
Examples of the Use of Access Bank
1. addwf 0x20,F,A ; add the data register at 0x20 in access bank with WREG
; register and store the sum in 0x20.
2 subwf 0x30FBANKED; subtract thevalueof WREGfromthedataregister 2. subwf 0x30,F,BANKED ; subtract the value of WREG from the data register
; 0x30 in the bank specified by the current contents
; of the BSR register. The difference is stored in
; data register 0x30.
3 dd f 0 40WA dd h WREG i i hd i 0 40i 3. addwf 0x40,W,A ; add the WREG register with data register at 0x40 in
; access bank and leaves the sum in WREG.
PIC18 Addressing Modes
- Register direct: Use an 8-bit value to specify a data register.
movwf 0x20,A ; the value 0x20 is register direct mode
- Immediate Mode : A value in the instruction to be used as an operand
addlw 0x10 ; add hex value 0x10 to WREG
movlw 0x30 ; load 0x30 into WREG
- Inherent Mode: an implied operand
andlw 0x3C ; the operand WREG is implied
daw ; the operand WREG is implied
- Indirect Mode: A special function register (FSRx) is used as a pointer to
the actual data register.
Format Example
INDFx x=0 1 2 movwf INDF0 INDFx x 0, 1, 2 movwf INDF0
POSTINCx movff POSTINC0,PRODL
POSTDECx movf POSTDEC0,W
PREINCx addwf PREINC1,F
PLUSWx movff PLUSW2,PRODL
PIC18 Instruction Examples p
Data Movement Instruction
lfsr FSR1,0xB00 ; place the value 0xB00 in FSR1
movf PRODL,W ; copy PRODL into WREG
movff 0x100,0x300 ; copy data register 0x100 to data register 0x300
movwf PRODL,A ; copy WREG to PRODL
swapf PRODL,F ; swap the upper and lower 4 bits of PRODL
movb 3 ; load3intoBSR movb 3 ; load 3 into BSR
movlw 0x10 ; WREG 0x10
Add Instructions Add Instructions
addwf 0x20,F,A ; add data register and WREG and place sum in WREG
dd f PRODL WA ddWREG PRODL d dl addwfc PRODL,W,A ; add WREG, PRODL, and carry and leave sum
; in WREG
addlw 0x5 ; increment WREG by 5 ; y
Subtract Instructions
subfwb PRODL F ; PRODL [WREG] [PRODL] borrowflag subfwb PRODL,F ; PRODL [WREG] [PRODL] borrow flag
subwf PRODH,W ; WREG [PRODH] [WREG]
subwfb 0x10,F,A ; 0x10 [0x10] [WREG] borrow flag
sublw 0x10 ; WREG 0x10 [WREG]
RISC
CISC
RISC
Simple instruction set
R l dfi di t ti f t
Complex instruction set
Irregular instructionformat Regular and fixed instruction format
Simple address modes
Irregular instruction format
Complex address modes
Pipelined instruction execution
Separated data and program memory
May also pipeline instruction execution
Combined data and program memory
Most operations are register to register
Take shorter time to design and debug
Most operations can be register to memory
Take longer time to design and debug
Provide large number of CPU registers Provide smaller number of CPU registers

Chapter 1: Introduction To PIC18

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The PIC18 Microcontroller

Chapter 1: Introduction to PIC18

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