6.

012 Spring 2007 Lecture 12 1

Lecture 12
Digital Circuits (II)
MOS INVERTER CIRCUITS
Outline
NMOS inverter with resistor pull-up
The inverter
NMOS inverter with current-source pull-up
Complementary MOS (CMOS) inverter
Static analysis of CMOS inverter
Reading Assignment:
Howe and Sodini; Chapter 5, Section 5.4
6.012 Spring 2007 Lecture 12 2
1. NMOS inverter with resistor pull-up:
Dynamics
C
L
pull-down limited by current through transistor
[shall study this issue in detail with CMOS]
C
L
pull-up limited by resistor (t
PLH
RC
L
)
Pull-up slowest
V
IN
:
LO HI
V
IN
:
HI LO
V
OUT
:
HI LO
V
OUT
:
LO HI
V
DD
C
L
R
V
DD
C
L
R
pull-down pull-up
6.012 Spring 2007 Lecture 12 3
1. NMOS inverter with resistor pull-up:
Inverter design issues
R |RC
L
| slow switching
g
m
|W| big transistor
(slow switching at input)
Noise margins |A
v
|
Trade-off between speed and noise margin.
During pull-up we need:
High current for fast switching
But also high incremental resistance for high noise
margin.
use current source as pull-up
6.012 Spring 2007 Lecture 12 4
2. NMOS inverter with current-source pull-up
High current throughout voltage range v
SUP
> 0
i
SUP
= 0 for v
SUP
0
i
SUP
= I
SUP
+ v
SUP
/ r
oc
for v
SUP
> 0
High small-signal resistance r
oc.
Equivalent circuit models :
IV characteristics of current source:
i
SUP
I
SUP
v
SUP
1
r
oc
v
SUP
i
SUP
+
_
I
SUP r
oc
i
SUP
v
SUP
+
_
r
oc
large-signal model small-signal model
6.012 Spring 2007 Lecture 12 5
NMOS inverter with current-source pull-up
Static Characteristics
Inverter characteristics :
High r
oc
high noise margins
V
IN
V
OUT
V
DD
C
L
i
SUP
i
D
v
OUT
= v
DS
V
IN
= V
GS

V
DD
I
SUP
+
V
DD
r
oc
V
OUT
V
IN
1 2
3
4
1
2
3 4
(a)
(b)
6.012 Spring 2007 Lecture 12 6
PMOS as current-source pull-up
Note: enhancement-mode PMOS has V
Tp
<0.
In saturation:
IV characteristics of PMOS:
I
Dp
V
SG
+ V
Tp
( )
2
5 V
S
D
G
V
G
B
I
D
(V
SG
,V
SD
)
(a)
1 2 3 4
50
100
150
200
250
300
I
Dp
(A)
V
SD
(V)
V
SG
= 3.5 V
V
SG
= 0, 0.5, 1 V
(cutoff region)
V
SG
= 3 V
V
SG
= 25
V
SG
= 2 V
V
SG
= 1.5 V
(b)
V
SD
= V
SG
+ V
Tp
= V
SG
1 V
(triode
region)
(saturation region)
I
Dp

V
D
+
_
V
SG
+
_
V
SD
5
+

6.012 Spring 2007 Lecture 12 7

PMOS as current-source pull-up:
Circuit and load-line diagram of inverter with PMOS
current source pull-up:
Inverter characteristics:
V
OUT
V
IN
0
0
V
DD
V
Tn
V
DD
NMOS cutoff
PMOS triode
NMOS saturation
PMOS triode
NMOS saturation
PMOS saturation
NMOS triode
PMOS saturation
V
OUT
V
DD
V
IN
0
0
-I
Dp
=I
Dn
V
DD
PMOS load line for V
SG
=V
DD
-V
B
V
IN
V
B
V
OUT
V
DD
C
L
6.012 Spring 2007 Lecture 12 8
PMOS as current-source pull-up:
NMOS inverter with current-source pull-up allows high
noise margin with fast switching
High Incremental resistance
Constant charging current of load capacitance
But
When V
IN
= V
DD
, there is a direct current path between
supply and ground
power is consumed even if the inverter is idle.
Ideally, we would like to have a current source that is
itself switchable, i.e it shuts off when input is high
CMOS!
V
IN
:HI
V
B
V
OUT
:LO
V
DD
C
L
V
OUT
V
DD
V
IN
0
0
-I
Dp
=I
Dn
V
DD
PMOS load line for V
SG
=V
DD
-V
B
6.012 Spring 2007 Lecture 12 9
3. Complementary MOS (CMOS) Inverter
V
IN
= 0 V
OUT
= V
DD
V
GSn
= 0 < V
Tn
NMOS OFF
V
SGp
= V
DD
> - V
Tp
PMOS ON
V
IN
= V
DD
V
OUT
= 0
V
GSn
= V
DD
> V
Tn
NMOS ON
V
SGp
= 0 < - V
Tp
PMOS OFF
Circuit schematic:
No power consumption while idle in any logic state!
Basic Operation:
V
IN
V
OUT
V
DD
C
L
6.012 Spring 2007 Lecture 12 10
Note:
V
IN
= V
GSn
= V
DD
-V
SGp
V
SGp
=V
DD
- V
IN
V
OUT
= V
DSn
= V
DD
-V
SDp
V
SDp
=V
DD
- V
OUT
I
Dn
= -I
Dp
Combine into single diagram of I
D
vs. V
OUT
with V
IN
as
parameter
V
IN
V
OUT
1
3
4
5
I
Dn
= I
Dp
I
Dp
= I
Dn
(a)
V
DD
V
OUT
V
DD
V
OUT
V
IN
(b)
n-channel p-channel
1
2
3
4
5
1
2
4
3
5
V
DD
V
DD
2
Output characteristics of both transistors:
CMOS Inverter (Contd.):
6.012 Spring 2007 Lecture 12 11
CMOS Inverter (Contd.):
No current while idle in any logic state
Inverter Characteristics:
rail-to-rail logic: logic levels are 0 and V
DD
High |A
v
| around logic threshold
good noise margins
V
OUT
V
IN
0
0
V
DD
-V
IN
I
D
V
OUT
V
IN
0
0
V
DD
V
Tn
V
DD
+V
Tp
V
DD
NMOS cutoff
PMOS triode
NMOS saturation
PMOS triode
NMOS saturation
PMOS saturation
NMOS triode
PMOS saturation
NMOS triode
PMOS cutoff
6.012 Spring 2007 Lecture 12 12
2. CMOS inverter: noise margins
Calculate V
M
Calculate A
v
(V
M
)
Calculate NM
L
and NM
H
Calculate V
M
(V
M
= V
IN
= V
OUT
)
At V
M
both transistors are saturated:
I
Dn
=
W
n
2L
n

n
C
ox
V
M
V
Tn
( )
2
I
Dp
=
W
p
2L
p

p
C
ox
V
DD
V
M
+ V
Tp
( )
2
V
OUT
V
IN
0
0
V
DD
V
M
V
IL
V
IH
V
M
V
DD
A
v
(V
M
)
NM
L
NM
H
6.012 Spring 2007 Lecture 12 13
CMOS inverter: noise margins (contd.)
Since :
Define:
k
n
=
W
n
L
n

n
C
ox
; k
p
=
W
p
L
p

p
C
ox
I
Dn
= I
Dp
Then:
1
2
k
n
V
M
V
Tn
( )
2
=
1
2
k
p
V
DD
V
M
+ V
Tp
( )
2
Solve for V
M
:
V
M
=
V
Tn
+
k
p
k
n
V
DD
+ V
Tp
( )
1+
k
p
k
n
Usually, V
Tn
and V
Tp
fixed and V
Tn
= - V
Tp
V
M
engineered through k
p
/k
n
ratio.
6.012 Spring 2007 Lecture 12 14
CMOS inverter: noise margins (contd..)
Symmetric case: k
n
= k
p
V
M
=
V
DD
2
This implies:
k
p
k
n
=1 =
W
p
L
p

p
C
ox
W
n
L
n

n
C
ox

W
p
L
p

p
W
n
L
n
2
p

W
p
L
p
2
W
n
L
n
Since usually L
p
L
n
= L
min
W
p
2W
n
Asymmetric case:
k
n
>> k
p
, or
W
n
L
n
>>
W
p
L
p
V
M
V
Tn
NMOS turns on as soon as V
IN
goes above V
Tn
.
Asymmetric case:
k
n
<< k
p
, or
W
n
L
n
<<
W
p
L
p
V
M
V
DD
+ V
Tp
PMOS turns on as soon as V
IN
goes below V
DD
+ V
Tp
.
6.012 Spring 2007 Lecture 12 15
CMOS inverter: noise margins (contd)
Calculate A
v
(V
M
)
Small signal model:
A
v
= g
mn
+ g
mp
( )
r
on
// r
op
( )
This can be rather large.
G1
G1=G2
S1
S1=S2
D1
D1=D2
+
-
v
in
+
-
v
gs1
+
-
v
out
g
mn
v
gs1
r
on
+
-
v
in
+
-
v
out g
mn
v
in
g
mp
v
in
r
on
//r
op
G2
S2
D2
+
-
v
sg2
=-v
in
g
mp
v
sg2
r
op
6.012 Spring 2007 Lecture 12 16
CMOS inverter: calculate noise margins
(contd.)
Noise-margin low, NM
L
:
V
IL
= V
M

V
DD
V
M
A
v
NM
L
= V
IL
V
OL
= V
IL
= V
M

V
DD
V
M
A
v
V
OUT
V
IN
0
0
V
DD
V
M
V
IL
V
IH
V
M
V
DD
A
v
(V
M
)
NM
L
NM
H
Noise-margin high, NM
H
:
V
IH
= V
M
1 +
1
A
v






NM
H
= V
OH
V
IH
= V
DD
V
M
1+
1
A
v






6.012 Spring 2007 Lecture 12 17
What did we learn today?
In NMOS inverter with resistor pull-up, there is a
trade-off between noise margin and speed
Trade-off resolved using current source pull-up
Use PMOS as current source.
In NMOS inverter with current-source pull-up: if
V
IN
= High, there is power consumption even if
inverter is idling.
Complementary MOS: NMOS and PMOS switch-
on alternatively.
No current path between power supply and ground
No power consumption while idling
Calculation of CMOS
V
M
Noise Margin
Summary of Key Concepts