Vn phng i din OMRON ti Vit nam

Hng dn thao tc vi ZEN

Mc lc

1 La chn ngn ng hin th ............................................................................................... 3
2 t thi gian ngy thng................................................................................................... 3
3 Lp chng trnh bc thang: ............................................................................................. 4
3.1 Ni dy u vo/ra v hot ng bn trong: ............................................................ 5
3.2- Xo chng trnh ...................................................................................................... 5
3.3- Vit chng trnh bc thang ..................................................................................... 6
V cc u vo...................................................................................................................... 8
V u ra............................................................................................................................... 9
4 Kim tra hot ng ca chng trnh bc thang............................................................. 11
Cc th tc kim tra hot ng ........................................................................................... 12
Kim tra hot ng.............................................................................................................. 12
5 Sa chng trnh bc thang: ........................................................................................... 13
5.1 Thay i u vo.................................................................................................... 13
5.2 Sa i cc chc nng ph khc cho u ra bit .................................................... 14
5.3 Xo cc u vo, u ra v cc ng ni ............................................................ 14
5.4 Chn cc dng ....................................................................................................... 14
5.5 Xo cc dng trng ................................................................................................ 15
6 S dng Timer (T) v Timer c lu (Holding Timer) (#).................................................. 16
6.1 Cc dng Timer thng (T0 n T7)...................................................................... 16
6.2 Dng Holding Timer (#0 n #3)............................................................................ 17
6.3 Thit lp trong mn hnh sa chng trnh bc thang............................................ 17
6.4 t thng s trong trang thit lp thng s (Parameter Settings) ......................... 17
6.5 Trang theo di thng s (Parameter Monitor)........................................................ 18
7 S dng b m (Counter) ............................................................................................. 18
Hot ng............................................................................................................................ 18
7.1 Thit lp thng s trong mn hnh sa chng trnh bc thang............................. 19
7.2 t thng s trong trang thit lp thng s (Parameter Settings) ......................... 19
7.3 Trang theo di thng s (Parameter Monitor)........................................................ 20
8 Weekly timer (k hiu @)................................................................................................ 20
8.1 Thit lp trong mn hnh sa chng trnh bc thang............................................ 21
8.2 t thng s trong trang thit lp thng s (Parameter Settings) ......................... 21
8.3 Trang theo di thng s (Parameter Monitor)........................................................ 22
9 Calendar Timer (k hiu * ) ............................................................................................. 22
Hot ng............................................................................................................................ 22
9.1 Thit lp trong mn hnh sa chng trnh bc thang............................................ 22
9.2 t thng s trong trang thit lp thng s (Parameter Settings) ......................... 23
9.3 Trang theo di thng s (Parameter Monitor)........................................................ 23
10 u vo tng t (analog input) v b so snh tng t (analog comparator).......... 24
Hot ng............................................................................................................................ 24
10.1 Thit lp trong mn hnh sa chng trnh bc thang............................................ 24
10.2 t thng s trong trang thit lp thng s (Parameter Settings) ......................... 25
10.3 Trang theo di thng s (Parameter Monitor)........................................................ 25
11 So snh gi tr hin ti (PV) ca counter v timer dng b so snh kiu P: .............. 26
Hot ng............................................................................................................................ 26
11.1 Thit lp trong mn hnh sa chng trnh bc thang............................................ 26
11.2 t thng s trong trang thit lp thng s (Parameter Settings) ......................... 27
11.3 Trang theo di thng s (Parameter Monitor)........................................................ 27
12 Cc bit thng bo hin th (Display bit)....................................................................... 28
12.1 Thit lp trong mn hnh sa chng trnh bc thang............................................ 28
12.2 t thng s trong trang thit lp thng s (Parameter Settings) ......................... 29
13 Dng cc bit nt bm (B)............................................................................................ 30
S dng bit nt bm............................................................................................................ 31



Trang 2
Hng dn thao tc vi ZEN






1 La chn ngn ng hin th

C th la chn ti 6 ngn ng hin th trn mt hin th LCD ca ZEN l
Anh, Php, Italia, c, Ty Ban Nha v Nht. Mc nh l ting Anh.
Ch : Khng nn thay i ngn ng hin th v vic i tr li sang ting Anh
c th kh khn khi hin th mt ngn ng khc.


Bt in



Bm OK chuyn sang trang Menu


Bm 4 ln chuyn con tr ti
LANGUAGE

Bm OK hin th ngn ng hin ti, Ch
cui ca ngn ng s nhp nhy (ch H
trong hnh)

Bm OK lm cho c t nhp nhy. By
gi ta c th la chn ngn ng khc dng
ph m /.

2 t thi gian ngy thng

Thi gian ngy thng khng c t khi xut xng. C th t thi gian
ngy thng cho cc model ca ZEN c h tr t nh nng ngy thng


SET CLOCK
YY/MM/DD
00/01/01
00:03 (SA)
SET CLOCK
SUMMER TIME
PROGRAM
RUN
PARAMETER
SET CLOCK
Sau khi bt in, bm OK hin th thit lp
cho ng h. Chn SET CLOCK

Bm OK vo trang hin th thi gian v
ngy thng hin ti. Ch s bn phi ca
ngy thng s nhp nhy







Trang 3
Hng dn thao tc vi ZEN

t thi gian v ngy thng
Dng cc ph m mi tn ln/ xung thay
i
SET CLOCK
SET ?
OK/ESC
11:35 (SU)
SET CLOCK
YY/MM/DD
00/04/01
11:35 (SU)
Dng cc ph m mi tn tri/phi thay i
v tr con nhy
Khi ngy thng c thay i, ngy th
cng t ng thay i theo. K hiu ca th
trong tun nh bng di y:

SU: Sunday
MO: Monday
TU: Tuesday
WE: Wednesday
TH: Thursday
FR: Friday
SA: Saturday


Bm OK hin th trang xc nhn thay i. Bm tip OK chp nhn thay
i

Ch :
- Nu tt in trong 1 thi gian di (2 ngy hoc hn 25
0
C), thi gian
ngy thng s b t li (reset) v gi tr mc nh l 00/1/1; 00:00 (SA)
- Nm c th c
- c nc c phn bit gi theo ma, nu chn

Nm c hin th v t theo th t sau: nm/thng/ngy

Lp chng trnh bc thang:
hng trnh mu
t trong khong t 2000 n 2099
Vi c SET CLOCK S
YY/MM/DD
01/05/01
11:35 (SU)
gi ma h (Summertime) th S s c hin th
bn phi trn cng trong thi gian ma h.
-
3

C


on sau y hng dn cch nhp 1 chng trnh bc thang: theo nh
chng trnh mu trn.










Trang 4
Hng dn thao tc vi ZEN
3.1 Ni dy u vo/ra v hot ng bn trong:

u ni ngun cp
Chng
Ni cc cng tc SW1 v SW2 vo
cc u ni input I0 v I1
Khi cng tc SW1 bt hay tt, Bit I0

(s (1) trn chng trnh bc thang)
cng bt hoc tt. Tng t vi cng
tc SW2 v bit I1
Khi chng trnh chy ch RUN

ong
v cng tc SW1 bt, Bit I0 bt ln
v cng lm bit u ra Q0 bt. Khi
tip im u ra (output contact)
cng bt theo (ch th bi s (3) tr
chng trnh)
Khi tip im u ra (output
) contact) bt ln (ch th bi s (3
trong chng trnh), ti ni vi u
ni u ra Q0 cng c bt
trnh bc
thang

3.2- Xo chng trnh
Ti




n phi xo chng trnh trong b nh ca ZEN trc khi vit 1 chng trnh

P (ch dng) mi xo c chng

m OK chuyn v mn hnh Menu v
hn DELETE PROG
m OK hin th trang xc nhn thay
m tip OK chp nhn thay i
mn
C
mi. Khi dng lnh DELETE PROG xo, ch c phn chng trnh l b
xo, cn cc phn khc nh ngn ng hin th , thi gian ngy thng v cc
thit lp khc khng b nh hng.
Cn phi chuyn ZEN v ch STO
trnh.


PROGRAM
RUN

LOCK
EDIT PROG
G
DELETE PROG
DELETE ?
EDIT PROG
G DELETE PRO
OK/ESC
DELETE PRO
PARAMETER
SET C



B
chn PROGRAM


C



B
i.

B
Sau mn hnh s quay li hin th
hnh trc ca Menu

Trang 5
Hng dn thao tc vi ZEN

3.3- Vit chng trnh bc thang
Cn phi chuyn ZEN v ch STOP mi vit hay thay i c chng

m OK chuyn v mn hnh Menu v
hn EDIT PROGRAM
au mn hnh hin th nh sau:

trnh.

EDIT PROG
G
PROGRAM
RUN

LOCK



B
chn PROGRAM

PARAMETER
SET C

C
DELETE PRO



S


m OK chuyn sang trang sa chng trnh bc thang
c hot ng khi trang sa i chng trnh bc thang:
i 1 thi im ch c th hin th c 2 dng trong mch ca chng trnh


Chng trnh v d mu

B

C

T
bc thang trong mn hnh Edit Screen.


M





Hin th
Hin th

Hin th s ca dng trong chng trnh ti v tr con tr
Con tr nhp nhy trng thi o
Cc chc nng ph thm cho u ra
i b ZEN c th cha ti 96 dng, mi dng c th gm 3 input
condition l cc tip im u vo v 1 output.

Hin th s ca dng trong chng trnh ti v tr con tr
khi c nhiu dng chng trnh di. Dng ph m mi tn xung hin th tip
khi c nhiu dng chng trnh trn. Dng ph m mi tn ln hin th tip
Trang 6
Hng dn thao tc vi ZEN


Trong hnh trn, y:
a ch bit ang c dng. Xem bng cc a ch trong
- dress: l a ch bit ang c dng
m
m v thng ng

Cc v tr cho vic vit cc u vo, u ra v ng ni

- Bit Type: l loi
PLC
Bit Ad
- Connection Line: ng ni gia cc tip i
- N.O v N.C input: cc u vo tip im thng


a- Vit u vo cho I0

m OK hin th v tr vit ban u (u
i
hp

b- Vit tip u vo I1 ni tip vi I0


m OK hin th li tip im u vo NO
m ALT chuyn sang loi tip im l

m ph m mi tn phi chuyn con tr
i
m OK chuyn con tr sang v tr nhp tip

B

vo NO a ch I0) v chuyn con tr nhp
nhy v v tr Bit type. Dng cc ph m mi
tn ln xung la chn loi ca bit (Bit
type). Dng ph m mi tn chuyn
sang v tr a ch bit v bm cc ph m m
tn ln xung thay i a ch bit
Bm nt OK hai ln hon tt vic n
a ch I0. Con tr gi y chuyn sang v tr
nhp tip theo.


B
v a ch I0

B
NC (Bm ALT chuyn v loi tip im l
NO)

B
nhy sang v tr a ch bit v dng ph m m
tn ln UP chuyn thnh 1

B
theo. ng ni (connection line) s t ng
c ni gia tip im I0 v tip im I1

Trang 7
Hng dn thao tc vi ZEN

V cc u vo

hiu cc u vo K


Cc vng nh (cc loi a ch)

hiu M t Loi a ch bit v s K
I Cc bit u vo ca module c CPU I0 --> I5 (6 u)
Q ) Cc bit u ra ca module c CPU Q0 --> Q3 (4 u
X Cc bit u vo ca module m rng
(1)
X0 --> XB (12 u)
Y Cc bit u ra ca module m rng Y0 --> YB (12 u)
(1)

M Cc bit t do dng trong chng trnh
(work bit)
M0 --> QF (16 bit)
Cc bit t d
lu trng thi (holding bit)
Cc bit bo trng thi cc n

H o dng trong chng trnh c H0 --> HF (16 bit)
B t bm B0 --> B7 (8 bit)
(2)
Ghi ch (1) Ch dng c khi ni cc module m rng vi module CPU
Cc timer, counter v b so snh gi tr (analog comparator)

hiu M t Loi a ch bit v s
(2) Ch dng c vi model c mn hnh LCD


K
T Timer tr thng thng T0 --> T7 (8 timer)
# Timer c lu trng thi khi mt in
(Holding Timer)
#0 --> #3 (4 timer)
Timer tun (Wee
* Timer ngy thng (Calendar Timer) *0 --> *7 (8 timer)
(1)

C Counter C0 --> C7 (8 counter)
A B so snh tng t (Analog
Comparator)
A0-A3 (4 b so snh)
(2)
B so snh th

@ kly Timer) @0 --> @7 (8 timer)
(1)

P ng P0-PF (16 b so snh)
Ghi ch (1) Ch dng c khi dng vi module CPU c chc nng l ch
el CPU c ngun DC

m nt ALT chuyn sang ch ghi
i
v 1 ng ni vi u ra
v ng h thi gian thc
(2) Ch dng c vi mod
B
ng ni. Con tr hnh mi tn ch sang tr
s nhp nhy
Bm nt


Trang 8
Hng dn thao tc vi ZEN


u ra V



Cc vng nh cho u ra

hiu 3.1.1.1.1.1 M t Loi a ch bit v s K
Q Cc bit u ra ca module c CPU Q0 --> Q3 (4 u)
Y Cc bit u ra ca module m rng Y0 --> YB (12 u)
(1)

M Cc bit t do dng trong chng trnh
(work bit)
M0 --> MF (16 bit)
Cc bit t d
lu trng thi (holding bit)
H o dng trong chng trnh c H0 --> HF (16 bit)

Cc chc nng ph thm khc cho cc bit u ra

hiu M t K
[ Hot ng ca u ra output s nh bnh thng
S Khi c bt bi lnh output kiu S (Set) ny, bit u ra s gi
b nguyn trng thi bt k c sau khi cc bit i trc l OFF v ch
tt vi lnh output kiu R
Khi c tt bi lnh outpu
nguyn trng thi tt k c sau khi cc bit i trc l OFF v ch
c bt vi lnh output kiu S
Mi khi lnh output kiu A (Alter
chuyn sang trng thi ngc li, v d khi ang ON s chuyn
sang OFF v ngc li
R t kiu R (Reset) ny, bit u ra s gi
A nate) c thc hin bit output s

in ca cc lnh output G


Q0 bt v tt
t
Q1 bt v vn Q2 tt khi I2 bt Q3 chuyn
a
i
khi I0 bt v t



ON khi I1 bt ri
tt
trng thi gi
ON v OFF m
khi I3 bt

Cc chc nng ph thm khc





Trang 9
Hng dn thao tc vi ZEN
Timers, Holding Timers, Counters, v Display Output



hiu M t Loi a ch bit v s Loi u ra K
T Timer T0 --> T7 (8 timer)
# Timer c lu trng
ch

er
thi khi mt in
(Holding Timer)
#0 --> #3 (4 timer)
T: u vo k
hot timer
R: u vo
Reset cho tim
Counter C: u vo m
cho counter
D: Chiu m
cho counter
R: u vo
reset cho
counter
bit) (ch cho mode
hnh)
D
C C0 --> C7 (8 counter)

D Bit hin th (Display D0-D7 (8 bit)
l c mn

c- Vit u ra cho bit Q0
m ln na v mt ng ni vi u ra
m OK hin th gi tr ban u cho u ra
tn ln /xung / la
hc
m nt OK hai ln hon tt vic nhp a
d- Vit 1 tip im Q0 song song vi I0

B

v chuyn con tr v v tr ghi u ra

B
(u ra bnh thng/Q0) v chuyn con tr nhy
v v tr loi bit Q.
Dng cc ph m mi
chn loi bit. Dng cc ph m v di
chuyn con tr v dng v chn cc c
nng khc hay chn a ch bit.

B
ch Q. Con tr gi y chuyn sang v tr nhp
input u dng tip theo.

m OK hin th I0 ri chuyn con tr v v tr
m la chn loi bit l Q
m nt OK hai ln hon tt vic nhp a
ch I0. Con tr gi y chuyn sang v tr nhp
tip theo.

B
la chn loi bit

B


B
Trang 10
Hng dn thao tc vi ZEN


e- V cc ng ni cho mch song song (mch OR)



Bm ALT khi con tr ang im gia 2 v tr cn ni, con tr s chuyn sang
nh v cho php v cc ng ni. Bm cc ph m , , , v cc
nhn.
chuyn sang ch v cc ng
i
ng thi v c ng ni thng ng
ngang. Du cng (+) biu th giao im.
huyn sang con tr nhp nhy.
.
nu
vit chng trnh vi cc ng ni to thnh vng k n. Chng trnh
th hot ng khng ng nu v nh vy
v chng trnh s b mt.
N
o hot ng tht.
rc khi bt in, hy kim tra dy ngun, dy u vo v mch u
ra u c ni ng v tt

h
ng ni ngang v thng ng.
Ch v cc ng ni s c thot ra khi n u hay cui mi dng
hoc khi ph m OK hay ESC c

Bm ALT

Ch :
n

Bm
v

Bm OK hon tt vic v ng ni v
c

Bm ESC kt thc hot ng v

Bm tip ESC tr v mn hnh Me


- Khng
c
- Lun lun bm ESC quay tr v mn hnh Menu. Nu khng quay tr v
mn hnh Menu trc khi tt in, cc thit lp

4 Kim tra hot ng ca chng trnh bc thang

Hy lun kim tra hot ng ca chng trnh bc thang trc khi a ZE
v

Ch :

- T
- Nn tho b dy ni vi ti ca u ra trc khi hot ng th trnh
cc s c c th xy ra
- Lun lun m bo an ton vng xung quanh trc khi bt in
ngun
Trang 11
Hng dn thao tc vi ZEN


c th tc kim tra hot ng C
im tra trc khi bt ngun
1. Kim tra rng ZEN c lp v u dy ng
c th xy ra khi ZEN hot ng
3. Bt ngun cho ZEN. Chuyn ZEN sang ch RUN

Ki

4. Bt mi u vo ln ON hoc v OFF v xem chng trnh c hot
ng
5. iu chnh li khi c vn

Phng php kim tra hot ng

Kim tra bng cc hin th u vo v
u ra nhp nhy

K

2. Kim tra nu c s c g
m tra hot ng
ng ng kh

Vi loi c mn hnh LCD
Vi loi khng c mn hnh LCD (loi Ni ZEN vi phn mm ZEN Support
ch th bng n LED) Software v kim tra bng chc nng
monitor.

Kim tra hot ng

hay i ch hot ng

Bm OK hin th mn hnh Menu v bm
chuyn con tr n RUN
T




PROGRAM
RUN
PARAMETER
SET CLOCK

Bm OK chuyn t STOP sang RUN


MONITOR
STOP
PARAMETER
SET CLOCK













Trang 12
Hng dn thao tc vi ZEN





SC
mn hnh ch nh
Q0 s ON khi
I0 ln ON
Q0 s vn ON
k c khi I0 v
OFF
Q0 s v OFF
khi I1 bt ln
ON


5 Sa chng trnh bc thang:
.1 Thay i u vo 5

Di chuyn con tr v v tr cn thay i u
vo
v chuyn con tr sang v tr nhp loi
it.
g ph m / thay i i ch bit t 0

Kim tra hot ng
mn hnh ch nh
Kim tra hot ng dng chc nng
theo di chng trnh bc thang
Bm ph m OK
chng trnh bc
i I0
N, cc
ng ni ng
Chn Monitor
ch RUN
PROGRAM
STOP
PARAMETER
SET CLOCK
Bm E
chuyn sang
chuyn sang mn
hnh theo di
thang
Q0 s ON kh
ln ON. Khi bit
ny O
v ngang s
m ln




Bm OK i con tr sang dng nhp
nhy
b
Bm ph m / la chn M
Bm chuyn sang v tr nhp loi bit.
Dn
ln 1.

Bm OK hon tt





Trang 13
Hng dn thao tc vi ZEN


5.2 Sa i cc chc nng ph khc cho u ra bit

By gi ta s thay i chc nng u ra bit sang S (tc SET)
Di chuyn con tr v v tr cn thay i u
OK i con tr sang dng nhp
hy
m chuyn con tr sang v tr thay i
m hai ln chuyn chc nng


ra


Bm
n
B
chc nng u ra.
Bm ph
u ra t [ thnh S

Bm OK hon tt


5.3 Xo cc u vo, u ra v

cc ng ni
Di chuyn con tr ti v tr ca u vo, u ra hay ng ni cn xo v bm
.



m DEL xo u vo v xo lun
ng ni i cng

Di chuyn con tr ti v tr ca u vo bn
a ng ni ny. Bm ALT
huyn sang ch v ng ni. Con tr
DEL

V d: Xo u vo ni tip M3

V d: Xo cc ng ni thng


B

ng

phi c
c
chuyn sang hnh mi tn

Bm DEL xo




5.4 Chn cc dng

chn 1 dng trng, chuyn con tr v u dng cn chn thm 1
n ALT dng trng v
Trang 14
Hng dn thao tc vi ZEN



chn mch song song (mch OR), cc u vo c th c thm
vo gia cc u vo song song.

Chuyn con tr v u dng cn chn thm 1 dng trng v n ALT




.5 Xo cc dng trng 5
n con tr v v tr u ca dng cn xo v n
EL.

xo 1 dng trng, chuy
D




Dng trng
Mt dng mi s c chn ti y
Bm ALT chn ti y
Mt dng mi s c chn ti y
Bm ALT chn thm khong
trng rng 1 dng gia cc u vo
song song.
Dng ny s c xo
Bm ALT xo dng trng
Cc dng ph a di s c t ng
chuyn ln
Cc ng ni thng ng s c
t ng ko di











Trang 15
Hng dn thao tc vi ZEN

6 S dng Timer (T) v Timer c lu (Holding Timer)
ZEN c sn 8 timer thng (T) v 4 holding timer (#):
et) khi timer chuyn t
RUN sang STOP hoc khi ngt in
(#)


Timer Gi tr hin hnh (PV) s b xo (res
C 4 dng timer thng c th s dng
Gi tr hin hnh (PV) s vn c l
RUN sang STOP hoc khi ngt in. Tim
vo k ch (trigger) ln ON. Bit u ra ca timer cng c gi
nguyn trng thi khi timer m xong.
C 1 dng holding timer
Timer thng (T0 n T7
Holding timer u khi timer chuyn t
er li tip tc khi u


6.1 Cc dng )
K hiu
Loi ng
dng

Loi timer Hot ng
ch nh
time gian t tr
sau khi u
vo trigger ln
ON

Tr
gi
thi
an
timer
Vn ON
trong
vo trigger
v tt sau 1
khong thi
gian t trc
sau khi u
vo trigger v
OFF

t thi
gian cho
g chiu sn
v qut
thng gi
timer
Vn ON
trong
thi gian
trc khi u
vo trigger b
ln ON

timer
Bt v tt lp i
lp li tro
khong chu k
t trc tron
khi u vo
trigger ON

Mch bo
ng bo

ci v n
nhp nhy
X On
DELAY
r
Bt sau 1
khong thi
c

OFF
DELAY khi u
ON

O One-shot
pulse 1 khong
t
t

F Flashing
pulse

ng
g








Trang 16
Hng dn thao tc vi ZEN

6.2 Dng Holding Timer (#0 n #3)
Loi ng
dng

Loi timer Hot ng
ch nh
time
thi gian
t trc
sau khi
u vo
trigger l
ON

Tr
g

thi
ian c
yu cu
tip tc
tr li sau
khi mt
in
X On
DELAY
r
Bt sau 1
khong

n

6.3 Thit lp trong mn hnh sa chng trnh bc thang
c v mn
nh Sa chng trnh bc thang.

Cc u vo trigger, u ra reset v cc thng s ca timer
h




imer address
a ch timer)
T0 n T7 hoc #0 n #3 T
(
Trigger input T (TRG) iu khin u vo trigger ca timer.
S k ch hot timer khi u vo trigger
bt ln ON
iu khin u ra reset ca timer. Khi
u vo rese
ca timer (PV) b xo v 0. Trng thi
u vo trigger s b b qua trong khi
u vo reset input ON
i timer
6.4 t trong trang thit lp thn
Reset input R (RES)
t bt ln ON, gi tr hin ti
Timer bit S bt tu theo lo

thng s g s (Parameter Settings)





Trang 17
Hng dn thao tc vi ZEN

Timer Type




ime Unit (n v thi gian)
n v 0,01 giy) Sai s: 0 n 10ms
T

S 00,01 n 99,99s (theo
M:S 00 pht 01s n 99 pht 59s (theo n v Sai s: 0 n 1s
pht giy)
H:M 00 gi 01 pht n 99h 59 pht (theo n v
gi pht )
t Sai s: 0 n 1 ph

Monitor Enabled/Disabled
c theo di v thay i A Cc thng s c th
D Cc thng s khng c php theo di v thay i


6.5 Trang theo di thng s (Parameter Monitor)
g th c theo di
ong trang ny.

Trn thi ca cc thng s v u vo ra ca timer c
tr




S dng b m (Counter)
tng hay m gim. Gi tr hin
nh ca counter (Present Value - PV) v trng thi ca u ra counter c
7

C th s dng ti 8 b m ch m
h
lu c khi ch hot ng ca ZEN thay i hay khi mt in.

Hot ng

Bit u ra ca counter (counter bit) bt ln ON khi gi tr m (hay gi tr hin
nh Present Value PV) vt qu gi tr t (set value - SV) (PVSV). Gi tr h
m s quay v 0 v bit u ra tt khi u vo reset bt ln ON. Cc u vo
m b b qua trong khi u vo reset ON.

Trang 18
Hng dn thao tc vi ZEN


.1 Thit lp thng s trong mn hnh sa chng trnh bc thang



7
c u ra cho u vo ca counter, chiu m (counter direction) v u C
vo reset c vit trong mn hnh sa chng trnh. Cc thng s thit lp
cho counter c t trang thit lp thng s (Parameter Setting)



ounter address C0 n C7 C
( a ch counter)
Counter input
(u vo m)
C (CNT) S tng hay gim gi tr m PV mi khi u
vo ny bt ln ON
Counter direction
nh chiu
D (DIR) m tng hay gim:
input
(Xc
m)
Chuyn gia ch
OFF: m tng
ON: m gim
Reset input R (RES) iu khin u ra reset ca counter. Khi u
s

(Reset) vo reset bt ln ON, gi tr hin ti ca
counter (PV) b xo v 0 v bit u ra
counter v OFF. Trng thi u vo m
b b qua trong khi u vo reset input ON
m m n gi tr t (PVSV)

Timer bit S bt khi b

7.2 t thng s trong trang thit lp thng s (Parameter Settings)






Trang 19
Hng dn thao tc vi ZEN
Set Value 0001 n 9999 ln
A Cc thng s c th c theo di v thay
i Monitor
disabled D thng s khng c php theo di v enabled/ Cc
thay i

.3 Trang theo di thng s (Parameter Monitor) 7
rng thi ca cc thng s v u vo ra ca counter c th c theo di T
trong trang ny.



h :
1. xo gi tr hin ti ca counter (PV) v bit u ra ca counter
.
C
(counter bit) khi ngt in hay khi thay i ch hot ng,
hy to 1 mch xo (reset) lc bt u thc hin chng trnh
Sau y l 1 v d:

2. Nu u vo m v u vo xc nh chiu (direction) cng
u c a vo counter cng lc, hy t u vo xc nh chi
trc u vo m trong chng trnh.


Weekly timer (k hiu @)
eekly timer s bt ln ON gia cc thi gian bt v tt (start /stop time) inh
8

W
trc trong nhng ngy xc nh. C 8 Weekly timer nh s t @0 n @7.

Ngy trong tun

hi T
gian
Trong v d trn, Weekly timer s bt ln ON mi ngy t

th Ba n th Su gia 8:15 v 17:30


Trang 20
Hng dn thao tc vi ZEN
8.1 Thit lp trong mn hnh sa chng trnh bc thang


Cc u vo ca timer c v mn hnh Sa chng trnh bc thang.
eekly timer address: @0 n @7 (8 timer) W



8.2 t thng s trong trang thit lp thng s (Parameter Settings)



et Value 0001 n 9999 ln S
Start day T Ch Nht n Th By
Fri/Sat) (Sun/Mon/Tues/Wed/Thurs/
Day
(ngy)
Stop day
Fri/Sat)
T Ch Nht n Th By
(Sun/Mon/Tues/Wed/Thurs/
00:00 n 23:59
(thi g Stop time 00:00 n 23:59
A Cc thng s c th c theo di v
thay i Monitor
disabled D g s khng c php theo enabled/ Cc thn
di v thay i
Start time Time
ian)

h : Khi con tr nm start day (ngy bt), bm ri bm / t
heo
uan h gia thi gian v ngy bt v tt (Start-Stop Day/Time)
Thng s t V d Hot ng
C
ngy tt (stop day). Nu stop day khng c t, timer s ch hot ng t
thi gian t.

Q

Khi Start day trc MO Hot ng t Th Hai n
Stop day
-FR
Th Su hng tun
Khi Start day sau FR-MO u hng
Stop day
Hot ng t Th S
tun n Th Hai tun sau
Khi Start day trng MO-MO
vi Stop day
Hot ng bt k ngy
trong tun
Day
Khi Stop day k
c t
Hot ng c
hng tun
Start-Stop
(ngy)
hng FR- h vo Th Su
Trang 21
Hng dn thao tc vi ZEN
Khi Start time trc
Stop time
ON: 08:00
OFF: 17:00
Hot ng t 08:00 n
17:00 hng ngy
Khi Start time sau
Stop time
ON: 18:00
OFF: 07:00
Hot ng t 18:00 n
07:00 ngy hm sau
Time
(thi gian)
Khi Start time trng
vi Stop time
ON: 18:00
OFF: 18:00
Hot ng bt k thi gian


8.3 Trang theo di thng s (Parameter Monitor)

Trng thi ca cc thng s v u vo ra ca timer c th c theo di
trong trang ny.


Ngy hin ti
Thi gian hin ti

9 Calendar Timer (k hiu * )

Calendar Timer (Timer theo ngy trong thng) bt ln ON trong cc ngy nh
trc. C 8 Calendar Timer k hiu t *0 n *7.

Hot ng




Calendar Timer bt ln ON trong cc ngy t 1/4 n
31/8 (1 April 31 August)


9.1 Thit lp trong mn hnh sa chng trnh bc thang


Cc u vo ca timer c v mn hnh Sa chng trnh bc thang.

Calendar timer address: *0 n *7 (8 timer)




Trang 22
Hng dn thao tc vi ZEN

9.2 t thng s trong trang thit lp thng s (Parameter Settings)




Start Date
(ngy bt)
T 1/1 n 31/12
Stop Date
(ngy tt)
T 1/1 n 31/12
A Cc thng s c th c theo di v thay
i Monitor
enabled/disabled D Cc thng s khng c php theo di v
thay i

Ch : Ngy thng trong ZEN c hin th theo th t nh sau:
nm/thng/ngy
V d: 4/5 l ngy 5 thng 4

Quan h gia ngy bt v tt (Start-Stop Date)

Thng s t V d Hot ng
Khi Start
date trc
Stop date
ON: 04/01
OFF: 09/01
Hot ng t 1/4 n 1/9
Khi Start
date sau
Stop date
ON: 04/01
OFF: 02/01
Hot ng t 1/4 n 1/2
nm sau Start-Stop Day
(ngy)
Khi Start
date trng
vi Stop
date
ON: 02/01
OFF: 02/01
Hot ng khng k ngy
thng

Ch : dng hot ng vo v d ngy 1/4, hy t stop date l ngy sau
ngy tc ngy 2/4


9.3 Trang theo di thng s (Parameter Monitor)

Trng thi ca cc thng s v u vo ra ca timer c th c theo di
trong trang ny.


Ngy hin ti

Trang 23
Hng dn thao tc vi ZEN
10 u vo tng t (analog input) v b so snh
tng t (analog comparator)

C th ni 2 u vo tng t 0-10V vo module CPU ca ZEN (vi model
dng ngun DC). Hai u vo ny l I4 v I5 nh hnh di.
T n hiu tng t c chuyn i thnh dng dng s BCD t 00.0 n 10.0.
Kt qu c th c dng vi 1 trong 4 b so snh tng t (analog
comparator) k hiu A0 n A3. Kt qu ca vic so snh ny c th c
dng lm u vo trong chng trnh.


Thit b cho
t n hiu
analog

Hot ng

V d 1 V d 2
Khi u vo analog I4 5.2V Khi u vo analog I5 I4



u ra ca b comparator s bt ln
ON khi in p u vo 1 t n
5,2V hoc cao hn
u ra ca b comparator s bt ln ON
khi in p u vo 2 cao hn u vo 1

Ch :
Khng c a t n hiu in p m vo cc u vo I4 v I5. Lm nh
vy c th lm hng cc mch bn trong ZEN.

10.1 Thit lp trong mn hnh sa chng trnh bc thang


Trang 24
Hng dn thao tc vi ZEN
Cc u vo ca b so snh analog c v mn hnh Sa chng trnh
bc thang.

Analog Comparator address: A0 n A3 (4 comparator)

10.2 t thng s trong trang thit lp thng s (Parameter Settings)


V d 1 V d 2
Khi so snh u vo analog vi 1
hng s (v d I4 hng s)
Khi so snh cc u vo analog ( v
d I5 I4)




D liu so snh 1
D liu so snh 1
Ton t so snh
Ton t so snh
D liu so snh 2
D liu so snh 2


Analog Comparator
address
T A0 n A3
1 I4: u vo analog 1
I5: u vo analog 2
D liu so snh
2 I5: u vo analog 2
Hng s: t 00.0 n 10.5
u ra ca b so snh (analog
comparator bit) s bt khi d liu so snh
1 d liu so snh 2
Ton t so snh
u ra ca b so snh (analog
comparator bit) s bt khi d liu so snh
1 d liu so snh 2
A Cc thng s c th c theo di v
thay i Monitor
enabled/disabled D Cc thng s khng c php theo di
v thay i


10.3 Trang theo di thng s (Parameter Monitor)

Trng thi ca cc thng s v u vo ra ca b so snh v u vo analog
c th c theo di trong trang ny.

Di y l mn hnh khi theo di hai dng so snh.

Trang 25
Hng dn thao tc vi ZEN




11 So snh gi tr hin ti (PV) ca counter v timer
dng b so snh kiu P:


Gi tr hin ti (PV) ca counter, holding timer (#) v timer (T) c th c so
snh dng b so snh loi P. C th so snh gi tr hin ti ca 2 counter v
timer thuc cng 1 loi hay so snh vi 1 hng s.

Hot ng

V d 1 V d 2

Khi so snh holding timer #0
12min34s


Khi so snh counter C1 counter C2




11.1 Thit lp trong mn hnh sa chng trnh bc thang


Cc u vo ca b so snh analog c v mn hnh Sa chng trnh
bc thang.

Comparator address: A0 n A3 (4 comparator)


Trang 26
Hng dn thao tc vi ZEN

11.2 t thng s trong trang thit lp thng s (Parameter Settings)


V d 1 V d 2

Khi so snh vo analog vi 1 hng s
(v d I4 hng s)

Khi so snh cc u vo analog ( v d
I5 I4)





Loi so snh
Ton t so snh
D liu so snh 2
D liu so snh 1
Loi so snh
Ton t so snh
D liu so snh 2
D liu so snh 1
Loi so snh T: Timer
#: Holding timer
C: Counter
1 T: T0 T7
#: #0 #7
C: C0 C7
D liu so snh
2 T: T0 T7
#: #0 #7
C: C0 C7
Hng s:
- t 00.0 n 99.99 khi loi so snh l T hoc
#
- t 0000 n 9999 khi loi so snh l C
u ra ca b so snh (comparator bit) s bt khi
d liu so snh 1 d liu so snh 2
Ton t so snh
u ra ca b so snh (comparator bit) s bt khi
d liu so snh 1 d liu so snh 2
A Cc thng s c th c theo di v thay i
Monitor
enabled/disabled
D Cc thng s khng c php theo di v thay
i


11.3 Trang theo di thng s (Parameter Monitor)

Trng thi ca cc thng s v u vo ra ca b so snh c th c theo
di trong trang ny.

Di y l mn hnh khi theo di hai dng so snh.




Trang 27
Hng dn thao tc vi ZEN

Ghi ch:
- Bm ALT chuyn d liu so snh gia a ch timer/counter v hng
s
- n v thi gian c xc nh nh sau khi loi so snh l Timer hay
Holding timer:
o Khi hng s c t cho d liu so snh 2, n v thi gian
c t ng nh ph hp vi n v thi gian ca timer trong
d liu so snh 1
o Cc n v thi gian c t ng chnh nh ph hp khi cc
n v thi gian l khc nhau gia timer trong trong d liu so
snh 1 v 2.



12 Cc bit hin th thng bo (Display bit)

Chng trnh trong ZEN c th hin th ln trn mn hnh LCD cc thng bo
t t, thi gian, gi tr hin hnh ca timer/counter hay gi tr ca b so snh
analog. C th hin th nhiu d liu trn cng mn hnh.

V d 1 V d 2

Theo di tnh trng h thng

Hin th ngy v thi gian li h thng xut
hin
Thit lp Thit lp






12.1 Thit lp trong mn hnh sa chng trnh bc thang



iu kin thc hin cho Display bit
Cc u vo ca bit hin th c v mn hnh Theo di thng s
(Parameter Settings).

Display address: D0 n D7 (8 bit)

Trang 28
Hng dn thao tc vi ZEN

12.2 t thng s trong trang thit lp thng s (Parameter Settings)



L0 Khng c chiu sng nn. Khng t chuyn
sang mn hnh hin th thng bo
(1)
L1 C chiu sng nn. Khng t chuyn sang
mn hnh hin th thng bo
(1)

L2 Khng c chiu sng nn. T chuyn sang
mn hnh hin th thng bo
(2)

Backlight/Display
L3 C chiu sng nn. T chuyn sang mn
hnh hin th thng bo
(2)

Display start
position
(V tr bt u
hin th )
X (v tr ch s): 00 n 11
Y: (dng): 0 n 3

CHR Cc k t (ti a 13 k t ch s v k hiu)
DAT Thng/Ngy (5 k t: /)
CLK Gi/pht (5 k t: :)
I4-I5 Gi tr analog (4 k t: .)
T0-T7 Gi tr hin ti ca timer (5 k t: .)
#0-#3 Gi tr hin ti ca timer (5 k t: .)
Display object
C0-C7 Gi tr hin ti ca counter (4 k t: )
A Cc thng s c th c theo di v thay
i Monitor
enabled/disabled D Cc thng s khng c php theo di v
thay i

Ch :
(1) Khi L0 hay L1 c chn tt chc nng hin th trang thng
bo, trang hin th thng bo s khng c hin th t ng.
Dng cc ph m chuyn ti trang hin th hot ng.
(2) Khi L2 hay L3 c chn bt chc nng hin th trang thng
bo, trang hin th thng bo s c hin th t ng hin th
d liu t. Mn hnh ch nh s khng c hin th . hin
th mn hnh ch nh, phi chuyn CPU v ch STOP.



Trang 29
Hng dn thao tc vi ZEN
Thit lp khi hin th ch (khi chn CHR)


Ni hin th cc k t (ti a:12)
Cc k t c th la chn hin th
V tr con tr hin th
V tr bn trong chui hin th
K t s oc chn
Nhy sng ng thi khi ang t
K t trc v sau k t s oc chn

Dng / cun qua cc k t c th la chn
cho hin th
K t c la s nhp nhy v ni bt


Dng ph m chuyn v tr t k t hin th
sang phi. Dng ph m chuyn v tr t k t
hin th sang tri









13 Dng cc bit nt bm (B)

Vi model c mn hnh LCD, mi khi bm 1 nt trn ZEN, bit nt bm tng
ng (Button switch) s thay i trng thi. C 8 bit nt bm, k hiu v a ch
t B0 n B7.




Trang 30
Hng dn thao tc vi ZEN




S dng bit nt bm

Cc nt bm c th c dng nh cc ph m n xo gi tr hin hnh ca
counter hay holding bit.

V d:
Bm DEL+ALT ng thi trong khi ang chy reset
counter C2 v 0 v bit H5 v OFF chng trnh bn.




Ch :
- Cc nt bm c th c dng nh l nt hot ng cho mi mn hnh.
Khi dng cc nt nh l cc bit nt bm, hy thc hin cc la chn tu
theo tnh trng ca mn hnh
- Cc nt c th c dng cho cc hot ng h thng ca ZEN nh
la chn menu, bt k bit nt bm c ang c s dng khng.
Khi 1 nt bm c nhn cho cc hot ng h thng ca ZEN, bit
tng ng cng bt. Hy m bo l h thng khng b nh hng
trc khi bm cc nt ny

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Hng dn thao tc vi ZEN

Cat No: ZEN-MAN-VN-1














OMRON, 2001
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system,
or transmitted, in any form, or by any means, mechanical, electronic, photocopying,
recording, or otherwise, without the prior written permission of OMRON.
No patent liability is assumed with respect to the use of the information contained herein.
Moreover, because OMRON is constantly striving to improve its high-quality products, the
information contained in this manual is subject to change without notice. Every precaution
has been taken in the preparation of this manual. Nevertheless, OMRON assumes no
responsibility for errors or omissions. Neither is any liability assumed for damages resulting
from the use of the information contained in this publication.















Revision: 1 7/01
Produced: TNBINH
Vn phng i din:
Cng ty OMRON ASIA PACIFIC PTE. LTD.
H ni:
2 Lng H, tng 6 (To nh VINACONEX)
Tel : 8313 121 / 8313 122 Fax : 8313 122
E-mail : OMRONHN@FPT.VN
TP H Ch Minh:
99 Nguyn Th Minh Khai, Q1
Tel : 830 1105 / 839 6666 Fax : 830 1279.
E-mail : OMRONHCM@HCM.VNN.VN
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