8051 Microcontroller

8051 Microcontroller
Presented By,
Er. Swapnil Kaware,
B.E. (Electronics),
svkawareya!oo.co.in
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Salient "eat#res
Salient "eat#res
(1). 8 $it %icrocontroller ori&inally developed $y 'ntel in 1(80.
()). *i&!+per,or%ance -M.S /ec!nolo&y.
(0). -ontains /otal 10 pins.
(1). 2ddress $#s is o, 13 $it 4 data $#s is o, 8 $it.
(5). 1K $ytes internal 5.M (pro&ra%).
(3). 1)8 $ytes internal 52M (data).
(6). "o#r 8+$it '7. ports.
(8). /wo 13+$it ti%ers.
((). Serial inter,ace -o%%#nication.
(10). 31K e8ternal code 4 data %e%ory space.
(11). )10 $it+addressa$le locations.
(1)). 'nternal %e%ory consists o, on+c!ip 5.M and on+c!ip data 52M.
(10). 8051 i%ple%ents a separate %e%ory space ,or pro&ra%s (code) and data.
(11). .peratin& ,re9#ency is )1M*:+00M*:.
(15). ;5< 5e&#lated =- power s#pply is re9#ired to operate .
(13). 't !as ,o#r 8 $it ports, total 0) '7. lines.
(16). 52M, 5.M, '7. ports, one serial port and ti%ers are all on+c!ip.
(18). 3+interr#pts () are e8ternal wit! ) priority levels).
(1(). >ow+power 'dle and Power+down Modes.
()0). "#ll d#ple8 ?25/.
()1). 8051 !as )1 special ,#nction re&isters (S"5s).
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8051 Block =ia&ra%
8051 Block =ia&ra%
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'nternal 2rc!itect#re
'nternal 2rc!itect#re
.scillator -irc#it@+
(1). /!e 8051 re9#ires an e8ternal oscillator circ#it.
()). /!e oscillator circ#it #s#ally r#ns aro#nd 1)M*:.
(0). /!e crystal &enerates 1)M p#lses in one second.
(1). /!e p#lse is #sed to sync!roni:e t!e syste% operation in
a controlled pace.
(5). 2n 8051 %ac!ine cycle consists o, 1) crystal p#lses
(clock cycle).
(3). ?sed ,or sync!roni:in& internal operations.
(6). Pins A/2>1 4 A/2>) !ave $een #sed.
(8). /!e len&t! o, %ac!ine cycle depends on t!e ,re9#ency o,
t!e crystal oscillator connected to 8051.

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'nternal Me%ory
'nternal Me%ory
(1). 8051 i%ple%ents a separate %e%ory space ,or pro&ra%s
(code) and data.
()). Bot! code and data %ay $e internal, !owever, $ot! e8pand
#sin& e8ternal co%ponents to a %a8i%#% o, 31K code %e%ory
and 31K data %e%ory.
(0). 'nternal %e%ory consists o, on+c!ip 5.M and on+c!ip data
52M.
(1). .n+c!ip 52M contains a ric! arran&e%ent o, &eneral p#rpose
stora&e, $it addressa$le stora&e, re&ister $anks, and special
,#nction re&isters.
(5). 'n t!e 8051, t!e re&isters and inp#t7o#tp#t ports are %e%ory
%apped and accessi$le like any ot!er %e%ory location.
(3). 'n t!e 8051, t!e stack resides wit!in t!e internal 52M, rat!er
t!an in e8ternal 52M.
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6
5e&isters 52M %e%ory space
allocation in t!e 8051
Microcontroller
5e&isters 52M %e%ory space
allocation in t!e 8051
Microcontroller
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5e&ister $anks in t!e 8051
Microcontroller
5e&ister $anks in t!e 8051
Microcontroller
Special "#nction 5e&isters
Special "#nction 5e&isters
(1). 2--
()). B
(0). PSB
(1). SP
(5). =P/5
(5). 'P
(3). PM.=E
(6). P-.C
(8). /M.=E
((). /-.C etc.
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(1). 8051 !as )1 special ,#nction re&isters (S"5s) at t!e top o,
internal 52M ,ro% address 80* to ""*.
()). Most o, t!e addresses ,ro% 80* to ""* are not deDned,
e8cept ,or )1 o, t!e%.
(0). So%e S"5Es are $ot! $it+addressa$le and $yte
addressa$le, dependin& on t!e instr#ction accessin& t!e
re&ister.
(1). /!is area consists o, a series o, %e%ory+%apped ports
and re&isters.
(5). 2ll 8051 -P? re&isters, '7. ports, ti%ers and ot!er
arc!itect#re co%ponents are accessi$le in 8051 - t!ro#&!
S"5s
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Special "#nction
5e&isters
Special "#nction
5e&isters
B 5e&ister
B 5e&ister
(1). B re&ister or acc#%#lator B is #sed alon&
wit! t!e acc#%#lator ,or %#ltiply and divide
operations.
()). M?> 2B@ %#ltiplies 8 $it #nsi&ned val#es in 2
and B. and leaves t!e 13 $it res#lt in 2 (low
$yte) and B (!i&! $yte).
(0). ='< 2B@ divided 2 $y B, leavin& t!e inte&er
res#lt in 2 and re%ainder in B.
(1). B re&ister is $it+addressa$le.
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PSB (Pro&ra% Stat#s word) 7
"la& 5e&ister
PSB (Pro&ra% Stat#s word) 7
"la& 5e&ister
(1). Stack pointer (SP) is an 8+$it re&ister at
address 81*.
()). 't contains t!e address o, t!e data ite%
c#rrently on top o, t!e stack.
(0). Stack operations incl#de p#s!in& data on t!e
stack andpoppin& data oF t!e stack.
(1). P#s!in& incre%ents SP $e,ore writin& t!e
data
(5). Poppin& ,ro% t!e stack reads t!e data and
decre%ents t!e SP
(3). 8051 stack is kept in t!e internal 52M
(6). =ependin& on t!e initial val#e o, t!e SP,
stack can !ave diFerent si:es
(8). E8a%ple@ M.< SP,G5"*
((). .n 8051 t!is wo#ld li%it t!e stack to 0)
$ytes since t!e #pper%ost address o, on c!ip
52M is 6"*.
Stack Pointer
Stack Pointer
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=ata pointer (=P/5)
=ata pointer (=P/5)
(1). =ata pointer (=P/5)@ is #sed to access e8ternal data
or code.
()). =P/5 is a 13 $it re&ister at addresses 8)* (low $yte)
and 80* (!i&! $yte).
(0). /!e data pointer is #sed in operations re&ardin&
e8ternal 52M and so%e instr#ctions involvin& code
%e%ory.
(1). E8a%ple@ t!e ,ollowin& instr#ctions write 55* into
e8ternal 52M location 1000*@
M.< 2,G55*
M.< =P/5,G1000*
M.<A =P/5,2
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'7. Ports
'7. Ports
(1). .ne o, t!e %aHor ,eat#res o, a %icrocontroller is t!e
versatility $#ilt into t!e '7. circ#its t!at connect t!e
%icrocontroller to t!e o#tside world .
()). /o $e co%%ercially via$le, t!e 8051 !ad to incorporate as
%any '7. ,#nctions as were tec!nically and econo%ically
possi$le.
(0). .ne o, t!e %ost #se,#l ,eat#res o, t!e 8051 is ,o#r
$idirectional '7. ports.
(1). Eac! port !as an 8+$it latc! in t!e S"5 space as %entioned
earlier.
(5). /o red#ce t!e overall packa&e pin co#nt, t!e 8051 e%ploys
%#ltiple ,#nctions ,or eac! port.
(3). Eac! port also !as an o#tp#t drive and an inp#t $#Fer.
(6). /!ese ports can $e #sed to &eneral p#rpose '7., as an
address and data lines.
(8). /!e ,o#r 8+$it '7. ports P0, P1, P) and P0 eac! #ses 8 pins
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'7. Ports
'7. Ports
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P.5/ 0
P.5/ 0
(1). Port 0 is 8+$it$idirectional '7. port.
()). Port 0 pins can $e #sed as !i&!+i%pedance inp#ts.
(0). Port 0 is also t!e %#ltiple8ed low+order address and
data $#s d#rin& accesses to e8ternal pro&ra% and data
%e%ory.
(1). Be r #sin& pins no. ,ro% 0) to 0(.
(5). B!en #sed as an o#tp#t t!e pin latc!es are
pro&ra%%ed to 0.
(5). B!en #sed as an inp#t t!e pin latc!es are
pro&ra%%ed to 1.
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(1). Port 1 is an 8+$it $idirectional '70 port.
()). Be r #sin& pins no. ,ro% 1 to (.
(0). Port 1 !ave no d#al ,#nctions.
(1). B!en #sed as an o#tp#t t!e pin latc!es
are pro&ra%%ed to 0.
(5). B!en #sed as an inp#t t!e pin latc!es
are pro&ra%%ed to 1.
P.5/ 1
P.5/ 1
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(1). Port ) is an 8+$it $idirectional '7. port.
()). Port ) e%its t!e !i&!+order address $yte d#rin&
,etc!es ,ro% e8ternal pro&ra% %e%ory and d#rin&
accesses to e8ternal data %e%ory t!at #se 13+$it
addresses (M.<A =P/5).
(0). B!en #sed as an o#tp#t t!e pin latc!es are
pro&ra%%ed to 0.
(1). B!en #sed as an inp#t t!e pin latc!es are
pro&ra%%ed to 1.
(5). Be r #sin& pins no. ,ro% )1 to )8.
P.5/ )
P.5/ )
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(1). Port 0 is an 8+$it $i+directional '70 port.
()). Be r #sin& pins no. ,ro% 10 to 16.

5A= (P0.0)@ Serial inp#t port,

/A= (P0.1)@ Serial o#tp#t port,

'C/0 (P0.))@ E8ternal interr#pt,

'C/1 (P0.0)@ E8ternal interr#pt,

/0 /0 (P0.1)@ /i%er 0 e8ternal inp#t,

/1 (P0.5)@ /i%er 1 e8ternal inp#t,

B5 (P0.3)@ E8ternal data %e%ory write stro$e,

5= (P0.6)@ E8ternal data %e%ory read stro$e,

P.5/ 0
P.5/ 0
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/i%ers and -o#nters
/i%ers and -o#nters
(1). Many %icrocontroller applications re9#ire t!e co#ntin& o,
e8ternal events, s#c! as ,re9#ency o, a p#lse train, or t!e
&eneration o, precise internal ti%e delays $etween actions.
()). Bot! o, t!ese tasks can $e acco%plis!ed #sin& so,tware
tec!ni9#es.
(0). /!e 8051 !as two 13+$it re&isters t!at can $e #sed as eit!er
ti%ers or co#nters.
(1). /!ese two #p co#nters are na%e /0 and /1 and are provided
,or &eneral #se o, t!e pro&ra%%er.
(5). Eac! co#nter %ay $e pro&ra%%ed to co#nt internal clock
p#lses, act as a ti%er, or pro&ra%%ed to co#nt e8ternal events
as a co#nter.
(3). /!e co#nters are divided into two 8+$it re&isters called t!e
ti%er low (/>0, />1) and ti%er !i&! (/*0, /*1) $ytes.
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/-.C (/i%er7-o#nter -ontrol 5e&ister)
/-.C (/i%er7-o#nter -ontrol 5e&ister)
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/M.= (/i%er7-o#nter -ontrol
5e&ister)
/M.= (/i%er7-o#nter -ontrol
5e&ister)
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S-.C (Serial Port -ontrol
5e&ister)
S-.C (Serial Port -ontrol
5e&ister)
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P-.C (Power Mode -ontrol
5e&ister)
P-.C (Power Mode -ontrol
5e&ister)
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'nterr#pts
'nterr#pts
2n interr#pt is a special ,eat#re w!ic! 2llows t!e 8051 to provide t!e
ill#sion o, I%#ltitaskin&,J alt!o#&! in reality t!e 8051 is only doin&
one t!in& at a ti%e. /!e word Iinterr#ptI can o,ten $e s#$stit#ted
wit! t!e word Ievent.J

2n interr#pt is tri&&ered w!enever correspondin& event occ#rs. B!en
t!e event occ#rs, t!e 8051 te%porarily p#ts Ion !oldI t!e nor%al
e8ec#tion o, t!e pro&ra% and e8ec#tes a special section o, code
re,erred to as an interr#pt !andler.
B!enever any device needs its service, t!e device notiDes t!e
%icrocontroller $y sendin& it an interr#pt si&nal.
/!ere are total 5 interr#pt so#rces in 8051 Microprocessor as ,ollows.
(1). /i%er "la& 0, ()). /i%er "la& 1, (/"1 4 /") are /i%er "la&
'nterr#pts).
(0). 'C/ 0, (1). 'C/ 1, ('C/ 0 4 'C/ 1 are e8ternal interr#pts).
(5). Serial Port 'nterr#pt (5' or /').
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'nterr#pts Priorities
'nterr#pts Priorities
'nterr#pt
=estinations
'nterr#p
t
2ddress
(*e8)
1 'E0 0000*
) /"0 000B*
0 'E1 0010*
1 /"1 001B*
5 SE5'2> 00)0*
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'nterr#pt Priority ('P) S"5
'nterr#pt Priority ('P) S"5
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'nterr#pt Ena$le ('E) S"5
'nterr#pt Ena$le ('E) S"5
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EC= ."

SESS'.C
EC= ."

SESS'.C
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