Cùng Nghiên C U Avr

SU T!
M V BIN SO#N B%I NTINSIDE

Ntinside 1

CNG NGHIN C(U AVR

SU T!M V BIN SO#N B%I NTINSIDE
Ntinside 2

BI 1 - LM QUEN AVR 3
BI 2 - CU TRC AVR 14

BI 3 - NG#T NGOI 27

BI 4 TIMER - COUNTER 40

BI 5 GIAO TI$P UART 64

BI 6 - CHUY&N ()I ADC 81

BI 7 GIAO TI$P SPI 97

BI 8 GIAO TI$P TWI - I2C 110

BI 9 - KEYPAD 138

BI 10 - TEXT LCD 144

BI 11 - GRAPHIC LCD 171

BI 12 - C CHO AVR 199

BI 13 - THI$T L+P FUSE BIT 211

Ntinside 3
Bi 1 - Lm quen AVR

I. Gi-i thi0u.
AVR l m*t h- vi .i/u khi1n do hng Atmel s2n xu5t (Atmel c7ng l nh
s2n xu5t dng vi .i/u khi1n 89C51 m c th1 b:n . t;ng nghe .>n). AVR l
chip vi .i/u khi1n 8 bits v?i c5u trc tAp lBnh .@n gi2n ha-RISC(Reduced
Instruction Set Computer), m*t ki1u c5u trc .ang th1 hiBn trong cc
b* xC l.
T3i sao AVR: so v?i cc chip vi .i/u khi1n 8 bits khc, AVR c nhi/u
.Dc tnh h@n hFn, h@n c2 trong tnh Gng dHng (dI sC dHng) v .Dc biBt l v/
chGc nKng:
GLn nh< chng ta khng cLn mMc thm b5t kN linh kiBn phH no khi
sC dHng AVR, thAm ch khng cLn nguPn t:o xung clock cho chip (th<Qng
l cc khRi th:ch anh).
Thi>t bS lAp trnh (m:ch n:p) cho AVR r5t .@n gi2n, c lo:i m:ch n:p
chU cLn vi .iBn trW l c th1 lm .<Xc. m*t sR AVR cn hY trX lAp trnh on
chip bZng bootloader khng cLn m:ch n:p
Bn c:nh lAp trnh bZng ASM, c5u trc AVR .<Xc thi>t k> t<@ng
thch C.
NguPn ti nguyn v/ source code, ti liBu, application noter5t l?n
trn internet.
HLu h>t cc chip AVR c nh[ng tnh nKng (features) sau:
C th1 sC dHng xung clock ln .>n 16MHz, hoDc sC dHng
xung clock n*i ln .>n 8 MHz (sai sR 3%)
B* nh? ch<@ng trnh Flash c th1 lAp trnh l:i r5t nhi/u lLn v
dung l<Xng l?n, c SRAM (Ram t\nh) l?n, v .Dc biBt c b* nh? l<u
tr[ lAp trnh .<Xc EEPROM.
B* nh? ch<@ng trnh Flash c th1 lAp trnh l:i r5t nhi/u lLn v
dung l<Xng l?n, c SRAM (Ram t\nh) l?n, v .Dc biBt c b* nh? l<u
tr[ lAp trnh .<Xc EEPROM.
Nhi/u ng vo ra (I/O PORT) 2 h<?ng (bi-directional).
8 bits, 16 bits timer/counter tch hXp PWM.
Cc b* chuy1n .Ri Analog Digital phn gi2i 10 bits, nhi/u
knh.
Ntinside 4
ChGc nKng Analog comparator.
Giao diBn nRi ti>p USART (t<@ng thch chu]n nRi ti>p RS-
232).
Giao diBn nRi ti>p Two Wire Serial (t<@ng thch chu]n I2C)
Master v Slaver.
Giao diBn nRi ti>p Serial Peripheral Interface (SPI)
...
M*t sR chip AVR thng dHng:
AT90S1200
AT90S2313
AT90S2323 and AT90S2343
AT90S2333 and AT90S4433
AT90S4414 and AT90S8515
AT90S4434 and AT90S8535
AT90C8534
ATtiny10, ATtiny11 and ATtiny12
ATtiny15
ATtiny22
ATtiny26
ATtiny28
ATmega8/8515/8535
ATmega16
ATmega161
ATmega162
ATmega163
ATmega169
ATmega32
ATmega323
ATmega103
ATmega64/128/2560/2561
AT86RF401.
....
Trong bi vi>t ny ti sC dHng chip ATmega8 .1 lm v dH, ti ch-n
ATmega8 v .y l lo:i chip thu*c dng AVR m?i nh5t, n c .Ly .^ cc
Ntinside 5
tnh nKng câ AVR nh<ng l:i nh_ g-n (gi PDIP c 28 chn) v low cost
nn cc b:n c th1 mua .1 t` mnh t:o Gng dHng.
T3i sao Assembly (ASM): b:n c th1 khng cLn bi>t v/ c5u trc câ
AVR van c th1 lAp trnh cho AVR bZng cc phLn m/m hY trX ngn ng[ c5p
cao nh< BascomAVR (Basic) hay CodevisionAVR (C), tuy nhin . khng
ph2i l mHc .ch câ bi vi>t ny. b1 hi1u th5u .o v/ AVR b:n ph2i lAp
trnh bZng chnh ngn ng[ câ n, ASM. Nh< vAy lAp trnh bZng ASM gip
b:n hi1u t<Qng tAn v/ AVR, v t5t nhin .1 lAp trnh .<Xc bZng ASM b:n
ph2i hi1u v/ c5u trc AVR.M*t l do khc b:n m ti khuyn b:n nn lAp
trnh bZng ASM l cc trnh dSch (compiler) ASM cho AVR l hon ton
miIn ph, v nguPn source code cho AVR vi>t bZng ASM l r5t l?n. Tuy
nhin m*t khi b:n . thnh th:o AVR v ASM b:n c th1 sC dHng cc ngn
ng[ c5p cao nh< C .1 vi>t Gng dHng v <u .i1m câ ngn ng[ c5p cao l
gip b:n dI dng th`c hiBn cc php ton .:i sR 16 hay 32 bit (vRn l v5n ./
kh khKn khi lAp trnh bZng ASM).
II. Cng c5.
Trnh bin d7ch: c r5t nhi/u trnh bin dSch b:n c th1 sC dHng .> bin
dSch code câ b:n thnh file intel hex .1 n:p vo chip, m*t sR trnh dSch
quen thu*c c th1 k1 .>n nh< sau:
AvrStudio: l trnh bin dSch ASM chnh thGc cung c5p bWi Atmel, .y l trnh bin dSch hon ton
miIn ph v t5t nhin l tRt nh5t cho lAp trnh AVR bZng ASM. Phin b2n hiBn t:i l 4.18 SP1, b:n c th1
download phLn m/m AvrStudio t:itrang web chnh thGc câ Atmel hoDc b2n 4.623 t:i .y.
Wavrasm: c7ng .<Xc cung c5p bWi Atmel, n chnh l ti/n thn câ AvrStudio. HiBn t:i wavrasm
khng cn .<Xc sC dHng nhi/u v so v?i AvrStudio trnh bin dSch ny c nhi/u h:ng ch>, n>u b:n quan tm c
th1 download t:i .y.
WinAVR hay avr-gcc: l b* trnh dSch .<Xc pht tri1n bWi gnu, ngn ng[ sC dHng l C v c th1 .<Xc
dng tch hXp v?i AvrStudio (dng Avrstudio lm trnh bin tAp editor). bDc biBt b* bin dSch ny c7ng miIn
ph v .a sR nguPn source code C .<Xc vi>t bZng b* ny, v vAy n r5t l t<Wng cho b:n khi vi>t cc Gng dHng
chuyn nghiBp. ViBc lAp trnh bZng avrgcc ti sc ./ cAp trong nh[ng phLn sau.
CodeVisionAvr: m*t ch<@ng trnh bZng ngn ng[ C r5t hay cho AVR, hY trX nhi/u th< viBn lAp trnh.
Tuy nhin l ch<@ng trnh th<@ng m:i. B:n c th1 download b2n demo (.Ly .^ chGc nKng nh<ng nh<ng gi?i h:n
dung l<Xng b* nh? ch<@ng trnh 2KB) t:i Website hpinfotech
ICCAVR: lAp trnh C cho avr, download b2n demo.
BascomAVR: lAp trnh cho AVR bZng basic, .y l trnh bin dSch kh hay v dI sC dHng, hY trX r5t
nhi/u th< viBn. Tuy nhin r5t kh debug lYi v khng thch hXp cho viBc tm hi1u AVR. V vAy ti khng b:n
khuy>n khch b:n sC dHng trnh dSch ny. B:n c th1 download b2n demo (4K limit).
Ntinside 6
V cn r5t nhi/u trnh bin dSch khc cho AVR m ti khng k1 ra .y, nhn chung t5t c2 cc trnh bin
dSch ny hY trX C hoDc Basic hoDc thAm ch Pascal. ViBc ch-n 1 trnh bin dSch ty thu*c vo mHc .ch, vo mGc
.* Gng dHng, vo kinh nghiBm sC dHng v nhi/u l do khc n[a. V dH ti th<Qng dng Avrstudio v avrgcc khi
h-c sC dHng AVR v khi vi>t th< viBn. Nh<ng khi cLn vi>t ch<@ng trnh Gng dHng ti th<Qng ch-n avrgcc v
CodeVisionAVR.
Trong bi vi>t ny ti h<?ng dan b:n sC dHng AvrStudio .1 vi>t ch<@ng
trnh cho AVR bZng ASM.
Ch9.ng trnh n3p (Chip Programmer): .a sR cc trnh bin dSch
(AvrStudio, CodeVisionAVR, Bascom) ./u tch hXp sdn 1 ch<@ng trnh
n:p chip hY trX nhi/u lo:i m:ch n:p nn b:n khng qu lo lMng. Trong
tr<Qng hXp khc, b:n c th1 sC dHng cc ch<@ng trnh n:p nh< Icprog hay
Ponyprogl cc ch<@ng trnh n:p miIn ph cho AVR. ViBc ch-n v sC
dHng ch<@ng trnh n:p sc .<Xc gi?i thiBu trong cc bi sau.
M3ch n3p: tham kh2o bi vi>t gi?i thiBu m:ch n:p AVR.
Ch9.ng trnh m ph:ng: avr simulator l trnh m ph_ng v debbug
.<Xc tch hXp sdn trong Avrstudio, avr simulator cho php b:n quan st
tr:ng thi cc thanh ghi bn trong AVR nn r5t ph hXp .1 b:n debug
ch<@ng trnh. Proteus l ch<@ng trnh thG hai ti muRn ni .>n, Proteus
khng nh[ng m ph_ng ho:t .*ng bn trong chip m cn m ph_ng m:ch
.iBn tC. Proteus m ph_ng r5t tr`c quan, n l 1 cng cH h[u ch khi cc b:n
ch<a c .i/u kiBn lm cc m:ch .iBn tC.
III. V d5 =>u tin c?a b3n.
Sau khi download AvrStudio, b:n hy ci .Kt phLn m/m trn my câ
b:n, qu trnh ci .Dt r5t .@n gi2n, b:n hy theo cc mDc .Snh v nh5n next
.1 ci .Dt. Trong bi .Lu tin ny chng ta sc vi>t thC 1 ch<@ng trnh .@n
gi2n cho AVR sau . ch:y m ph_ng bZng Proteus. C th1 c m*t sR cu
lBnh cc b:n sc khng hi1u, nh<ng .;ng lo lMng qu, trong bi thG 2 chng
ta sc h-c v/ c5u trc AVR cc b:n sc .<Xc gi2i thich r h@n.
b1 th`c hiBn v dH ny, b:n hy t:o m*t Project bZng AVRStudio, phLn
h<?ng dan chi ti>t cho viBc t:o Project trong AVRStudio b:n hy tham kh2o
W bi h<?ng dan AVRStudio.bo:n code v dH trong bi .Lu tin ny .<Xc
trnh by trong List1.
List 1. bo:n code .Lu tin câ b:n.
1
2
.CSEG
.INCLUDE "M8DEF.INC"
Ntinside 7
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
.ORG 0x000
RJMP BATDAU

.ORG 0x020
BATDAU:
; KHOI TAO CAC DIEU KIEN DAU
LDI R16, HIGH(RAMEND)
LDI R17, LOW(RAMEND)
OUT SPH, R16
OUT SPL, R17
LDI R16, 0xFF;
OUT DDRB, R16

; CHUONG TRINH CHINH
MAIN:
LDI R16, 0B00000001
OUT PORTB, R16
RCALL DELAY

LDI R16, 0B00000010
OUT PORTB, R16
RCALL DELAY

LDI R16, 0B00000100
OUT PORTB, R16
RCALL DELAY

LDI R16, 0B00001000
OUT PORTB, R16
RCALL DELAY

LDI R16, 0B00010000
OUT PORTB, R16
RCALL DELAY

LDI R16, 0B00100000
OUT PORTB, R16
RCALL DELAY

Ntinside 8
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
LDI R16, 0B01000000
OUT PORTB, R16
RCALL DELAY

LDI R16, 0B10000000
OUT PORTB, R16
RCALL DELAY

RJMP MAIN
; CHUONG TRING CON DELAY 65535 chu ky (khoang 65535us
neu xung ;clock cho chip la 1M)
DELAY:
LDI R20, 0xFF
DELAY0:
LDI R21, 0xFF
DELAY1:
DEC R21
BRNE DELAY1
DEC R20
BRNE DELAY0
RET
Tr<?c khi tm hi1u ngh\a .o:n code, hy nhn 1 l<Xt qua .o:n code.
Tr<?c h>t viBc vi>t HOA hay vi>t th<Qng l khng quan tr-ng, b:n c th1
vi>t .o:n code v?i b5t cG hnh thGc no miIn .ng c php, t; kha l .<Xc.
Trong .o:n code:
B:n th5y 1 sR t; c mu BLUE (v dH LDI, OUT, RJMP, RCALL, RET). l cc INSTRUCTiON,
tGc l cc cu lBnh câ ngn ng[ ASM, b:n c th1 .-c ti liBu AVR INSTRUCTION .1 tm hi1u t5t c2 cc
INSTRUCTION. Cc INSTRUCTION sau . sc .<Xc trnh dSch dSch thnh cc m t<@ng Gng.
M*t sR t; bMt .Lu bZng bZng d5u ch5m . l cc DIRECTIVE (v dH .INCLUDE hay .ORG ). c7ng l
nh[ng t; kha mDc .Snh câ ASM AVR, cc DIRECTIVE khng ph2i l m lBnh m chU l cc chU dan v/ .Sa chU
b* nh?, khWi .*ng b* nh?, .Snh ngh\a macrov khng .<Xc trnh dSch dSch thnh m. Chi ti>t v/ DIRECTIVE
c th1 tm th5y trong cc ti liBu v/ ASM AVR, d<?i .y ti tm tMt cc DIRECTIVE v chGc nKng câ chng
nh< sau:
Ntinside 9

Thng th<Qng 1 INSTRUCTION .<Xc theo sau bWi 2 ton h:ng operand (tuy nhin c nhi/u tr<Qng
hXp chU c 1 ton h:ng hoDc khng c ton h:ng), khi . ton h:ng thG nh5t sc l cc THANH GHI. câ AVR
(nh< . ./ cAp, chng ta sc kh2o st thanh ghi AVR trong cc bi sau), v dH : LDI R16, 0xFF; trong . ton
h:ng R16 l tn 1 thanh ghi trong AVR, v 0xFF l 1 hZng sR d:ng hexadecimal c gi trS t<@ng Gng l 255
d:ng thAp phn hay 11111111 nhS phn.
Cc t; theo sau bWi d5u : l cc nhn label (v dH MAIN, DELAY), . l t; do chng ta t` .Dt,
n th`c ch5t l 1 vS tr trong b* nh? ch<@ng trnh, c th1 sC dHng nhn nh< 1 ch<@ng trnh con.
PhLn .i sau d5u ; g-i l gi2i thch comment, phLn ny khng .<Xc bin dSch, b:n c th1 ghi
comment W b5t cG .u trong ch<@ng trnh v?i yu cLu ph2i sC dHng d5u ; tr<?c n.
Gi@i thch =o3n code:c th1 chia .o:n code trn thnh 4 phLn: phLn .Lu
chGa cc DIRECTIVE v lBnh RJMP dng .1 xc .Snh cc .Sa chU b* nh?
ch<@ng trnh, phLn 2 l khWi t:o m*t sR .i/u kiBn .Lu cho Stack Pointer v
PORT, phLn 3 l ch<@ng trnh chnh, v phLn 4 l ch<@ng trnh con ( ch
.y chU l cch bR tr câ ring ti, m*t khi . quen thu*c, b:n c th1 bR tr
ch<@ng trnh theo cch ring câ b:n).
PhLn 1 v phLn 2:
.CSEG
ChU thS .CSEG: Code Segment bo cho trnh bin dSch rZng phLn code theo sau l phLn ch<@ng trnh th`c thi,
phLn ny sc .<Xc download vo b* nh? ch<@ng trnh câ chip.
Ntinside 10
ChU thS .INCLUDE bo cho trnh bin dSch bMt .Lu .-c 1 file .nh km, trong tr<Qng hXp trn l file
M8DEF.INC, .y l file chGa cc khai bo cho chip Atmega8 nh< thanh ghi, ngMtcho viBc truy xu5t trong
ch<@ng trnh câ b:n, .y l dng bMt bu*c, n>u b:n lAp trnh cho chip khc b:n hy .ei tn file .nh km, v dH
m32def.inc cho chip ATmega32 b:n c th1 tm th5y cc file ny trong th< mHc C:\Program
Files\Atmel\AVR Tools\AvrAssembler2\Appnotes.
.ORG 0x000
ChU thS .ORG: Set Program Origin, set vS tr trong b* nh? sc .<Xc tc .*ng .>n, trong tr<Qng hXp trn, .ORG
0x000 xc .Snh phLn code theo ngay sau sc nZm W .Sa chU 000, vS tr .Lu tin, trong b* nh? ch<@ng trnh. V
dng lnh trong vS tr .Lu tin . l:
RJMP BATDAU
RJMP: Relative Jump l lBnh nh2y khng .i/u kiBn .>n 1 vS tr trong b* nh?, trong tr<Qng hXp trn l nh2y .>n
nhn BATDAU, v nhn BATDAU nZm W vS tr 0x020 (sR hexadecimal, 0x020 =32 decimal) v n .<Xc khai
bo ngay sau DIRECTIVE .ORG 0x020.
.ORG 0x020
BATDAU
Nh< th> phLn b* nh? ch<@ng trnh nZm gi[a 0 v 0x020 khng .<Xc sC dHng trong .o:n code câ chng ta, phLn
ny .<Xc sC dHng cho mHc .ch khc, . l cc vect@ ngMt ( khng .<Xc ./ cAp W .y). Ti>p theo:
; KHOI TAO CC DIEU KIEN DAU
OUT SPH, R16
OUT SPL, R17
BRn dng code trn khWi t:o cho Stack Pointer, chng ta sc tm hi1u phLn ny trong cc bi v/ Stack v ch<@ng
trnh con.
LAi khuyn: cc b3n nn khCi =Dng 1 ch9.ng trnh theo cch trn v chng ta sE hiGu chng r h.n sau
ny !
LDI R16, 0xFF
OUT DDRB, R16
Ntinside 11
B:n ch 2 dng trn v nh[ng g ti gi2i thch sau .y, 2 dng ny c tc dHng khWi .*ng PORTB câ chip
ATmega8 tc dHng nh< cc ng xu5t tn hiBu (OUTPUT). Tr<?c h>t hy quan st chip ATmega8 trong hnh sau

Hnh 1: chip ATmega8.
B:n c th1 th5y chip ny gPm 28 chn, trng . c cc chn .<Xc ghi l PB0(chn 14), PB1(chn
15),,PB7(chn 10), . l cc chn câ PORTB. PORT l khi niBm chU cc ng xu5t nhAp. Trong AVR, PORT
c th1 giao ti>p theo 2 h<?ng (bi directional), c th1 dng .1 xu5t hoDc nhAn thng tin, mYi PORT c 8 chn.
Chip Atmega8 c 3 PORT c tn t<@ng Gng l PORTB, PORTC v PORTD (m*t sR chip AVR khc c 4 hoDc 6
PORT). PORT .<Xc coi l cCa ng then chRt câ vi .i/u khi1n.
Trong AVR, mYi PORT lin quan .>n 3 thanh ghi (8 bits) c tn t<@ng Gng l DDRx, PINx, v PORTx v?i x
l tn câ PORT, mYi bit trong thanh ghi t<@ng Gng v?i mYi chn câ PORT. Trong tr<Qng hXp câ Atmega8
x l B, C hoDc D. V dH chng ta quan tm .>n PORTB th 3 thanh ghi t<@ng Gng c tn l DDRB, PINB v
PORTB, trong . 2 thanh ghi PORTB v PINB .<Xc nRi tr`c ti>p v?i cc chn câ PORTB, DDRB l thanh ghi
.i/u khi1n h<?ng ( Input hoDc Output). Vi>t gi trS 1 vo m*t bit trong thanh ghi DDRB th chn t<@ng Gng câ
PORTB sc l chn xu5t (Output), ng<Xc l:i gi trS 0 xc lAp chn t<@ng Gng l ng nhAp. Sau khi vi>t gi trS .i/u
khi1n vo DDRB, viBc truy xu5t PORTB .<Xc th`c hiBn thng qua 2 thanh ghi PINB v PORTB.
Quay l:i v?i 2 dng code câ chng ta, dng .Lu: LDI R16, 0xFF, v?i LDI LoaD Immediately, dng lBnh c
ngh\a l load gi trS 0xFF vo thanh ghi R16, R16 l tn 1 thanh ghi trong b* nh? câ AVR, 0xFF l 1 hZng sR
c d:ng thAp lHc phn, k hiBu 0x ni ln .i/u ., b:n c7ng c th1 dng k hiBu khc l $ .1 chU 1 sR thAp
lHc phn, v dH &FF, v 0xFF=255(thAp phn)=0B11111111 (nhS phn). Nh< th> sau dng .Lu thanh ghi R16 c
gi trS l 11111111 (nhS phn). Dng thG 2: OUT DDRB, R16 ngh\a l xu5t gi trS t; thanh ghi R16 ra thanh
ghi DDRB, tm l:i sau 2 dng trn gi trS DDRB nh< sau:
1 1 1 1 1 1 1 1
Ntinside 12
C th1 b:n sc h_i t2i sao chng khng sC dHng 1 dng duy nh5t l LDI DDRB, 0xFF hay OUT DDRB,
0xFF, chng ta khng th1 v lBnh LDI chU cho php th`c hiBn trn cc thanh ghi R16,R31 v lBnh OUT khng
th`c hiBn .<Xc v?i cc hZng sR.
V v DDRB=11111111 nn trong tr<Qng hXp ny t5t c2 cc chn câ PORTB . sdn sng cho viBc xu5t d[ liBu.
Lc ny thanh ghi PINB khng c tc dHng, thanh ghi PORTB sc l thanh ghi xu5t, ghi gi trS vo thanh ghi ny
sc tc .*ng .>n cc chn câ PORTB.1
PhLn 3: Ch<@ng trnh chnh
MAIN:
LDI R16, 0B00000001
OUT PORTB, R16
RCALL DELAY
B:n chU cLn ch 4 dng trn trong ton b* phLn ch<@ng trnh chnh, tr<?c h>t MAIN: chU l 1 nhn do chng
ta t` .Dt tn, giRng nh< 1 c*t mRc trong ch<@ng trnh thi. Dng LDI R16, 0B00000001 th b:n . hi1u, chU
c 1 khc biBt nh_ l ti sC dHng hZng sR d:ng nhS phn cho b:n dI hi1u h@n. V dng OUT PORTB, R16 .1
xu5t gi trS 0B00000001 c sdn trong R16 ra thanh ghi PORTB, lc ny chn PB0 câ chip sc ln 1 (5V) v cc
chn cn l:i sc W mGc 0 (0V). Dng thG 3: RCALL DELAY l lBnh g-i ch<@ng trnh con DELAY, t:m hon
tr<?c khi th`c hiBn cc dng lBnh ti>p theo:
LDI R16, 0B00000010
OUT PORTB, R16
RCALL DELAY
Ba dng lBnh ny c7ng giRng ba dng trn, nh<ng gi trS xu5t ra lc ny l 0B00000010, chn PB1 sc ln 5V v
cc chn khc xuRng mGc 0V. V cG nh< th> .>n .o:n cuRi:
LDI R16, 0B10000000
OUT PORTB, R16
RCALL DELAY
RJMP MAIN
Sau khi k>t thGc 3 dng trn chn PB7 sc ln 5V, k>t thc 1 vng
xoay. CuRi cng l quay v> .Lu ch<@ng trnh chnh bZng dng RJMP
MAIN
By giQ chMc b:n . .on .<Xc ch<@ng trnh câ chng ta th`c hiBn viBc g, . l qut xoay vng cc
chn câ PORTB, n>u chng ta k>t nRi cc chn câ PORTB v?i cc LED, chng ta sc c 1 hiBu Gng qut LED
xoay vng, chng ta th`c hiBn .i/u ny bZng phLn m/m Proteus.
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PhLn 4: ch<@ng trinh con DELAY: .o:n ch<@ng trnh ny khng lm g c2 ngoi viBc tr hon 1
kho2ng thQi gian, tuy nhin b:n ch<a th1 hi1u n ngay .<Xc.
by chU l 1 v dH .@n gi2n, ti cR gMng th`c hiBn n theo cch dI hi1u nh5t cho b:n, v th> .o:n code c vf h@i
di dng, b:n hy th`c hiBn l:i .o:n ch<@ng trnh chnh bZng .o:n code câ b:n.
Ph>n cuIi cng l bin d7ch =o3n code thnh file intel hex =G =K vo chip, nhLn phm F7 =G bin d7ch.
Sau khi bin dSch b:n sc c 1 file tn avr1.hex trong th<c mHc project, chng ta sc dng file ny .e vo chip
sau ny.
IV. M ph:ng bMng Proteus.
Chng ta hy thC nghiBm .o:n ch<@ng trnh câ chng ta bZng Proteus.
N>u b:n th`c hiBn .ng k>t qu2 sc nh< minh h-a trong hnh 2 H<?ng dan
cH th1 cch vc m:ch .iBn v m ph_ng bZng phLn m/m Proteus b:n hy xem
bi "M ph_ng Proteus".

Hnh 2. M ph_ng.

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Bi 2 - Cu Trc AVR

I. Gi-i thi0u.
Bi ny ti>p tHc bi .Lu tin trong lo:t bi gi?i thiBu v/ AVR, n>u sau
bi "Lm quen AVR" b:n . phLn no bi>t cch lAp trnh cho AVR bZng
AVRStudio th trong bi ny, chng ta sc tm hi1u kg h@n v/ c5u trc câ
AVR. Sau bi ny, b:n sc:
Hi1u .<Xc c5u trc AVR, c5u trc b* nh? v cch thGc ho:t .*ng câ
chip.
Hi1u v/ Stack v cch ho:t .*ng.
Bi>t .<Xc m*t sR instruction c@ b2n truy xu5t b* nh?.
H-c cc instruction rc nhnh v vng lDp.
Ch<@ng trnh con (Subroutine) v Macro.
C2i ti>n v dH trong bi 1.
Vi>t 1 v dH minh h-a cch sC dHng b* nh? v vng lDp.
II. TK chOc c?a AVR.
AVR c c5u trc Harvard, trong . .<Qng truy/n cho b* nh? d[ liBu
(data memory bus) v .<Qng truy/n cho b* nh? ch<@ng trnh (program
memory bus) .<Xc tch ring. Data memory bus chU c 8 bit v .<Xc k>t nRi
v?i hLu h>t cc thi>t bS ngo:i vi, v?i register file. Trong khi . program
memory bus c .* r*ng 16 bits v chU phHc vH cho instruction registers.
Hnh 1 m t2 c5u trc b* nh? câ AVR.
BD nh- ch9.ng trnh (Program memory): L b* nh? Flash lAp trnh
.<Xc, trong cc chip AVR c7 (nh< AT90S1200 hay AT90S2313) b* nh?
ch<@ng trnh chU gPm 1 phLn l Application Flash Section nh<ng trong cc
chip AVR m?i chng ta c thm phLn Boot Flash setion. Boot section sc
.<Xc kh2o st trong cc phLn sau, trong bi ny khi ni v/ b* nh? ch<@ng
trnh, chng ta t` hi1u l Application section. Th`c ch5t, application section
bao gPm 2 phLn: phLn chGa cc instruction (m lBnh cho ho:t .*ng câ chip)
v phLn chGa cc vector ngMt (interrupt vectors). Cc vector ngMt nZm W phLn
.Lu câ application section (t; .Sa chU 0x0000) v di .>n bao nhiu ty
thu*c vo lo:i chip. PhLn chGa instruction nZm li/n sau ., ch<@ng trnh vi>t
cho chip ph2i .<Xc load vo phLn ny. Xem l:i phLn .Lu câ v dH trong bi
1:
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.ORG 0x000
RJMP BATDAU
.ORG 0x020
Trong v dH ny, ngay sau khi set vS tr 0x000 bZng chU thS
(DIRECTIVE) .ORG 0x000 chng ta dng instruction RJMP .1 nh2y .>n vS
tr 0x020, nh< th> phLn b* nh? ch<@ng trnh t; 0x00 .>n 0x01F khng .<Xc
sC dHng (v trong v dH ny chng ta khng sC dHng cc vector ngMt).
Ch<@ng trnh chnh .<Xc bMt .Lu t; .Sa chU 0x020, con sR 0x020 l do ng<Qi
lAp trnh ch-n, thAt ra cc vector ngMt câ chip ATMEGA8 chU ko di .>n
.Sa chU 0x012, v vAy ch<@ng trnh chnh c th1 .<Xc bMt .Lu t; b5t cG vS tr
no sau .. b1 bi>t .* di cc vector ngMt câ t;ng chip b:n hy tham kh2o
datasheet câ chip ..
V chGc nKng chnh câ b* nh? ch<@ng trnh l chGa instruction, chng
ta khng c nhi/u c@ h*i tc .*ng ln b* nh? ny khi lAp trnh cho chip, v
th> .Ri v?i ng<Qi lAp trnh AVR, b* nh? ny khng qu quan tr-ng. T5t c2
cc thanh ghi quan tr-ng cLn kh2o st nZm trong b* nh? d[ liBu câ chip.

Hnh 1. Te chGc b* nh? câ AVR.
BD nh- dP li0u (data memory): by l phLn chGa cc thanh ghi quan
tr-ng nh5t câ chip, viBc lAp trnh cho chip phLn l?n l truy cAp b* nh? ny.
B* nh? d[ liBu trn cc chip AVR c .* l?n khc nhau ty theo mYi chip,
tuy nhin v/ c@ b2n phLn b* nh? ny .<Xc chia thnh 5 phLn:
Ph>n 1: l phLn .Lu tin trong b* nh? d[ liBu, nh< m t2 trong hnh 1,
phLn ny bao gPm 32 thanh ghi c tn g-i l register file (RF), hay General
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Purpose Rgegister GPR, hoDc .@n gi2n l cc Thanh ghi. T5t c2 cc thanh
ghi ny ./u l cc thanh ghi 8 bits nh< trong hnh 2.

Hnh 2. Thanh ghi 8 bits.
T5t c2 cc chip trong h- AVR ./u bao gPm 32 thanh ghi Register File c
.Sa chU tuyBt .Ri t; 0x0000 .>n 0x001F. MYi thanh ghi c th1 chGa gi trS
d<@ng t; 0 .>n 255 hoDc cc gi trS c d5u t; -128 .>n 127 hoDc m ASCII
câ m*t k t` no .Cc thanh ghi ny .<Xc .Dt tn theo thG t` l R0 .>n
R31. Chng .<Xc chia thnh 2 phLn, phLn 1 bao gPm cc thanh ghi t; R0
.>n R15 v phLn 2 l cc thanh ghi R16 .>n R31. Cc thanh ghi ny c cc
.Dc .i1m sau:
b<Xc truy cAp tr`c ti>p trong cc instruction.
Cc ton tC, php ton th`c hiBn trn cc thanh ghi ny chU cLn 1 chu
kN xung clock.
Register File .<Xc k>t nRi tr`c ti>p v?i b* xC l trung tm CPU câ
chip.
Chng l nguPn chGa cc sR h:ng trong cc php ton v c7ng l .ch
chGa k>t qu2 tr2 l:i câ php ton.
b1 minh h-a, hy xt v dH th`c hiBn php c*ng 2 thanh ghi bZng instruction
ADD nh< sau:
ADD R1, R2
B:n th5y trong dng lBnh trn, 2 thanh ghi R1 v R2 .<Xc sC dHng tr`c ti>p v?i tn câ chng, dng lBnh
trn khi .<Xc dSch sang opcode .1 download vo chip sc c d:ng: 0000110000010010 trong . 00001=1 tGc
thanh ghi R1 v 00010 = 2 chU thanh ghi R2. Sau php c*ng, k>t qu2 sc .<Xc lp trong 1
chu kN xung clock, ngo:i tr; SBCI, SUBI, CPI, ANDI v LDI, cc instruction ny chU c th1 truy nhAp cc thanh
ghi t; R16 .>n R31.
Thanh ghi R0 l thanh ghi duy nh5t .<Xc sC dHng trong instruction LPM (Load Program Memory). Cc thanh
ghi R26, R27, R28, R29, R30 v R31 ngoi chGc nKng thng th<Qng cn .<Xc sC dHng nh< cc con tr_ (Pointer
register) trong m*t sR instruction truy xu5t gin ti>p. Chng ta sc kh2o st v5n ./ con tr_ sau ny. Hnh 3 m t2
cc chGc nKng phH câ cc thanh ghi.
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Hnh 3. Register file.
Tm l:i 32 RF câ AVR .<Xc xem l 1 phLn câ CPU, v th> chng .<Xc CPU sC dHng tr`c ti>p v nhanh
chng, .1 g-i cc thanh ghi ny, chng ta khng cLn g-i .Sa chU m chU cLn g-i tr`c ti>p tn câ chng. RF
th<Qng .<Xc sC dHng nh< cc ton h:ng (operand) câ cc php ton trong lc lAp trnh.
Ph>n 2: l phLn nZm ngay sau register file, phLn ny bao gPm 64 thanh ghi .<Xc g-i l 64 thanh ghi
nhAp/xu5t (64 I/O register) hay cn g-i l vng nh? I/O (I/O Memory). Vng nh? I/O l cCa ng giao ti>p gi[a
CPU v thi>t bS ngo:i vi. T5t c2 cc thanh ghi .i/u khi1n, tr:ng thicâ thi>t bS ngo:i vi ./u nZm W .y. Xem
l:i v dH trong bi 1, trong . ti c ./ cAp v/ viBc .i/u khi1n cc PORT câ AVR, mYi PORT lin quan .>n 3
thanh ghi DDRx, PORTx v PINx, t5t c2 3 thanh ghi ny ./u nZm trong vng nh? I/O. Xa h@n, n>u muRn truy
xu5t cc thi>t bS ngo:i vi khc nh< Timer, chuy1n .ei Analog/Digital, giao ti>p USART./u th`c hiBn thng
qua viBc .i/u khi1n cc thanh ghi trong vng nh? ny.
Vng nh I/O c th# '()c truy c+p nh( SRAM hay nh( cc thanh ghi I/O. N-u s/ d1ng instruction truy xu3t
SRAM '# truy xu3t vng nh ny th '4a ch6 c8a chng '()c tnh t9 0x0020 '-n 0x005F. Nh(ng n-u truy xu3t
nh( cc thanh ghi I/O th '4a ch6 c8a chng ';!c tnh t9 0x0000 '-n 0x003F.
Xt v dH instruction OUT dng xu5t gi trS ra cc thanh ghi I/O, lBnh ny sC dHng .Sa chU ki1u thanh ghi, c5u
trc câ lBnh nh< sau: OUT A, Rr, trong . A l .Sa chU câ thanh ghi trong vng nh? I/O, Rr l thanh ghi RF,
lBnh OUT xu5t gi trS t; thanh ghi Rr ra thanh ghi I/O c .Sa chU l A. Gi2 sC chng ta muRn xu5t gi trS chGa
trong R6 ra thanh ghi .i/u khi1n h<?ng câ PORTD, tGc thanh ghi DDRD, .Sa chU tnh theo vng I/O câ thanh
ghi DDRD l 0x0011, nh< th> cu lBnh câ chng ta sc c d:ng: OUT 0x0011, R6. Tuy nhin trong 1 tr<Qng hXp
khc, n>u muRn truy xu5t DDRD theo d:ng SRAM, v dH lBnh STS hay LDS, th ph2i dng .Sa chU tuyBt .Ri câ
thanh ghi ny, tGc gi trS 0x0031, khi . lBnh OUT W trn .<Xc vi>t l:i l STS 0x0031, R6.
<# th>ng nh3t cch s/ d1ng t9 ng@, t9 by giB chng ta dng khi niCm '4a ch6 I/O cho cc thanh ghi
trong vng nh I/O '# ni '-n '4a ch6 khng tnh phDn Register File, khi niCm '4a ch6 bE nh c8a thanh ghi
l ch6 '4a ch6 tuyCt '>i c8a chng trong SRAM. V d1 thanh ghi DDRD c '4a ch6 I/O l 0x0011 v '4a ch6 bE
nh c8a n l 0x0031, '4a ch6 bE nh = '4a ch6 I/O + 0x0020.
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V cc thanh ghi trong vng I/O khng .<Xc hi1u theo tn g-i nh< cc Register file, khi lAp trnh cho cc
thanh ghi ny, ng<Qi lAp trnh cLn nh? .Sa chU câ t;ng thanh ghi, .y l viBc t<@ng .Ri kh khKn. Tuy nhin,
trong hLu h>t cc phLn m/m lAp trnh cho AVR, .Sa chU câ t5t c2 cc thanh ghi trong vng I/O ./u .<Xc .Snh
ngh\a tr<?c trong 1 file Definition, b:n chU cLn .nh km file ny vo ch<@ng trnh câ b:n l c th1 truy xu5t cc
thanh ghi v?i tn g-i câ chng. Gi2 sC trong v dH W bi 1, .1 lAp trnh cho chip Atmega8 bZng AVRStudio,
dng thG 2 chng ta sC dHng INCLUDE "M8DEF.INC" .1 load file .Snh ngh\a cho chip ATMega8, file
M8DEF.INC. V vAy, trong sau ny khi muRn sC dHng thanh ghi DDRD b:n chU cLn g-i tn câ chng,
nh<: OUT DDRD,R6.
Ph>n 3: RAM t\nh, n*i (internal SRAM), l vng khng gian cho chGa cc bi>n (t:m thQi hoDc ton cHc)
trong lc th`c thi ch<@ng trnh, vng ny t<@ng t` cc thanh RAM trong my tnh nh<ng c dung l<Xng kh nh_
(kho2ng vi KB, ty thu*c vo lo:i chip).
Ph>n 4: RAM ngo:i (external SRAM), cc chip AVR cho php ng<Qi sC dHng gMn thm cc b* nh? ngoi .1
chGa bi>n, vng ny th`c ch5t chU tPn t:i khi no ng<Qi sC dHng gMn thm b* nh? ngoi vo chip.
Ph>n 5: EEPROM (Electrically Ereasable Programmable ROM) l m*t phLn quan tr-ng câ cc chip AVR
m?i, v l ROM nn b* nh? ny khng bS xa ngay c2 khi khng cung c5p nguPn nui cho chip, r5t thch hXp cho
cc Gng dHng l<u tr[ d[ liBu. Nh< trong hnh 1, phLn b* nh? EEPROM .<Xc tch ring v c .Sa chU tnh t;
0x0000.
Cu h:i by giA l AVR ho3t =Dng nh9 thQ no?
Hnh 4 bi1u diIn c5u trong bn trong câ 1 AVR. B:n th5y rZng 32 thanh ghi trong Register File .<Xc k>t nRi
tr`c ti>p v?i Arithmetic Logic Unit -ALU (ALU c7ng .<Xc xem l CPU câ AVR) bZng 2 line, v th> ALU c
th1 truy xu5t tr`c ti>p cng lc 2 thanh ghi RF chU trong 1 chu kN xung clock (vng .<Xc khoanh trn mu ._
trong hnh 4).

Hnh 4. C5u trc bn trong AVR.
Cc instruction .<Xc chGa trong b* nh? ch<@ng trnh Flash memory d<?i d:ng cc thanh ghi 16 bit. B* nh?
ch<@ng trnh .<Xc truy cAp trong mYi chu kN xung clock v 1 instruction chGa trong program memory sc .<Xc
load vo trong instruction register, instruction register tc .*ng v là ch-n register file c7ng nh< RAM cho
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ALU th`c thi. Trong lc th`c thi ch<@ng trnh, .Sa chU câ dng lBnh .ang th`c thi .<Xc quy>t .Snh bWi m*t b*
.>m ch<@ng trnh PC (Program counter). b chnh l cch thGc ho:t .*ng câ AVR.
AVR c t cc instruction ./u .<Xc th`c thi trong 1 chu kN xung clock, v vAy c th1 nguPn
clock l?n nh5t cho AVR c th1 nh_ h@n 1 sR vi .i/u khi1n khc nh< PIC nh<ng thQi gian th`c thi van nhanh h@n.
III. Stack.
Stack .<Xc hi1u nh< l 1 thp d[ liBu, d[ liBu .<Xc chGa vo stack W .Unh thp v d[ liBu c7ng .<Xc l5y
ra t; .Unh. Ki1u truy cAp d[ liBu câ stack g-i l LIFO (Last In First Out vo sau ra tr<?c). Hnh 5 th1 hiBn
cch truy cAp d[ liBu câ stack.

Hnh 5. Stack.
Khi niBm v cch thGc ho:t .*ng câ stack c th1 .<Xc p dHng cho AVR, bZng cch khai bo m*t vng
nh? trong SRAM l stack ta c th1 sC dHng vng nh? ny nh< m*t stack th`c thH.
b1 khai bo m*t vng SRAM lm stack chng ta cLn xc lAp .Sa chU .Lu câ stack bZng cch xc lAp con tr_
stack-SP (Stack Pointer). SP l 1 con tr_ 16 bit bao gPm 2 thanh ghi 8 bit SPL v SPH (ch[ L l LOW chU thanh
ghi mang gi trS byte th5p câ SP, v H = HIGH), SPL v SPH nZm trong vng nh? I/O. Gi trS gn cho thanh
ghi SP sc l .Sa chU khWi .*ng câ stack. Quay l:i v dH W bi 1, phLn khWi t:o cc .i/u kiBn .Lu.
; KHOI TAO CC DIEU KIEN DAU
OUT SPH, R16
OUT SPL, R17
BRn dng khai bo trn mHc .ch l gn gi trS câ RAMEND cho con tr_ SP, RAMEND (tGc End of Ram)
l bi>n chGa .Sa chU l?n nh5t câ RAM n*i trong AVR, bi>n ny .<Xc .Snh ngh\a trong file M8DEF.INC. Nh<
th> sau 4 dng trn, con tr_ SP chGa gi trS cuRi cng câ SRAM hay ni cch khc vng stack bMt .Lu t; vS tr
cuRi cng câ b* nh? SRAM. Nh<ng t:i sao l vS tr cuRi cng m khng l 1 gi trS khc. C th1 gi2i thch nh<
sau: stack trong AVR ho:t .*ng t; trn xuRng, sau khi d[ liBu .<Xc .]y vo stack, SP sc gi2m gi trS v th> khWi
.*ng SP W vS tr cuRi cng câ SRAM sc trnh .<Xc viBc m5t d[ liBu do ghi .. B:n c th1 khWi .*ng stack v?i 1
.Sa chU khc, tuy nhin v l do an ton, nn khWi .*ng stack W RAMEND.
Hai instruction dng cho truy cAp stack l PUSH v POP, trong . PUSH dng .]y d[ liBu vo stack v POP
dng l5y d[ liBu ra kh_i stack. D[ liBu .<Xc .]y vo v l5y ra kh_i stack t:i vS tr m con tr_ SP tr_ .>n. V dH
cho chip ATMega8, RAMEND=0x045F, sau khi khWi .*ng, con tr_ SP tr_ .>n vS tr 0x045F trong SRAM, n>u ta
vi>t cc cu lBnh sau:

LDI R1, 1
PUSH R1
LDI R1, 5
PUSH R1
LDI R1, 8
PUSH R1
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Khi . n*i dung câ stack sc nh< trong hnh 6.

Hnh 6. N*i dung stack trong v dH.
Sau mYi lLn PUSH d[ liBu, SP sc gi2m 1 .@n vS v tr_ vo vS tr ti>p theo.
By giQ n>u ta dng POP .1 l5y d[ liBu t; stack, POP R2, th R2 sc mang gi trS câ ngKn nh? 0x045D, tGc
R2=8. Tr<?c khi instruction POP .<Xc th`c hiBn, con tr_ SP .<Xc tKng ln 1 .@n vS, sau . d[ liBu sc .<Xc l5y
ra t; vS tr m SP tr_ .>n trong stack.
Stack trong AVR khng ph2i l v .y, ngh\a l chng ta chU c th1 PUSH d[ liBu vo stack W 1 .* su
nh5t .Snh no .5y (phH thu*c vo chip). SC dHng stack khng .ng cch .i khi sc lm ch<@ng trnh th`c thi sai
hoDc tRn thQi gian th`c thi v ch. V th> khng nn sC dHng stack chU .1 ln thng th<Qng. (ng dHng
phe bi>n nh5t câ stack l sC dHng trong cc ch<@ng trnh con (Subroutine), khi chng ta cLn nh2y t; m*t vS tr
trong ch<@ng trnh chnh .>n 1 ch<@ng trnh con, sau khi th`c hiBn ch<@ng trnh con l:i muRn quay v/ vS tr ban
.Lu trong ch<@ng trnh chnh th Stack l ph<@ng cch tRi m ch<@ng trnh trong tr<Qng
hXp ny. Xem l:i v dH trong bi 1, trong ch<@ng trnh chnh chng ta dng lBnh RCALL DELAY .1 nh2y .>n
.o:n ch<@ng trnh con DELAY, RCALL l lBnh nh2y .>n 1 vS tr trong b* nh? ch<@ng trnh, tr<?c khi nh2y, PC
.<Xc c*ng thm 1 v PUSH m*t cch t` .*ng vo stack. CuRi ch<@ng trnh con DELAY, chng ta dng
instruction RET, instruction ny POP d[ liBu t; stack ra PC m*t cch t` .*ng, bZng cch ny chng ta c th1
quay l:i vS tr tr<?c .. Chnh v cc lBnh RCALL v RET sC dHng stack m*t cch t` .*ng nn ta ph2i khWi .*ng
stack ngay t; .Lu, n>u khng ch<@ng trnh sc th`c thi sai chGc nKng.
Tm l:i cLn khWi .*ng stack W .Lu ch<@ng trnh v khng nn sC dHng stack m*t cch ty thch n>u ch<a thAt
cLn thi>t.
IV. Thanh ghi tr3ng thi - SREG (STATUS REGISTRY).
NZm trong vng nh? I/O, thanh ghi SREG c .Sa chU I/O l 0x003F v .Sa chU b* nh? l 0x005F (th<Qng .y
l vS tr cuRi cng câ vng nh? I/O) l m*t trong sR cc thanh ghi quan tr-ng nh5t câ AVR, v th> m ti dnh
phLn ny .1 gi?i thiBu v/ thanh ghi ny. Thanh ghi SREG chGa 8 bit cQ (flag) chU tr:ng thi câ b* xC l, t5t c2
cc bit ny ./u bS xa sau khi reset, cc bit ny c7ng c th1 .<Xc .-c v ghi bWi ch<@ng trnh. ChGc nKng câ
t;ng bit .<Xc m t2 nh< sau:

Hnh 7. Thanh ghi tr:ng thi.
Bit 0 C (Carry Flag: CA nh-): l bit nh? trong cc php .:i sR hoDc logic, v dH thanh ghi R1 chGa
gi trS 200, R2 chGa 70, chng ta th`c hiBn php c*ng c nh?: ADC R1, R2, sau php c*ng, k>t qu2 sc .<Xc lt qu2 th`c l 270 m thanh ghi R1 l:i chU c kh2 nKng chGa tRi .a gi trS 255
(v c 8 bit) nn trong tr<Qng hXp ny, gi trS lu k>t qu2 php ton .:i sR hay php Logic bZng 0.
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Bit 2 N (Negative Flag: CA m): cQ ny .<Xc set n>u k>t qu2 php ton .:i sR hay php Logic l sR
m.
Bit 3 V (Twos complement Overflow Flag: CA trn c?a b 2): ho:t .*ng câ cQ ny c vf sc kh
hi1u cho b:n v n lin quan .>n ki>n thGc sR nhS phn (phLn b), chng ta sc ./ cAp .>n khi no th5y cLn thi>t.
Bit 4 S (Sign Bit: Bit dLu): Bit S l k>t qu2 php XOR gi[a 1 cQ N v V, S=N xor V.
Bit 5 H (Half Carry Flag: CA nhA nPa): cQ H l cQ nh? trong 1 vi php ton .:i sR v php Logic,
cQ ny hiBu qu2 .Ri v?i cc php ton v?i sR BCD.
Bit 6 T (Bit Copy Storage): .<Xc sC dHng trong 2 Instruction BLD (Bit LoaD) v BST (Bit
STorage). Ti sc gi2i thch chGc nKng Bit T trong phLn gi?i thiBu v/ BLD v BST.
Bit 7 I (Global Interrupt Enable) : Cho php ngMt ton b*): Bit ny ph2i .<Xc set ln 1 n>u trong
ch<@ng trnh c sC dHng ngMt. Sau khi set bit ny, b:n muRn kch ho:t lo:i ngMt no cLn set cc bit ngMt ring câ
ngMt .. Hai instruction dng ring .1 Set v Clear bit I l SEI v CLI.
Ch : t5t c2 cc bit trong thanh ghi SREG ./u c th1 .<Xc xa thng qua cc instruction khng ton h:ng
CLx v set bWi SEx, trong . x l tn câ Bit.V dH CLT l xa Bit T v SEI l set bit I.
Ti chU gi2i thch ngMn g-n chGc nKng câ cc bit trong thanh ghi SREG, cH th1 chGc nKng v cch sC dHng câ
t;ng bit chng ta sc tm hi1u trong cc tr<Qng hXp cH th1 sau ny, ng<Qi .-c c th1 t` tm hi1u thm trong cc ti
liBu v/ INSTRUCTION cho AVR.
Ti cung c5p thm 1 b2ng tm tMt s` 2nh h<Wng câ cc php ton .:i sR, logic ln cc Bit trong thanh ghi
SREG.
Ntinside 22
Hnh 8. hnh h<Wng câ cc php ton ln SREG.
IV. Macro v ch9.ng trnh con.
Macro l khi niBm chU m*t .o:n code nh_ .1 th`c hiBn m*t cng viBc no ., n>u c 1 .o:n code no .
m b:n r5t hay sC dHng khi lAp trnh th b:n nn dng macro .1 trnh viBc ph2i vi>t .i vi>t l:i .o:n code .. LAp
trnh ASM cho AVR cho php b:n sC dHng Macro, .1 t:o 1 Macro b:n sC dHng DIRECTIVE.
.MACRO delay4
NOP
NOP
NOP
NOP
.ENDMACRO
bo:n Macro trn c tn delay4 th`c hiBn viBc delay 4 chu kN my bZng 4 lBnh NOP, n>u trong ch<@ng trnh
b:n cLn dng Macro ny th chU cLn g-i delay4 W b5t kN dng no.
[] ; code câ b:n
Delay4
[] ; code câ b:n
MYi lLn tn câ Macro .<Xc g-i, trnh bin dSch sc tm .>n Macro . v copy ton b* n*i dung Macro vo vS
tr b:n g-i. Nh< vAy th`c ch5t con tr_ ch<@ng trnh khng nh2y .>n Macro, Macro khng lm gi2m dung l<@ng
ch<ong trnh m chU lm cho viBc lAp trnh nhi nhng h@n. by chnh l khc biBt l?n nh5t câ Macro v
Subroutine (ch<@ng trnh con).
Ch9.ng trnh con c7ng l 1 .o:n code th`c hiBn 1 chGc nKng .Dc biBt no .. Tuy nhin khc v?i Macro,
mYi khi g-i ch<@ng trnh con, con tr_ ch<@ng trnh nh2y .>n ch<@ng trnh con ./ th`c thi ch<@ng trnh con v
sau . quay v/ ch<@ng trnh chnh. Nh< th> ch<@ng trnh con chU .<Xc bin dSch 1 lLn v c th1 sC dHng nhi/u
lLn, n lm gi2m dung l<Xng ch<ong trnh. by l n ch<@ng trnh con v nh2y v/ ch<@ng trnh chnh cLn vi chu
kN my, c th1 lm chAm ch<@ng trnh, .y l nh<Xc .i1m câ ch<@ng trnh con so v?i macro.
Ch<@ng trnh con cho AVR lun .<Xc bMt .Lu bZng 1 Label, . c7ng l tn v .Sa chU câ ch<@ng trnh con.
Ch<@ng trnh con th<Qng .<Xc k>t thc v?i cu lBnh RET (Return). Chng ta . bi>t v/ ch<@ng trnh con qua v
dH câ bi 1, trong . DELAY l 1 ch<@ng trnh con.
b1 g-i ch<@ng trnh con t; 1 vS tr no . trong ch<@ng trnh, chng ta c th1 dng
lBnh CALL hoDc RCALL (Relative CALL) (xem l:i v dH bi 1 v/ cch sC dHng RCALL). MYi khi cc lBnh ny
.<Xc g-i, b* .>m ch<@ng trnh .<Xc t` .*ng .<Xc PUSH vo stack v khi ch<@ng trnh con k>t thc bZng lBnh
RET, b* .>m ch<@ng trnh .<Xc POP trW ra v quay v/ ch<@ng trnh chnh. LBnh CALL c th1 g-i 1 ch<@ng
trnh con W b5t kN vS tr no trong khi RCALL chU g-i trong kho2ng b* nh? 4KB, nh<ng RCALL cLn t chu kN
xung clock h@n khi th`c thi.
Hai instruction khc c th1 .<Xc dng .1 g-i ch<@ng trnh con . l JMP (Jump) v RJMP (Relative Jump).
Khc v?i cc lBnh call, cc lBnh jump khng cho php quay l:i v khng t` .*ng PUSH b* .>m ch<@ng trnh vo
Stack, .1 sC dHng cc lBnh ny g-i ch<@ng trnh con b:n cLn m*t sR lBnh jump khc W cuRi ch<@ng trnh con.
Tm l:i b:n nn vi>t 1 ch<@ng trnh con .ng chu]n v dng CALL hoDc RCALL .1 g-i ch<@ng cc
ch<@ng trnh ny, chU nh[ng tr<Qng hXp .Dc biBt hoDc b:n hi1u r5t r v/ chng th c th1 dng cc lBnh jump.
V. V d5 minh hRa.
N>u b:n . .-c v hi1u .>n thQi .i1m ny th b:n . c th1 hi1u h>t ho:t .*ng câ ch<@ng trnh v dH trong
bi 1, thAt s` v dH . r5t .@n gi2n v dI hi1u. Tuy nhin, b:n c th/ tRi <u ha v dH . theo h<?ng lm gi2m
dung l<Xng ch<@ng trnh v t5t nhin, ch<@ng trnh sc kh hi1u h@n cho ng<Qi khc. Cc phLn khWi .*ng vS tr
b* nh?, stack v ch<@ng trnh con DELAY chng ta khng thay .ei, chU thay .ei phLn ch<@ng trnh chnh, 1
trong nh[ng cch vi>t ch<@ng trnh chnh nh< cch sau:
; CHUONG TRINH CHINH , BAI 1, VI DU 1, VERSION 2///////////////////////////////
LDI R16, $1 ;LOAD GIA TRI KHOI DONG CHO R16
MAIN:
OUT PORTB, R16 ; XUAT GIA TRI TRONG R16 RA PORTB
RCALL DELAY ; GOI CHUONG TRINH CON DELAY
ROL R16 ; XOAY THANH GHI R16 SANG TRAI 1 VI TRI
RJMP MAIN ; NEU R16 j0, NHAY VE MAIN, TIEP TUC QUET
;/////////////////////////////////////////////////////////////////////////////////////////
C th1 khng cLn gi2i thch b:n c7ng . c th1 hi1u .o:n code trn, .y chU l 1 trong nh[ng cch c th1,
b:n hy vi>t l:i theo cch câ ring b:n v?i yu cLu l ch<@ng trnh ph2i th`c hiBn .ng chGc nKng v ngMn g-n.
Ntinside 23
By giQ chng ta sc th`c hiBn m*t v dH minh h-a cho nh[ng g chng ta . h-c trong bi 2 ny. N*i dung
câ v dH th1 hiBn trong m:ch .iBn hnh 9. Ho:t .*ng câ m:ch .iBn tC nh< sau: 1 chip ATMega8 .<Xc sC dHng
nh< m*t counter, c th1 dng .1 .>m ln v .>m xuRng, 2 button trong m:ch .iBn tc .*ng nh< 2 kicker, nh5n
button 1 .1 .>m ln v button .1 .>m xuRng, gi trS .>m nZm trong kho2ng t; 0 .>n 9. Gi trS .>m .<Xc hi1n thS
trn 1 LED 7 .o:n lo:i anod chung (d<@ng chung), chip 7447 .<Xc dng .1 gi2i m t; gi trS BCD xu5t ra bWi
ATMega8 sang tn hiBu cho LED 7 .o:n anod chung, chng ta cLn sC dHng 7447 v tn hiBu xu5t ra t; chip
ATMega8 l d:ng nhS phn hoDc BCD , tn hiBu ny khng th1 hi1n thS tr`c ti>p trn cc LED 7 .o:n, chip 7447
c nhiBm vH chuy1n 1 d[ liBu d:ng digit BCD sang m ph hXp cho LED 7 .o:n.
b1 th`c hiBn v dH, tr<?c h>t b:n hy vc m:ch .iBn nh< trong hnh 9 bZng phLn m/m Proteus (xem cch vc
m:ch .iBn bZng Proteus), m:ch .iBn chU c 5 lo:i linh kiBn l chip ATMega8 (t; kha mega8), 1 LED 7 .o:n
anod chung v?i tn .Ly .^ trong Proteus l 7SEG-COM-AN-GRN (t; kha 7SEG), 1 chip 7447 (t; kha 7447),
1 .iBn trW 10 k v 2 button (t; kha button).

Hnh 9. V dH cho bi 2.
SC dHng AVRStudio t:o 1 project m?i v?i tn g-i avr2 (xem l:i cch t:o Project m?i trong AVRStudio). Vi>t
l:i phLn code bn d<?i vo vo file avr2.asm
List 1. V dH c5u trc AVR

10
11
12
13
14
15
16
.CSEG.
.ORG 0x0000
RJMP BATDAU
.ORG 0x0020
BATDAU:
;KHOI DONG STACK POINTER
OUT SPL, R16
OUT SPH,R17
; KHOI DONG CAC PORT
CLR R16 ; XOA R16, R16=0
OUT DDRB, R16 ; DDRB=0, PORTB LA NGO NHAP
LDI R16, 0xFF ; SET TAT CA CAC BIT CUA R16 LEN 1
OUT PORTB,R16 ;DDRB=0, PORTB =0xFF, KEO LEN CAC CHAN PORTB
Ntinside 24
17
18
19
20
21
22
23
24
5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
OUT DDRD, R16 ;DDRD=0xFF, PORTD LA NGO XUAT
CLR R25 ;XOA R25, R25 LA THANH GHI DUNG CHUA SO DEM
SER R20 ; R20 LA THANH GHI TAM CHUA GIA TRI TRUOC DO CUA PINB
MAIN:
IN R21,PINB ;DOC GIA TRI TU PINB, TUC TU CAC BUTTON
RCALL SOSANH ;GOI CHUONG TRINH CON SOSANH
OUT PORTD, R25 ;XUAT GIA TRI DEM RA PORTD
SBRS R21,0 ;NEU BIT 0 CUA R21 (TUC CHAN PB0) =1 THI BO QUA DONG ;TIEP THEO
RCALL TANG ;NHAY DEN CHUONG TRINH CON TANG GIA TRI DEM
RCALL GIAM ;NHAY DEN CHUONG TRINH CON GIAM GIA TRI DEM
MOV R20,R21 ;LUU LAI TRANG THAI PINB
RJMP MAIN
;**********************CHUONG TRINH CON************************
; **************subroutine kiem tra gioi hang (tu 0 den 9) cua so dem
SOSANH:
CPI R25, 10
BREQ RESET0 ;NEU GIA TRI DEM=10 THI TRA VE 0
CPI R25, 255
BREQ RESET9 ;NEU GIA TRI DEM =255 THI TRA VE 9
RJMP QUAYVE ;NHAY DEN NHAN QUAYVE
RESET0:
LDI R25,$0 ;TRA GIA TRI DEM VE 0
RJMP QUAYVE
RESET9:
LDI R25,$9 ;GAN 9 CHO GIA TRI DEM
QUAYVE:
RET
; ************************************************************
; **************subroutine tang so dem 1 don vi neu dieu kien thoa
TANG:
SBRS R20,0
RET
INC R25
RET
; **************subroutine giam so dem 1 don vi neu dieu kien thoa
GIAM:
SBRS R20,1
RET
Ntinside 25
56
57
DEC R25
RET
Trong v ny ny, chng ta sC dHng 2 PORT câ chip ATMega8, PORTD dng xu5t d[ liBu (sR .>m) ra chip
7447 v sau . hi1n thS trn LED 7 .o:n. PORTB dng nh< ng nhAp, tn hiBu t; cc button sc .<Xc chip
ATMega8 nhAn thng qua 2 chn PB0 v PB1 câ PORTB.
Ho:t .*ng câ cac PORT v viBc xc lAp 1 PORT nh< cc ng xu5t chng ta . kh2o st trong bi 1. % .y
chng ta kh2o st thm v/ xc lAp PORT nh< 1 ng nhAp, tr<?c h>t b:n hy quan st m:ch .iBn t<@ng .<@ng câ
1 chn trong cc PORT xu5t nhAp câ AVR trong hnh 10.

Hnh 10. C5u trc chn trong PORT câ AVR.
Trong m:ch .iBn hnh 10, cc diode v tH .iBn chU c chGc nKng b2o vB chn PORT, nh<ng .iBn trW Rpu (R
Pull up) .ng vai tr quan tr-ng nh< l .iBn trW ko ln khi chn câ PORT lm nhiBm vH nhAn tn hiBu (ng
nhAp). Tuy nhin trong AVR, .iBn trW ko ln ny khng ph2i lun kch ho:t, chng ta bi>t rZng mYi PORT câ
AVR c 3 thanh ghi: DDRx, PORTx v PINx, n>u DDRx=0 th PORT x l ng nhAp, lc ny thanh ghi PINx l
thanh ghi chGa d[ liBu nhAn v/, .Dc biBt thanh ghi PORTx van .<Xc sC dHng trong mode ny, . l thanh ghi xc
lAp .iBn trW ko ln, nh< th> n>u DDRx=0 v PORTx=0xFF th cc chn PORTx l ng nhAp v .<Xc ko ln
bWi 1 .iBn trW trong chip, ngh\a l cc chn câ PORTx lun W mGc cao, muRn kch .1 thay .Pi tr:ng thi chn
ny chng ta cLn nRi chn . tr`c ti>p v?i GND, .5y l l do t:i sao cc button trong m:ch .iBn câ chng ta c
1 .Lu nRi v?i chn câ chip cn .Lu kia .<Xc nRi v?i GND. by c7ng l ngh\a câ khi niBm .iBn trW ko ln
(Pull up resistor) trong kg thuAt .iBn tC. bo:n code trong phLn KHOI DONG CAC PORT câ v dH ny xc
lAp PORTD l ng xu5t (DDRD=0xFF) , PORTB l ng nhAp c sC dHng .iBn trW ko ln (DDRB=0,
PORTB=0xFF).
Chng ta sc gi2i thch ho:t .*ng câ .o:n ch<@ng trnh chnh v cc .o:n ch<@ng trnh con. Tr<?c h>t, trong
ch<@ng trnh ny, chng ta sC dHng 3 thanh ghi chnh l R20, R21 v R25, trong . R25 l thanh ghi chGa sR
.>m, gi trS câ thanh ghi R25 sc .<Xc xu5t ra PORTD câ chip, thanh ghi R21 chGa tr:ng thi câ thanh ghi
PINB v c7ng l tr:ng thi câ cc button, thanh ghi R20 k>t hXp v?i thanh ghi R21 t:o thnh 1 b* .>m c:nh
xuRng câ cc button. b1 hi1u th5u .o ho:t .*ng .>m (c7ng l ho:t .*ng chnh câ v dH ny) chng ta xt
tr:ng thi chn PB0 nh< trong hnh 11.

Hnh 11. Thay .ei tr:ng thi W cc chn I/O.
Trong tr:ng thi bnh th<Qng (button khng .<Xc nh5n), chn PB0 W mGc cao (do .iBn trW ko ln), b* .>m
khng ho:t .*ng, gi trS .>m khng thay .ei, by giQ n>u nh5n button, chn PB0 .<Xc nRi tr`c ti>p v?i GND,
chn ny sc bS ko xuRng mGc th5p, bZng cch ki1m tra tr:ng thi chn PB0, n>u PB0=0 ta tKng gi trS .>m 1 .@n
vS. t<Wng nh< th> c vf hXp l, tuy nhin n>u p dHng th ch<@ng trnh sc ho:t .*ng khng .ng chGc nKng,
khi b:n nh5n 1 lLn gi, trS .>m c th1 tKng .>n c2 trKm hoDc khng ki1m sot .<Xc, hiBu Gng ny t<@ng t` khi
Ntinside 26
b:n nh5n v gi[ 1 phm trn bn phm my tnh, l do l v chng ta sC dHng ph<@ng php ki1m tra mGc .1 .>m,
thQi gian qut câ ch<@ng trnh r5t ngMn so v?i thQi gian chng ta gi[ button. b1 khMc phHc, chng ta dng
ph<@ng php ki1m tra c:nh xuRng, chU khi no pht hiBn chn PB0 thay .ei t; 1 xuRng 0 th m?i tKng gi trS .>m
1 .@n vS, k>t qu2 l mYi lLn nh5n button th gi trS .>m chU tKng 1 (ngay c2 khi ta nh5n v gi[ button), thanh ghi
R20 .<Xc sC dHng .1 l<u tr:ng thi tr<?c . câ PINB (c7ng l tr:ng thi câ cc button).
Trong ch<@ng trnh, ti sC dHng 2 istruction m?i l SBRC v SBRS .1 ki1m tra tr:ng thi cc chn câ
PORTB (button). SBRC Skip if Bit in Register is Clear, lBnh ny sc b_ qua 1 dng lBnh ngay sau . (chU b_
qua 1 dng duy nh5t) n>u 1 bit trong thanh ghi W mGc 0, SBRC Skip if Bit in Register is Set- ho:t .*ng t<@ng
t` SBRC nh<ng skip sc x2y ra n>u bit trong thanh ghi W mGc 1. Dà vo .y chng ta gi2i thch 4 dng sau:
RCALL TANG ;NHAY DEN CHUONG TRINH CON TANG GIA TRI DEM
RCALL GIAM ;NHAY DEN CHUONG TRINH CON GIAM GIA TRI DEM
Dng 1 dng ki1m tra tr:ng thi bit 0 trong R21 (ch R21 chGa gi trS câ PINB), n>u bit ny bZng 1 (set),
tGc chn PB0=1 hay button khng .<Xc nh5n, th nh2y b_ qua dng lBnh ti>p theo .1 .>n dng 3. % dng 3
ch<@ng trnh ki1m tra tr:ng thi chn PB1 (button thG 2). Quay l:i dng 1, n>u ch<@ng trnh ki1m tra pht hiBn
chn PB0=0 (button thG nh5t .<Xc nh5n) th dng lBnh thG 2 .<Xc th`c thi, k>t qu2 l ch<@ng trnh nh2y .>n
ch<@ng trnh con TANG.
TANG:
SBRS R20,0
RET
INC R25
RET
Dng .Lu tin câ ch<@ng trnh con TANG l ki1m tra tr:ng thi tr<?c . câ chn PB0 (.<Xc lu tr:ng thi ny bZng 0, ngh\a l khng c s` chuy1n t; 1 xuRng 0 W chn PB0, dng 2
(lBnh RET) sc .<Xc th`c thi .1 quay v/ ch<@ng trnh chnh. Nh<ng n>u PB0 tr<?c . bZng 1, ngh\a l c s` thay
.ei t; 1->0 W chn ny, gi trS .>m sc .<Xc tKng thm 1 nhQ INC R25, sau . quay v/ ch<@ng trnh chnh.
Tm l:i muRn tKng gi trS .>m thm 1 .@n vS cLn th_a mn 2 .i/u kiBn: chn PB0 hiBn t:i =0 (button .ang .<Xc
nh5n) v tr:ng thi tr<?c . câ PB0 ph2i l 1 (trnh tr<Qng hXp tKng lin tHc). Ph<@ng php ny c th1 p dHng
cho r5t nhi/u tr<Qng hXp .>m d:ng .>m xung.
Qu trnh gi2m gi trS .>m .<Xc hi1u t<@ng t`, phLn cn l:i câ v dH ny b:n .-c hy t` gi2i thch theo
nh[ng gXi trn.

Ntinside 27
Bi 3 - Ng"t ngoi

I. NgSt trn AVR.
Interrupts, th<Qng .<Xc g-i l ngMt, l m*t tn hiBu kh]n c5p gWi .>n b*
xC l, yu cLu b* xC l t:m ng;ng tGc khMc cc ho:t .*ng hiBn t:i .1 nh2y
.>n m*t n@i khc th`c hiBn m*t nhiBm vH kh]n c5p no ., nhiBm vH ny
g-i l trnh phHc vH ngMt isr (interrupt service routine ). Sau khi k>t thc
nhiBm vH trong isr, b* .>m ch<@ng trnh sc .<Xc tr2 v/ gi trS tr<?c . .1 b*
xC l quay v/ th`c hiBn ti>p cc nhiBm vH cn dang dW. Nh< vAy, ngMt c
mGc .* n ngMt c
th1 xu5t pht t; cc thi>t bS bn trong chip (ngMt bo b* .>m timer/counter
trn, ngMt bo qu trnh gWi d[ liBu bZng RS232 k>t thc) hay do cc tc
nhn bn ngoi (ngMt bo c 1 button .<Xc nh5n, ngMt bo c 1 gi d[ liBu
. .<Xc nhAn).
NgMt l m*t trong 2 kg thuAt bMt s` kiBn c@ b2n bao gPm: h_i vng
(Polling) v ngMt. Hy t<Wng t<Xng b:n cLn thi>t k> m*t m:ch .i/u khi1n
hon chUnh th`c hiBn r5t nhi/u nhiBm vH bao gPm nhAn thng tin t; ng<Qi
dng qua cc button hay keypad (hoDc keyboard), nhAn tn hiBu t; c2m bi>n,
xC l thng tin, xu5t tn hiBu .i/u khi1n, hi1n thS thng tin tr:ng thi ln cc
LCD(b:n hon ton c th1 lm .<Xc v?i AVR ), r rng trong cc nhiBm
vH, viBc nhAn thng tin ng<Qi dng (start, stop, setup, change,) r5t hi>m
x2y ra (so v?i cc nhiBm vH khc) nh<ng l:i r5t kh]n c5p, .<Xc u dng Polling ngh\a l b:n cLn vi>t 1 .o:n ch<@ng trnh
chuyn thKm d tr:ng thi câ cc button (ti t:m g-i l Input() ) v b:n
ph2i chn .o:n ch<@ng trnh ny vo r5t nhi/u vS tr trong ch<@ng trnh
chnh .1 trnh tr<Qng hXp b_ st lBnh t; ng<Qi dng, .i/u ny thAt lng ph
thQi gian th`c thi. Gi2i php cho v5n ./ ny l sC dHng ngMt, bZng cch k>t
nRi cc button v?i .<Qng ngMt câ chip v sC dHng ch<@ng trnh Input() lm
isr câ ngMt ., b:n khng cLn ph2i chn Input() trong lc .ang th`c thi v
v th> khng tRn thQi gian cho n, Input() chU .<Xc g-i khi ng<Qi dng nh5n
cc button. b l t<Wng câ ngMt.
Hnh 1 minh h-a cch te chGc ngMt thng th<Qng trong cc chip AVR, sR
l<Xng ngMt trn mYi dng chip l khc nhau, Gng v?i mYi ngMt sc c vector
ngMt, vector ngMt l cc thanh ghi c .Sa chU cR .Snh, .<Xc .Snh ngh\a tr<?c
nZm trong phLn .Lu câ b* nh? ch<@ng trnh. V dH vector ngMt ngoi 0
(external interrupt 0) câ chip atmega8 c .Sa chU l 0x009 (theo datasheet t;
Ntinside 28
Atmel). Trong lc ch<@ng trnh chnh .ang th`c thi, n>u c m*t s` thay .ei
dan .>n ngMt x2y ra W chn INT0 (chn 4), b* .>m ch<@ng trnh (Program
Counter) nh2y .>n .Sa chU 0x009, gi2 sC ngay t:i .Sa chU 0x009 chng ta c
.Dt 1 lBnh RJMP .>n m*t trnh phHc vH ngMt (IRS1 chFng h:n), m*t lLn n[a
b* .>m ch<@ng trnh nh2y .>n IRS1 .1 th`c thi trnh phHc vH ngMt, k>t thc
ISR1, b* .>m ch<@ng trnh l:i quay v/ vS tr tr<?c . trong ch<@ng trnh
chnh, qu trnh ngMt k>t thc. Khng mang tnh bMt bu*c nh<ng ti khuyn
b:n nn te chGc ch<@ng trnh ngMt theo cc ny .1 trnh nh[ng lYi lin quan
.>n .Sa chU ch<@ng trnh.

Hnh 1. NgMt.
B2ng 1 tm tMt cc vector ngMt c trn chip atmega8, cho cc chip khc
b:n hy tham kh2o datasheet .1 bi>t thm.
B2ng 1 cc vector ngMt v Reset trn chip Atmega8.
Ntinside 29

II. NgSt ngoi (External Interrupt).
PhLn ny ti dnh gi?i thiBu cc b:n cch ci .Dt v sC dHng ngMt ngoi
v .y l lo:i ngMt duy nh5t .*c lAp v?i cc thi>t bS ngo:i vi câ chip, cc
ngMt khc th<Qng gMn v?i ho:t .*ng câ 1 thi>t bS no . nh<
Timer/Counter, giao ti>p nRi ti>p USART, chuy1n .ei ADCchng ta sc
kh2o st cH th1 khi tm hi1u v/ ho:t .*ng câ cc thi>t bS ny.
NgMt ngoi l cch r5t hiBu qu2 .1 th`c hiBn giao ti>p gi[a ng<Qi dng
v chip, trn chip atmega8 c 2 ngMt ngoi c tn t<@ng Gng l INT0 v
INT1 t<@ng Gng 2 chn sR 4 (PD2) v sR 5 (PD3). Nh< ti . ./ cAp trong
bi AVR2, khi lm viBc v?i cc thi>t bS ngo:i vi câ AVR, hLu nh< chng ta
Ntinside 30
chU thao tc trn cc thanh ghi chGc nKng .Dc biBt - SFR (Special Function
Registers) trn vng nh? IO, m*i thi>t bS bao gPm m*t tAp hXp cc thanh ghi
.i/u khi1n, tr:ng thi, ngMtkhc nhau, .i/u ny .Png ngh\a chng ta ph2i
nh? t5t c2 cc thanh ghi câ AVR. Lc ny datasheet pht huy tc dHng, b:n
ph2i nhanh chng download file datasheet câ chip mnh .ang sC dHng, c
r5t nhi/u n@i .1 download nh< t:i www.atmel.com hay trn cc trang web
chuyn cung c5p IC datasheet free (www.alldatasheet.com l 1 v dH). Quay
v/ v?i ngMt ngoi, c 3 thanh ghi lin quan .>n ngMt ngoi . l MCUCR,
GICR v GIFR. CH th1 cc thanh ghi .<Xc trnh by bn d<?i.
Thanh ghi =iTu khiGn MCU MCUCR (MCU Control Register) l
thanh ghi xc lAp ch> .* ngMt cho ngMt ngoi, gi2 sC chng ta k>t nRi cc
chn ngMt nh< hnh 2.

Hnh 2. K>t nRi ngMt ngoi cho atmega8.
Gi2 sC chng ta k>t nRi cc ngMt ngoi trn AVR mega8 nh< pha tri
hnh 9, cc button dng t:o ra cc ngMt, c 4 kh2 nKng (t:m g-i l cc
MODE) c th1 x2y ra khi chng ta nh5n v th2 cc button. N>u khng nh5n,
tr:ng thi cc chn INT l HIGH do .iBn trW ko ln, khi v;a nh5n 1 button,
sc c chuy1n tr:ng thi t; HIGH sang LOW, chng ta g-i l c:nh xuRng -
Falling Edge, khi button .<Xc nh5n v gi[, tr:ng thi cc chn INT .<Xc
xc .Snh l LOW v cuRi cng khi th2 cc button, tr:ng thi chuy1n t; LOW
sang HIGH, g-i l c:nh ln Rising Edge. Trong nh[ng tr<Qng hXp cH th1,
1 trong 4 MODEs trn ./u h[u ch, v dH trong cc Gng dHng .>m xung
(.>m encoder câ servo motor chFng h:n) th 2 MODE c:nh ph2i .<Xc
dng. Thanh ghi MCUCR chGa cc bits cho php chng ta ch-n 1 trong 4
MODE trn cho cc ngMt ngoi. D<?i .y l c5u trc thanh ghi MCUCR
.<Xc trch ra t; datasheet câ chip atmega8.
Ntinside 31

MCUCR l m*t thanh ghi 8 bit nh<ng .Ri v?i ho:t .*ng ngMt ngoi,
chng ta chU quan tm .>n 4 bit th5p câ thanh ghi ny (4 bit cao dng cho
Power manager v Sleep Mode), 4 bit th5p l cc bit Interrupt Sense Control
(ISC), 2 bit ISC11, ISC10 dng cho INT1 v ISC01, ISC00 dng cho INT0.
Hy nhn vo b2ng tm tMt bn d<?i .1 bi>t chGc nKng câ cc bit trn, .y
l b2ng chn trS câ 2 bit ISC11, ISC10. B2ng chn trS cho cc bit ISC01,
ISC00 hon ton t<@ng t`.
B2ng 2: INT1 Sense Control

ThAt dI dng .1 hi1u chGc nKng câ cc bit Sense Control, v dH b:n
muRn set cho INT1 l ngMt c:nh xuRng (Falling Edge) trong khi INT0 l
ngMt c:nh ln (Rising Edge), hy .Dt dng lBnh MCUCR =0x0B (0x0B =
00001011 nhS phn) trong ch<@ng trnh câ b:n.
Thanh ghi .i/u khi1n ngMt chung GICR (General Interrupt Control
Register) (trn cc chip AVR c7, nh< cc chip AT90Sxxxx, thanh ghi ny c
tn l thanh ghi mDt n: ngMt thng th<Qng GIMSK, b:n tham kh2o thm
datasheet câ cc chip ny n>u cLn sC dHng .>n). GICR c7ng l 1 thanh ghi
8 bit nh<ng chU c 2 bit cao (bit 6 v bit 7) l .<Xc sC dHng cho .i/u khi1n
ngMt, c5u trc thanh ghi nh< bn d<?i (trch datasheet).

Ntinside 32
Bit 7 INT1 g-i l bit cho php ngMt 1(Interrupt Enable), set bit ny
bZng 1 ngh\a b:n cho php ngMt INT1 ho:t .*ng, t<@ng t`, bit INT0 .i/u
khi1n ngMt INT0.
Thanh ghi cQ ngMt chung GIFR (General Interrupt Flag Register) c 2
bit INTF1 v INTF0 l cc bit tr:ng thi (hay bit cQ - Flag) câ 2 ngMt INT1
v INT0, n>u c 1 s` kiBn ngMt ph hXp x2y ra trn chn INT1, bit INTF1
.<Xc t` .*ng set bZng 1 (t<@ng t` cho tr<Qng hXp câ INTF0), chng ta c
th1 sC dHng cc bit ny .1 nhAn ra cc ngMt, tuy nhin .i/u ny l khng cLn
thi>t n>u chng ta cho php ngMt t` .*ng, v vAy thanh ghi ny th<Qng khng
.<Xc quan tm khi lAp trnh ngMt ngoi. C5u trc thanh ghi GIFR .<Xc trnh
by trong hnh ngay bn d<?i.

Sau khi . xc lAp cc bit sdn sng cho cc ngMt ngoi, vi0c sau cng
chng ta c>n lm l set bit I, tOc bit cho php ngSt ton c5c, trong thanh
ghi tr:ng thi chung câ chip (thanh ghi SREG, xem l:i bi AVR2). MDt
ch khc l v cc chn PD2, PD3 l cc chn ngSt nn b3n ph@i set
cc chn ny l Input (set thanh ghi DDRD). Qu trnh thi>t lAp ngMt ngoi
.<Xc trnh by trong hnh 10.

Hnh 3. Thi>t lAp ngMt ngoi.
NgSt ngoi v-i ASM: D<?i .y ti trnh by cch vi>t ch<@ng trnh sC
dHng ngMt ngoi bZng ngn ng[ ASM, .Ri v?i cc ngMt khc b:n chU cLn
thm cc DIRECTIVE .1 .Snh vS cc vector ngMt t<@ng Gng v vi>t ch<@ng
trnh phHc vH ngMt t<@ng Gng.
Ntinside 33
List 1. NgMt v?i ASM.
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.CSEG
.ORG 0x000 ; bSnh vS vS tr .Lu tin
RJMP BATDAU
.ORG 0x001; bSnh vS vector ngMt ngoi 0 - INT0 (xem b2ng
vector)
RJMP INT0_ISR ; Nh2y .>n INT0_ISR n>u c ngMt INT0 x2y
ra
.ORG 0x002 ; bSnh vS vector ngMt ngoi 1 INT1 (xem b2ng
vector)
RJMP INT1_ISR ; Nh2y .>n INT1_ISR n>u c ngMt INT1 x2y
ra
;T<@ng t`, .Snh vS cc vector ngMt khc W .y..
;..
.ORG 0x020 ; bSnh vS ch<@ng trnh chnh
BATDAU:
; khWi t:o Stack
OUT SPH, R16
OUT SPL, R17
; set chn PD2 v PD3 nh< cc chn input
LDI R16, 0Bxxxx00xx ; x l tr:ng thi do b:n t` ch-n, 0
hoDc 1
OUT DDRD, R16 ; PD2 v PD3 l input
LDI R16, 0Bxxxx11xx ; x l tr:ng thi do b:n t` ch-n, 0
hoDc 1
OUT PORTD, R16 ; mMc .iBn trW ko ln cho PD2, PD3

; khWi .*ng ngMt
LDI R16, $0B ; $0B=00001011, INT1: ngMt c:nh xuRng,
INT0: ngMt c:nh ln
OUT MCUCR, R16 ; xu5t gi trS .i/u khi1n ra thanh ghi
MCUCR
LDI R16, $C0 ;$C0=11000000: Enable INT1 v INT0
OUT GICR, R16 ;xu5t gi trS .i/u khi1n ra thanh ghi GICR
Ntinside 34
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SEI ;set bit cho php ngMt ton cHc
; Ch<@ng trnh chnh
MAIN:
;cc cng viBc m ch<@ng trnh chnh cLn th`c hiBn
;.
RJMP MAIN
;v .y l .Snh ngh\a trnh phHc vH ngMt
INT0_ISR
INT0_ISR:
; cc cng viBc cLn th`c hiBn khi c ngMt
;.
RETI ; ph2i dng lBnh RETI .1 quay v/ ch<@ng trnh chnh
;v .y l .Snh ngh\a trnh phHc vH ngMt
INT1_ISR
INT1_ISR:
; cc cng viBc cLn th`c hiBn khi c ngMt
;.
RETI ; ph2i dng lBnh RETI .1 quay v/ ch<@ng trnh chnh
B:n th5y cc cc ngMt .<Xc .Snh vS nZm gi[a vS tr 0x0000, khi m?i khWi
.*ng, t:i v tr 0x000 l lBnh RJMP BATDAU, nh< th> cc lBnh RJMP t:i
cc vector ngMt v cc ISR ./u khng .<Xc th`c hiBn, chng chU .<Xc th`c
hiBn m*t cch t` .*ng khi c ngMt.
NgSt ngoi v-i C: Avr-libc hY trX m*t th< viBn hm cho ngMt kh hon
h2o, .1 sC dHng ngMt trong ch<@ng trnh vi>t bZng C (avr-gcc) b:n chU cLn
include file interrupt.h nZm trong th< mHc con avr l xong. file header
interrupt.h chGa .Snh ngh\a cc hm v ph<@ng thGc phHc vH cho vi>t trnh
phHc vH ngMt, cc vector ngMt khng .<Xc .Snh ngh\a trong file ny m trong
file iom8.h (cho atmega8). N>u b:n v tnh tm th5y 1 ch<@ng trnh ngMt no
. khng include file interrupt.h m include file signal.h th b:n .;ng ng:c
nhin, . l cch vi>t c7 trong avr-gcc, thAt ra b:n hon ton c th1 sC dHng
cch vi>t c7 v cc phin b2n m?i câ avr-libc (.i cng v?i cc b2n WinAVR
m?i) van hY trX cch vi>t ny nh<ng khng khuyn khch b:n dng.
Trong C cc trnh phHc vH ngMt c tn l ISR (vector_name), trong cc
phin b2n c7, trnh phHc vH ngMt c tn SIGNAL(vector_name) nh<ng c7ng
nh< file header signal.h, trnh ny van .<Xc hY trX trong phin b2n m?i
nh<ng khng .<Xc khuy>n khch sC dHng.
List 2. NgMt v?i C.
Ntinside 35
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#include <avr/interrupt.h>

ISR (vector_name)
{
//user code here
}
Trong . vector_name l tn câ cc vector ngMt .Snh ngh\a sdn avr-libc,
ISR l tn bMt bu*c, b:n khng .<Xc dng cc tn khc ty N (nh<ng c th1
dng SIGNAL nh< . trnh by W trn). bDc biBt, b:n c th1 .Dt ISR W tr<?c
hoDc sau ch<@ng trnh chnh ./u khng 2nh h<Wng v thAt ra, . c kh
nhi/u cng .o:n .<Xc th`c hiBn khi b:n g-i ISR (nh<ng b:n khng th5y
v c7ng khng cLn quan tm), ISR lun .<Xc trnh bin dSch .Dt W ngoi
vng vector ngMt nh< cch chng ta th`c hiBn trong ASM, nh< th> m*t
ch<@ng trnh sC dHng nhi/u lo:i ngMt sc ph2i c sR l<Xng trnh ISR t<@ng
Gng nh<ng v?i vector_name khc nhau, mYi khi c ngMt x2y ra, ty thu*c
vo gi trS câ vector_name m 1 trong cc trnh ISR .<Xc th`c thi. bRi v?i
cc vector_name, .1 bi>t .<Xc vector_name cho mYi lo:i ngMt, b:n cLn tham
kh2o ti liBu avr-libc manual. B2ng 10 tm tMt cc vector_name câ m*t
sR ngMt thng dHng trn atmega8, b:n ch rZng cc vector_name trong avr-
libc .<Xc .Snh ngh\a r5t khc nhau cho t;ng lo:i chip, b:n nh5t thi>t ph2i sC
dHng ti liBu avr-libc manual .1 bi>t chnh xc cc vector_name cho lo:i
chip m b:n .ang dng.
B2ng 3: vector_name cho atmega8.
Vector name Old vector name Description
ADC_vect SIG_ADC ADC Conversion Complete
ANA_COMP_vect SIG_COMPARATOR Analog Comparator
EE_RDY_vect SIG_EEPROM_READY EEPROM Ready
INT0_vect SIG_INTERRUPT0 External Interrupt 0
INT1_vect SIG_INTERRUPT1 External Interrupt Request 1
SPI_STC_vect SIG_SPI Serial Transfer Complete
SPM_RDY_vect SIG_SPM_READY Store Program Memory Ready
TIMER0_OVF_vect SIG_OVERFLOW0 Timer/Counter0 Overflow
TIMER1_CAPT_vect SIG_INPUT_CAPTURE1 Timer/Counter Capture Event
TIMER1_COMPA_vect SIG_OUTPUT_COMPARE1A
Timer/Counter1 Compare Match
A
Ntinside 36
TIMER1_COMPB_vect SIG_OUTPUT_COMPARE1B Timer/Counter1 Compare MatchB
TIMER2_COMP_vect SIG_OUTPUT_COMPARE2 Timer/Counter2 Compare Match
TWI_vect SIG_2WIRE_SERIAL 2-wire Serial Interface
USART3_UDRE_vect SIG_USART3_DATA USART3 Data register Empty
III. V d5 ngSt ngoi v-i C.
b1 th`c hiBn v dH sC dHng ngMt ngoi bZng C, ti sc vi>t l:i ch<@ng
trnh v dH câ bi "c5u trc AVR" nh<ng bZng ngn ng[ C v sC dHng ngMt.
Trong ch<@ng trnh v dH câ bi AVR2, chng ta th`c hiBn viBc .>m ln v
.>m xuRng dng 2 button, chng ta sc van th`c hiBn trn t<Wng ny nh<ng
c cht thay .ei trong k>t nRi, tr<?c h>t b:n vc 1 m:ch .iBn m ph_ng trong
Proteus nh< hnh 4.

Hnh 4. M:ch .iBn m ph_ng ngMt.
K>t nRi button .>m ln v?i ngMt INT0, button .>m xuRng v?i INT1,
PORTB .<Xc ch-n lm PORT xu5t. Hy ch:yProgrammer Notepad, t:o 1
Project m?i tn AVR2-INT, type .o:n code bn d<?i vo 1 file new v l
Ntinside 37
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#include <avr/delay.h>

volatile int8_t val=0; //khai bo 1 bi>n val 8 bit, c d5u v gi trS
khWi t:o bZng 0.
int main(void){

DDRD=0x00; //khai bo PORTD l Input .1 sC dHng 2 chn
ngMt.
PORTD=0xFF; //sC dHng .iBn trW n*i ko ln.
DDRB=0xFF; //PORTB l Output .1 xu5t LED 7 .o:n

MCUCR|=(1<<ISC11)|(1<<ISC01); //c2 2 ngMt l ngMt c:nh
xuRng
GICR |=(1<<INT1)|(1<<INT0); //cho php 2 ngMt ho:t .*ng
sei(); //set bit I cho php ngMt ton cHc

DDRC=0xFF; //PORTC l Output
while (1){ //vng lDp v tAn
PORTC++; //qut PORTC
_delay_loop_2(60000);
}
return 0;
}

//Trnh phHc vH ngMt câ INT0
ISR(INT0_vect){
val++; //n>u c ngMt INT0 x2y ra, tKng
val thm 1
if (val>9) val=0; //gi?i h:n khng v<Xt qu 9
PORTB=val;
}

//Trnh phHc vH ngMt câ INT1
ISR(INT1_vect){
val--; //n>u c ngMt INT1 x2y ra, gi2m
val .i 1
if (val<0) val=9; //gi?i h:n khng nh_ h@n 0
PORTB=val;
Ntinside 38
}
C lc .o:n code ny kh dI hi1u n>u cc b:n theo di t; .Lu bi h-c, ti
chU gi2i thch nh[ng nt c@ b2n v m?i. t<Wng l chng ta sC dHng 1
bi>n t:m 8 bit, c d5u .1 lm, tn bi>n val, mYi khi c ngMt trn
chn INT0, tKng val 1 .@n vS v ng<Xc l:i khi c ngMt trn INT1, gi2m val .i
1, . l n*i dung câ 2 trnh phHc vH ngMt. Trong ch<@ng trnh chnh, tr<?c
h>t chng ta th`c hiBn viBc xc lAp ho:t .*ng cho 2 ngMt, sau . .<a ch<@ng
trnh vo 1 vng lDp v tAn while(1), PORTC .<Xc dng .1 ki1m tra rZng
ch<@ng trnh trong vng lDp v tAn van .ang ho:t .*ng. C lc phLn kh hi1u
nh5t trong .o:n code l cch m ti dng .1 khai bo cho 2 thanh ghi .i/u
khi1n ngMt MCUCR v GICR.
N>u xem l:i b2ng tm tMt cc ton tC câ C, ton tC << .<Xc g-i l
ton tC dSch tri dng trn d:ng nhS phn câ cc con sR, n>u b:n th5y
x=5<<3 ngh\a l dSch cc bit nhS phn câ 5 sang tri 3 vS tr v gn cho x,
nh< m t2 nh< sau:

B:n th5y ton b* cc bit câ 5 . dSch sang tri 3 vS tr v gi trS câ sR m?i thu .<Xc l x=40, ch
40=5x8=5x2^3 . Hy nhn cu lBnh MCUCR|=(1<<ISC11)|(1<<ISC01), giQ th b:n . hi1u (1<<ISC11) ngh\a l
dSch sR 1 sang tri ISC11 vS tr, v (1<<ISC01) l dSch sR 1 sang tri ISC01 vS tr, nh<ng ISC11 v ISC01 W .u
ra v gi trS câ chng l bao nhiu? B:n ch , khi b:n include file io.h th file iom8.h .<Xc chn vo, v
trong file ny chGa khai bo .Sa chU cc thanh ghi câ chip atmega8, cc tn bit c7ng .<Xc khai bo sdn trong file
ny, n>u b:n mW file iom8.h (th<Qng nZm trong th< mHc ~\WinAVR\avr\include\avr) bZng 1 ch<@ng trnh text
editor nh< notepad, dng chGc nKng find b:n sc th5y cc dng .Snh ngh\a nh< sau:
/* MCUCR */
#define SE 7
#define SM2 6
#define SM1 5
#define SM0 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0
by l .Snh ngh\a vS tr cc bit trong thanh ghi MCUCR, vAy l . r, ISC11=3, ISC01=1, do .:
(1<<ISC11) t<@ng .<@ng (1<<3) = 00001000 (Binary) v (1<<ISC01) = 00000010, b:n hy t<Wng t<Xng rZng
b:n . mang sR 1 .>n cc vS tr câ ISC11 v ISC01 trong thanh ghi MCUCR. By giQ .>n l<Xt ton tC OR
bitwise |.
(1<<ISC11) = 00001000
(1<<ISC01) = 00000010
Ntinside 39
--------------------------------------------------
(1<<ISC11)|(1<<ISC01) = 00001010
Gn gi trS ny cho MCUCR, .Ri chi>u v?i b2ng cc gi trS câ cc bit
ISC (b2ng 9) b:n sc th5y chng ta .ang set cho 2 ngMt l falling edge. bi/u
cuRi cng câ cu lBnh set MCUCR l cch rt g-n cu lBnh
MCUCR|=(1<<ISC11)|(1<<ISC01) th`c ch5t l MCUCR= MCUCR|
((1<<ISC11)|(1<<ISC01)), .y l cch set m*t sR bit trong m*t thanh ghi m
khng muRn lm 2nh h<Wng .>n cc bit khc (nh<ng b:n ph2i thAt c]n thAn
v?i cch lm ny v c th1 sc ph2n tc dHng n>u b:n khng nMm r), b:n c
th1 gn tr`c ti>p MCUCR=(1<<ISC11)|(1<<ISC01), hay nhanh h@n
MCUCR=0x0A (0x0A=00001010). VAy l do no khi>n ti bi>n 1 cu lBnh
gn .@n gi2n thnh m*t bi ton kh hi1u, cu tr2 lQi chnh l tnh teng
qut, trong cc chip AVR khc nhau, vS tr cc bit trong cc thanh ghi l r5t
khc nhau, cu lBnh MCUCR=0x0A .ng cho atmega8 nh<ng khng p
dHng .<Xc cho cc chip khc trong khi cu lBnh
MCUCR=(1<<ISC11)|(1<<ISC01) th ho:t .*ng tRt, m*t l do khc l cch
vi>t gin ti>p ny gip ng<Qi khc (hay chnh b:n) khi .-c code c th1 dI
dng hi1u .<Xc .P ng<Qi vi>t
Ti ngh\ b:n . qu hi1u dng lBnh ti>p theo, GICR
|=(1<<INT1)|(1<<INT0). Ti d;ng gi2i thch .o:n code W .y v c7ng d;ng
bi AVR3, b:n hy th`c tAp bZng cch vi>t l:i .o:n code trn bZng ASM.

Ntinside 40
Bi 4 - Timer - Counter

I. Gi-i thi0u.
Trong bi 3 ti . gi?i thiBu khi qut ph<@ng php lAp trnh bZng ngn
ng[ C cho AVR v?i WinAVR v cch sC dHng ngMt trong AVR. Bi 4 ny
chng ta sc kh2o st cc ch> .* ho:t .*ng câ ph<@ng php .i/u khi1n cc
b* .Snh thQi, .>m (Timer/Counter) trong AVR. Cng cH phHc vH cho bi ny
van l b* cng cH WinAVR v phLn m/m m ph_ng Proteus. Ti van dng
chip Atmega8 .1 lm v dH. M*t .i/u khng may mMn l khng ph2i t5t c2
cc b* Timer/Counter trn t5t c2 cc dng chip AVR l nh< nhau, v th>
nh[ng g ti trnh by trong bi ny c th1 sc khng .ng v?i cc dng AVR
khc nh< AT90STuy nhin ti c7ng sc cR gMng chU ra m*t sR .i1m khc
biBt c@ b2n .1 cc b:n c th1 t` mnh .i/u khi1n cc chip khc. N*i dung bi
h-c ny bao gPm:
NMm bMt c@ b2n cc b* Timer/Counter c trn AVR.
SC dHng cc Timer/Counter nh< cc b* .Snh thQi.
SC dHng cc Timer/Counter nh< cc b* .>m.
SC dHng cc Timer/Counter nh< cc b* t:o xung .i/u r*ng PWM.
Vi>t m*t v dH .i/u khi1n .*ng c@ RC servo bZng PWM.
II. TKng quan cc bD Timer/Counter trn chip Atmega8.
Timer/Counter l cc module .*c lAp v?i CPU. ChGc nKng chnh câ
cc b* Timer/Counter, nh< tn g-i câ chng, l .Snh th (t:o ra m*t kho2ng
thQi gian, .>m thQi gian) v .>m s` kiBn. Trn cc chip AVR, cc b*
Timer/Counter cn c thm chGc nKng t:o ra cc xung .i/u r*ng PWM
(Pulse Width Modulation), W m*t sR dng AVR, m*t sR Timer/Counter cn
.<Xc dng nh< cc b* canh chUnh thQi gian (calibration) trong cc Gng dHng
thQi gian th`c. Cc b* Timer/Counter .<Xc chia theo .* r*ng thanh ghi chGa
gi trS .Snh thQi hay gi trS .>m câ chng, cH th1 trn chip Atmega8 c 2 b*
Timer 8 bit (Timer/Counter0 v Timer/Counter2) v 1 b* 16 bit
(Timer/Counter1). Ch> .* ho:t .*ng v ph<@ng php .i/u khi1n câ t;ng
Timer/Counter c7ng khng hon ton giRng nhau, v dH W chip Atmega8:
Timer/Counter0: l m*t b* .Snh thQi, .>m .@n gi2n v?i 8 bit. G-i l
.@n gi2n v b* ny chU c 1 ch> .* ho:t .*ng (mode) so v?i 5 ch> .* câ b*
Timer/Counter1. Ch> .* hoat .*ng câ Timer/Counter0 th`c ch5t c th1 coi
nh< 2 ch> .* nh_ (v c7ng l 2 chGc nKng c@ b2n) . l t:o ra m*t kho2ng
thQi gian v .>m s` kiBn. Ch l trn cc chip AVR dng mega sau ny
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nh< Atmega16,32,64chGc nKng câ Timer/Counter0 .<Xc nng ln nh<
cc b* Timer/Counter1
Timer/Counter1: l b* .Snh thQi, .>m .a nKng 16 bit. B*
Timer/Counter ny c 5 ch> .* ho:t .*ng chnh. Ngoi cc chGc nKng thng
th<Qng, Timer/Counter1 cn .<Xc dng .1 t:o ra xung .i/u r*ng PWM
dng cho cc mHc .ch .i/u khi1n. C th1 t:o 2 tn hiBu PWM .*c lAp trn
cc chn OC1A (chn 15) v OC1B (chn 16) bZng Timer/Counter1. Cc b*
Timer/Counter ki1u ny .<Xc tch hXp thm kh nhi/u trong cc chip AVR
sau ny, v dH Atmega128 c 2 b*, Atmega2561 c 4 b*
Timer/Counter2: tuy l m*t module 8 bit nh< Timer/Counter0 nh<ng
Timer/Counter2 c .>n 4 ch> .* ho:t .*ng nh< Timer/Counter1, ngoi ra n
n cn .<Xc sC dHng nh< m*t module canh chUnh thQi gian cho cc Gng
dHng thQi gian th`c (ch> .* asynchronous).
Trong ph:m vi bi 4 ny, ti ch^ y>u h<?ng dan cch sC dHng 4 ch> .*
ho:t .*ng câ cc Timer/Counter. Ch> .* asynchronous câ Timer/Counter2
sc .<Xc b_ qua v c th1 ch> .* ny khng .<Xc sC dHng phe bi>n.
Tr<?c khi kh2o st ho:t .*ng câ cc Timer/Counter, chng ta thRng nh5t
cch g-i tMt tn g-i câ cc Timer/Counter l T/C, v dH T/C0 .1 chU
Timer/Counter0
II. SU d5ng Timer/Counter.
C m*t sR .Snh ngh\a quan tr-ng m chng ta cLn nMm bMt tr<?c khi sC
dHng cc T/C trong AVR:
BOTTOM: l gi trS th5p nh5t m m*t T/C c th1 .:t .<Xc, gi trS ny
lun l 0.
MAX: l gi trS l?n nh5t m m*t T/C c th1 .:t .<Xc, gi trS ny .<Xc
quy .Snh bWi bWi gi trS l?n nh5t m thanh ghi .>m câ T/C c th1 chGa
.<Xc. V dH v?i m*t b* T/C 8 bit th gi trS MAX lun l 0xFF (tGc 255
trong hB thAp phn), v?i b* T/C 16 bit th MAX bZng 0xFFFF (65535). Nh<
th> MAX l gi trS khng .ei trong mYi T/C.
TOP: l gi trS m khi T/C .:t .>n n sc thay .ei tr:ng thi, gi trS ny
khng nh5t thi>t l sR l@n nh5t 8 bit hay 16 bit nh< MAX, gi trS câ MAX
c th1 thanh .ei bZng cch .i/u khi1n cc bit .i/u khi1n t<@ng Gng hoDc c
th1 nhAp tr; ti>p thng qua m*t sR thanh ghi. Chng ta sc hi1u r v/ gi trS
TOP trong lc kh2o st T/C1.
1. Timer/Counter0:
Thanh ghi: c 4 thanh ghi .<Xc thi>t k> ring cho ho:t .*ng v .i/u
khi1n T/C0, . l:
Ntinside 42
TCNT0 (Timer/Counter Register): l 1 thanh ghi 8 bit chGa gi trS vAn
hnh câ T/C0. Thanh ghi ny cho php b:n .-c v ghi gi trS m*t cch tr`c
ti>p.
TCCR0 (Timer/Counter Control Register): l thanh ghi .i/u khi1n
ho:t .*ng câ T/C0. Tuy l thanh ghi 8 bit nh<ng th`c ch5t chU c 3 bit c
tc dHng . l CS00, CS01 v CS02.

Cc bit CS00, CS01 v CS02 g-i l cc chip ch-n nguPn xung nhSp cho
T/C0 (Clock Select). ChGc nKng cc bit ny .<Xc m t2 trong b2ng 1.
B2ng 1: chGc nKng cc bit CS0X

TIMSK (Timer/Counter Interrupt Mask Register): l thanh ghi mDt n:
cho ngMt câ t5t c2 cc T/C trong Atmega8, trong . chU c bit TOIE0 tGc bit
sR 0 (bit .Lu tin) trong thanh ghi ny l lin quan .>n T/C0, bit ny c tn
l bit cho php ngMt khi c trn W T/C0. Trn (Overflow) l hiBn t<Xng x2y
ra khi b* gi trS trong thanh ghi TCNT0 . .:t .>n MAX (255) v l:i .>m
thm 1 lLn n[a.

Khi bit TOIE0=1, v bit I trong thanh ghi tr:ng thi .<Xc set (xem l:i
bi 3 v/ .i/u khi1n ngMt), n>u m*t trn x2y ra sc dan .>n ngMt trn.
Ntinside 43
TIFR (Timer/Counter Interrupt Flag Register): l thanh ghi cQ nh?
cho t5t c2 cc b* T/C. Trong thanh ghi ny bit sR 0, TOV0 l cQ chU thS ngMt
trn câ T/C0. Khi c ngMt trn x2y ra, bit ny t` .*ng .<Xc set ln 1. Thng
th<Qng trong .i/u khi1n cc T/C vai tr câ thanh ghi TIFR khng qu quan
tr-ng.
Ho3t =Dng: T/C0 ho:t .*ng r5t .@n gi2n, ho:t .*ng câ T/C .<Xc
kch bWi m*t tn hiBu (signal), cG mYi lLn xu5t hiBn tn hiBu kch gi trS
câ thanh ghi TCNT0 l:i tKng thm 1 .@n vS, thanh ghi ny tKng cho .>n khi
n .:t mGc MAX l 255, tn hiBu kch ti>p theo sc lm thanh ghi TCNT0 trW
v/ 0 (trn), lc ny bit cQ trn TOV0 sc t` .*ng .<Xc set bZng 1. V?i cch
thGc ho:t .*ng nh< th> c vf T/C0 v dHng v cG tKng t; 0 .>n 255 rPi l:i
quay v/ khng v qu trnh lDp l:i. Tuy nhin, y>u tR t:o s` khc biBt chnh
l tnh hiBu kch v ngMt trn, k>t hXp 2 y>u tR ny chng ta c th1 t:o ra 1
b* .Snh thQi gian hoDc 1 b* .>m s` kiBn. Tr<?c h>t b:n hy nhn l:i b2ng 1
v/ cc bit ch-n xung nhSp cho T/C0. Xung nhSp cho T/C0 chnh l tn hiBu
kch cho T/C0, xung nhSp ny c th1 t:o bZng nguPn t:o dao .*ng câ chip
(th:ch anh, dao .*ng n*i trong chip). BZng cch .Dt gi trS cho cc bit
CS00, CS01 v CS02 câ thanh ghi .i/u khi1n TCCR0 chng ta sc quy>t
.Snh bao lu th sc kch T/C0 m*t lLn. V dH m:ch Gng dHng câ b:n c
nguPn dao .*ng clkI/O = 1MHz tGc chu kN 1 nhSp l 1us ( 1 micro giy),
b:n .Dt TCCR0=5 (SC02=1, CS01=0, CS00=1), cKn cG theo b2ng 1 tn hiBu
kch cho T/C0 sc bZng clkI/O/1024 ngh\a l sau 1024us th T/C0 m?i .<Xc
kch 1 lLn, ni cch khc gi trS câ TCNT0 tKng thm 1 sau 1024us (ch
l tLn sR .<Xc chia cho 1024 th chu kN sc tKng 1024 lLn). Quan st 2 dng
cuRi cng trong b2ng 1 b:n sc th5y rZng tn hiBu kch cho T/C0 c th1 l5y t;
bn ngoi (External clock source), .y chnh l t<Wng cho ho:t .*ng câ
chGc nKng .>m s` kiBn trn T/C0. BZng cch thay .ei tr:ng thi chn T0
(chn 6 trn chip Atmega8) chng ta sc lm tKng gi trS thanh ghi TCNT0
hay ni cch khc T/C0 c th1 dng .1 .>m s` kiBn x2y ra trn chn T0.
D<?i .y chng ta sc xem xt cH th1 cch .i/u khi1n T/C0 theo 1 ch> .*
.Snh thQi gian v .>m.
1.1 B $%nh th'i gian.
Chng ta c th1 t:o ra 1 b* .Snh th .1 ci .Dt m*t kho2ng thQi gian no
.. V dH b:n muRn rZng cG sau chnh xc 1ms th chn PB0 thay .ei tr:ng
thi 1 lLn (nh5p nhy), b:n l:i khng muRn dng cc lBnh delay nh< tr<?c
nay van dng v nh<Xc .i1m câ delay l CPU khng lm g c2 trong lc
delay, v th> trong nhi/u tr<Qng hXp cc lBnh delay r5t h:n ch> .<Xc sC
dHng. By giQ chng ta dng T/C0 .1 lm viBc ny, t<Wng l chng ta cho
Ntinside 44
b* .>m T/C0 ho:t .*ng, khi n .>m .^ 1ms th n sc t` kch ho:t ngMt trn,
trong trnh phHc vH ngMt trn chng tat hay .ei tr:ng thi chn PB0. Ti
minh h-a t<Wng nh< trong hnh 1.

Hnh 1. So snh 2 cch lm viBc.
(CPU nop: CPU khng lm g c2)
M*t v5n ./ n2y sinh lc ny, nh< ti trnh by trong phLn tr<?c, T/C0
chU .>m t; 0 .>n 255 rPi l:i quay v/ 0 (x2y ra 1 ngMt trn), nh< th> d<Qng
nh< chng ta khng th1 ci .Dt gi trS mong muRn b5t kN cho T/C0? Cu tr2
lQi l chng ta c th1 bZng cch gn tr<?c m*t gi trS cho thanh ghi TCNT0,
khi 5y T/C0 sc .>m t; gi trS m chng ta gn tr<?c v k>t thc W 255. Tuy
nhin do khi trn x2y ra, TCNT0 l:i .<Xc t` .*ng tr2 v/ 0, do . viBc gn
gi trS khWi t:o cho TCNT0 ph2i .<Xc th`c hiBn lin tHc sau mYi lLn x2y ra
trn, vS tr tRt nh5t l .Dt trong trnh phHc vH ngMt trn.
ViBc cn l:i v c7ng l viBc quan tr-ng nh5t l viBc tnh ton gi trS chia
(prescaler) cho xung nhSp câ T/C0 v viBc xc .Snh gi trS khWi .Lu cLn gn
cho thanh ghi TCNT0 .1 c .<Xc 1 kho2ng thQi gian .Snh th chnh xc nh<
mong muRn. Tr<?c h>t chng ta sc ch-n prescaler sao cho hXp l nh5t (ch-n
gi trS chia bZng cch set 3 bit CS02,CS01,CS00). Gi2 sC nguPn xung clock
nui chip câ chng ta l clkI/O=1MHz tGc l 1 nhSp m5t 1us, n>u chng
ta .1 prescaler=1, tGc l tLn sR câ T/C0 (t:m g-i l fT/C0) c7ng bZng
clkI/O=1MHz, cG 1us T/C0 .<Xc kch v TCNT0 sc tKng 1 .@n vS. Khi .
gi trS l?n nh5t m T/C0 c th1 .:t .<Xc l 256 x 1us=256us, gi trS ny nh_
h@n 1ms m ta mong muRn. N>u ch-n prescaler=8 (xem b2ng 1) ngh\a l cG
sau 8 nhSp (8us) th TCNT0 m?i tKng 1 .@n vS, kh2 nKng l?n nh5t m T/C0
.>m .<Xc l 256 x 8us=2048us, l?n h@n 1ms, vAy ta hon ton c th1 sC
dHng prescaler=8 .1 t:o ra m*t kho2ng .Snh th 1ms. B<?c ti>p theo l xc
.Snh gi trS khWi .Lu câ TCNT0 .1 T/C0 .>m .ng 1ms (1000us). (ng v?i
prescaler=8 chng ta . bi>t l cG 8us th TCNT0 tKng 1 .@n vS, dI dng tnh
Ntinside 45
.<Xc b* .>m cLn .>m 1000/8=125 lLn .1 h>t 1ms, do . gi trS ban .Lu câ
TCNT0 ph2i l 256-125=131. B:n c th1 quan st hnh 2 .1 hi1u th5u .o
h@n.

Hnh 2. Qu trnh th`c hiBn.
Hy t:o 1 Project bZng Programmer Notepad v?i tn g-i TIMER0 v
vi>t .o:n code cho Project ny nh< trong list 1.
List 1. bSnh th 1ms v?i T/C0.

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#include <avr/io.h>
#include <util/delay.h>

int main(void){
DDRB=0xFF; //PORTB la output PORT
PORTB=0x00;

TCCR0=(1<<CS01);// CS02=0, CS01=1, CS00=0: chon Prescaler = 8
TCNT0=131; //gan gia tri khoi tao cho T/C0
TIMSK=(1<<TOIE0);//cho phep ngat khi co tran o T/C0
sei(); //set bit I cho phep ngat toan cuc

//do nothing
}
return 0;
}

//trinh phuc vu ngat tran T/C0
ISR (TIMER0_OVF_vect ){
PORTB ^=1; //doi trang thai Bit PB0
}
Ntinside 46

bo:n code r5t .@n gi2n, b:n chU cLn ch .>n 3 dng khai bo cho
T/C0 (dng 9, 10, 11). V?i dng 9: TCCR0=(1<<CS01) l 1 cch set bit
CS01 trong thanh ghi .i/u khi1n TCCR0 ln 1, 2 bit CS02 v CS00 .<Xc .1
gi trS 0 (b:n xem l:i bi 3 v/ cch set cc bit .Dc biBt trong cc thanh ghi),
tm l:i dng ny t<@ng .<@ng TCCR0=2, gi trS Prescaler .<Xc ch-n bZng 8
(tham kh2o b2ng 1). Dng 10 chng ta gn gi trS khWi t:o cho thanh ghi
TCNT0. V dng 11 set bit TIOE0 ln 1 .1 cho php ngMt x2y ra khi c trn
W T/C0. Trong trnh phHc vH ngMt trn T/C0, chng ta sc th`c hiBn .ei tr:ng
thi chn PB0 bZng ton t; XOR (^), ch .>n ngh\a câ ton tC XOR:
n>u XOR m*t bit v?i sR 1 th bit ny sc chuy1n tr:ng thi (t; 0 sang 1 v
ng<Xc l:i). CuRi cng v quan tr-ng l chng ta cLn gn l:i gi trS khWi t:o
cho T/C0.
B:n c th1 vc mt m:ch .iBn m ph_ng .@n gi2n dng 1 Oscilloscope nh<
trong hnh 3 .1 ki1m tra ho:t .*ng câ .o:n code.

Hnh 3. M ph_ng .Snh th câ T/C0.
1.2 B $*m s- ki/n.
Nh< ti trnh by trong phLn ho:t .*ng câ T/C0, chng ta c th1 dng
T/C0 nh< m*t b* .>m (counter) .1 .>m cc s` kiBn (s` thay .ei tr:ng thi)
x2y ra trn chn T0. BZng cch .Dt gi trS cho thanh ghi TCCR0 = 6
(CS02=1, CS01=1, CS00=0) cho php .>m c:nh xuRng trn chn T0, n>u
TCCR0 = 7 (CS02=1, CS01=1, CS00=1) th c:nh ln trn chn T0 sc
.<Xc .>m. C sC dHng ngMt hay khng phH thu*c vo mHc .ch sC dHng.
Kh2o st 1 v dH .@n gi2n gLn giRng v?i v dH .>m trong bi AVR2 nh<ng
sC dHng T/C0 v chU .>m 1 chi/u tKng. K>t nRi m:ch .iBn nh< trong hnh 4,
Ntinside 47
mYi lLn Button 1 .<Xc nh5n, gi trS .>m tKng thm 1. Button 2 dng reset gi
trS .>m v/ 0. bo:n code cho v dH thG 2 ny .<Xc trnh by trong List 2.

Hnh 4. b>m 1 chi/u bZng T/C0.
List 2. b>m s` kiBn v?i T/C0

N*i dung trong ch<@ng trnh chnh l khai bo cc h<?ng giao ti>p cho
cc PORT, PORTB l ouput .1 xu5t k>t qu2 .>m ra led 7 .o:n, PORTD

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#include <avr/io.h>

int main(void){
PORTB=0x00;
DDRD=0x00; //khai bao PORTD la input de ket noi Button kich vao chan T0
PORTD=0xFF; //su dung dien tro keo len cho PORTD

TCCR0=(1<<CS02)|(1<<CS01);// CS02=1, CS01=1, CS00=0: xung nhip tu chan T0, down
TCNT0=0;

if (TCNT0==10) TCNT0=0;
PORTB=TCNT0; //xuat gia tri dem ra led 7 doan
if (bit_is_clear(PIND,7)) TCNT0=0; //Reset bo dem neu chan PD7=0
}
return 0;
}
Ntinside 48
.<Xc khi bo input v cc button .<Xc nRi v?i PORT ny. T/C0 .<Xc khai
bo sC dHng nguPn kch ngoi t; T0, d:ng c:nh xuRng thng qua dng
TCCR0=(1<<CS02)|(1<<CS01), b:n c7ng c th1 khai bo t<@ng .<@ng l
TCCR0=6 (tham kh2o b2ng 1). Gi trS câ b* .>m sc .<Xc xu5t ra PORTB
.1 ki1m tra. bi1m ch trong .o:n ch<@ng trnh ny l macro
bit_is_clear, .y l m*t macro .<Xc .Snh ngh\a trong file sfr_defs.h
dng .1 ki1m tra 1 bit trong m*t thanh ghi .Dc biBt c .<Xc xa (bZng 0) hay
khng, trong tr<Qng hXp câ .o:n code trn: if(bit_is_clear(PIND,7))
TCNT0=0; ngh\a l ki1m tra xem n>u chn PD7 .<Xc ko xuRng 0 (button
2 .<Xc nh5n) th sc reset b* .>m v/ 0.
Nh< vAy viBc sC dHng T/C0 l t<@ng .Ri .@n gi2n, b:n chU cLn khai bo
cc gi trS thch hXp cho thanh ghi .i/u khi1n TCCR0 bZng cch tham kh2o
b2ng 1, sau . khWi t:o gi trS cho TCNT0 (n>u cLn thi>t), khai bo c sC
dHng ngMt hay khng bZng cch set hay khng set bit TOIE0 trong thanh ghi
TIMSK l hon t5t.
2. Timer/Counter1:
Timer/Counter1 l b* T/C 16 bits, .a chGc nKng. by l b* T/C r5t l
t<Wng cho lAp trnh .o l<Qng v .i/u khi1n v c .* phn gi2i cao (16 bits)
v c kh2 nKng t:o xung .i/u r*ng PWM (Pulse Width Modulation th<Qng
dng .1 .i/u khi1n .*ng c@).
Thanh ghi: c kh nhi/u thanh ghi lin quan .>n T/C1. V l T/C 16
bits trong khi .* r*ng b* nh? d[ liBu câ AVR l 8 bit (xem l:i bi 2) nn
.i khi cLn dng nh[ng cDp thanh ghi 8 bits t:o thnh 1 thanh ghi 16 bit, 2
thanh ghi 8 bits sc c tn k>t thc bZng cc k t` L v H trong . L l thanh
ghi chGa 8 bits th5p (LOW) v H l thanh ghi chGa 8 bits cao (High) câ gi
trS 16 bits m chng t:o thnh.
TCNT1H v TCNT1L (Timer/Counter Register): l 2 thanh ghi 8 bit t:o thnh thanh ghi 16 bits
(TCNT1) chGa gi trS vAn hnh câ T/C1. C2 2 thanh ghi ny cho php b:n .-c v ghi gi trS m*t cch tr`c ti>p.
2 thanh ghi .<Xc k>t hXp nh< sau:

TCCR1A v TCCR1B (Timer/Counter Control Register): l 2 thanh
ghi .i/u khi1n ho:t .*ng câ T/C1. T5t c2 cc mode ho:t .*ng câ T/C1 ./u
.<Xc xc .Snh thng qua cc bit trong 2 thanh ghi ny. Tuy nhin, .y
Ntinside 49
khng ph2i l 2 byte cao v th5p câ m*t thanh ghi m l 2 thanh ghi hon
ton .*c lAp. Cc bit trong 2 thanh ghi ny bao gPm cc bit ch-n mode hay
ch-n d:ng sng (Waveform Generating Mode WGM), cc bit quy .Snh
d:ng ng ra (Compare Output Match COM), cc bit ch-n gi trS chia
prescaler cho xung nhSp (Clock Select CS)C5u trc câ 2 thanh ghi
.<Xc trnh by nh< bn d<?i.

Nhn chung .1 thu*c h>t cch phRi hXp cc bit trong 2 thanh ghi TCCR1A v TCCR1B l t<@ng .Ri
phGc t:p v T/C1 c r5t nhi/u mode ho:t .*ng, chng ta sc kh2o st chng trong phLn cc ch> .* ho:t .*ng câ
T/C1 bn d<?i. % .y, trong thanh ghi TCCR1B c 3 bit kh quen thu*c l CS10, CS11 v CS12. by l cc bit
ch-n xung nhSp cho T/C1 nh< truong T/C0. B2ng 2 sc tm tMt cc ch> .* xung nhSp trong T/C1.
B2ng 2: chGc nKng cc bit CS12, CS11 v CS10.

OCR1A v OCR1B (Ouput Compare Register A v B): c m*t sR khi niBm m?i m chng ta cLn bi>t
khi lm viBc v?i T/C1, m*t trong sR . l Ouput Compare (sorry, I dont wanna translate it to Vietnamese).
Trong lc T/C ho:t .*ng, gi trS thanh ghi TCNT1 tKng, gi trS ny .<Xc lin tHc so snh v?i cc thanh ghi
OCR1A v OCR1B (so snh .*c lAp v?i t;ng thanh ghi), viBc so snh ny trn AVR g-i l g-i l Ouput
Compare. Khi gi trS so snh bZng nhau th 1 Match x2y ra, khi . m*t ngMt hoDc 1 s` thay .ei trn chn
OC1A (hoDc/v chn OC1B) x2y ra (.y l cch t:o PWM bWi T/C1). T:i sao l:i c A v B? b l v ng<Qi thi>t
k> AVR muRn mW r*ng kh2 nKng Gng dHng T/C1 cho b:n. A v B .:i diBn cho 2 knh (channel) v B. C7ng v
.i/u ny m chng ta c th1 t:o 2 knh PWM bZng T/C1. Tm l:i, c@ b2n 2 thanh ghi ny chGa cc gi trS .1 so
snh, chGc nKng v cc ch> .* ho:t .*ng cH th1 câ chng sc .<Xc kh2o st trong cc phLn sau.
Ntinside 50

ICR1 (InputCapture Register 1): khi niBm m?i thG 2 câ T/C1 l Input Capture. Khi c 1 s` kiBn trn
chn ICP1 (chn 14 trn Atmega8), thanh ghi ICR1sc capture gi trS câ thanh ghi .>m TCNT1. M*t ngMt c
th1 x2y ra trong tr<Qng hXp ny, v th> Input Capture c th1 .<Xc dng .1 cAp nhAt gi trS TOP câ T/C1.
TIMSK (Timer/Counter Interrupt Mask Register): cc b* T/C trn AVR dng chung thanh ghi mDt n:
ngMt, v th> TIMSK c7ng .<Xc dng .1 quy .Snh ngMt cho T/C1. C .i/u lc ny chng ta chU quan tm .>n cc
bit t; 2 .>n 5 câ TIMSK. C t5t c2 4 lo:i ngMt trn T/C1 (nh? l:i T/C0 chU c 1 lo:i ngMt trn)

Bit 2 trong TIMSK l TOIE1, bit quy .Snh ngMt trn cho thanh T/C1 (t<@ng t` tr<Qng hXp câ T/C0).
Bit 3, OCIE1B l bit cho php ngMt khi c 1 Match x2y ra trong viBc so snh TCNT1 v?i OCR1B.
Bit 4, OCIE1A l bit cho php ngMt khi c 1 Match x2y ra trong viBc so snh TCNT1 v?i OCR1A.
Bit 5, TICIE1 l bit cho php ngMt trong tr<Qng hXp Input Capture .<Xc dng.
Cng v?i viBc set cc bit trn, bit I trong thanh ghi tr:ng thi ph2i .<Xc set n>u muRn sC dHng ngMt (xem
l:i bi 3v/ .i/u khi1n ngMt).
TIFR (Timer/Counter Interrupt Flag Register): l thanh ghi cQ nh? cho t5t c2 cc b* T/C. Cc bit t; 2
.>n 5 trong thanh ghi ny l cc cQ tr:ng thi câ T/C1.

Cc mode ho:t .*ng: c t5t c2 5 ch> .* ho:t .*ng chnh trn T/C1. Cc
ch> .* ho:t .*ng c@ b2n .<Xc quy .Snh bWi 4 bit Waveform Generation
Mode (WGM13, WGM12, WGM11 WGM10) v m*t sR bit phH khc. 4 bit
Waveform Generation Mode l:i .<Xc bR tr nZm trong 2 thanh ghi TCCR1A
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v TCCR1B (WGM13 l bit 4, WGM12 l bit 3 trong TCCR1B trong khi
WGM11 l bit 1 v WGM10 l bit 0 trong thanh ghi TCCR1A) v th> cLn
phRi hXp 2 thanh ghi TCCR1 trong lc .i/u khi1n T/C1. Cc ch> .* ho:t
.*ng câ T/C1 .<Xc tm tMt trong b2ng sau 3:
B2ng 3: cc bit WGM v cc ch> .* ho:t .*ng câ T/C1.
2.1 Normal mode (Ch* $ th.'ng).
by l ch> .* ho:t .*ng .@n gi2n nh5t câ T/C1. Trong ch> .* ny,
thanh ghi .>m TCNT1 .<Xc tKng gi trS t; 0 (BOTTOM) .>n 65535 hay
0xFFFF (TOP) v quay v/ 0. Ch> .* ny hon ton giRng cch m Timer0
ho:t .*ng chU c khc l gi trS .>m cao nh5t l 65535 thay v 255 nh< trong
timer0. Nhn vo b2ng 3, .1 set T/C1 W Normal mode chng ta cLn set 4 bit
WGM v/ 0, v 0 l gi trS mDc .Snh câ cc thanh ghi nn th`c t> chng ta
khng cLn tc .*ng .>n cc bit WGM. Duy nh5t m*t viBc quan tr-ng cLn
lm l set cc bit Clock Select (CS12, SC11, CS10) trong thanh ghi
TCCR1B (xem thm b2ng 2). B:n c th1 tham kh2o v dH câ Timer0. bo:n
code trong list 3 l 1 v dH t:o 1 kho2ng thQi gian 10ms bZng T/C1, normal
mode:
List 3. bSnh th 10ms v?i T/C1.

#include <avr/io.h>

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int main(void){
PORTB=0x00;

TCCR1B=(1<CS10);// CS12=0, CS11=0, CS10=1: chon Prescaler =1
// thanh ghi TCCR1B duoc dung thay vi TCCR0 cua Timer0
TIMSK=(1<<TOIE1);//cho phep ngat khi co tran o T/C1

//do nothing
}
return 0;
}
//trinh phuc vu ngat tran T/C1
ISR (TIMER1_OVF_vect ){
PORTB ^=1; //doi trang thai Bit PB0
}

2.2 Clear Timer on Compare Match (xa timer n*u x0y ra b3ng trong so
snh)-CTC.
M*t cch g-i tMt câ ch> .* ho:t .*ng ny l CTC, m*t ch> .* ho:t
.*ng m?i trn T/C1. Nhn vo b2ng 3 b:n sc th5y c 2 mode CTC (mode 4
v mode 12). Ti l5y v dH mode 4 .1 gi2i thch ho:t .*ng câ CTC. Khi b:n
set cc bit Waveform Generation Mode tuong Gng: WGM13=0, WGM12=1,
WGM11=0, WGM10=0 th mode 4 .<Xc ch-n. Trong mode ny, thanh ghi
OCR1A chGa gi trS TOP (gi trS so snh do ng<Qi dng .Dt), thanh ghi .>m
TCNT1 tKng t; 0, khi TCNT1 bZng gi trS chGa trong OCR1A th m*t
Compare Match x2y ra. Khi ., m*t ngMt c th1 x2y ra n>u chng ta cho
php ngMt Compare Match (set bit OCF1A trong thanh ghi TIMSK ln 1).
Mode ny c7ng t<@ng .Ri .@n gi2n, m*t Gng dHng c@ b2n câ mode ny l
.@n gi2n ha viBc .>m cc s` kiBn bn ngoi. V dH b:n k>t nRi 1 sensor
.>m sR ng<Qi .i vo 1 cKn phng v?i ch5n T1 (chn counter source câ
T/C1), b:n muRn rZng cG sau khi .>m 5 ng<Qi th sc thng bo 1 lLn. List 4
l .o:n code m t2 v dH ny:
List 4. PhRi hXp CTC v?i .>m s` kiBn.
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#include <avr/io.h>
volatile usigned char val=0; //khai bao 1 bien tam val va khoi tao =0
int main(void){
PORTB=0x00;
TCCR1B=GM12)|(1<<CS12)|(1<<CS11);//xung nhip tu chan T1, canh xuong
OCR1A=4; //gan gia tri can so sanh
TIMSK=(1<OCIE1A);//cho phep ngat khi gia tri dem bang 4

//do nothing
}
return 0;
}
//trinh phuc vu ngat compare match
ISR (TIMER1_COMPA_vect){
val++;
if (val==10) val=0; //gioi han bien val tu 0 den 9
PORTB =val; //xuat gia tri ra PORTB
}

Ti chU gi2i thch nh[ng .i1m m?i trong List 4. ThG nh5t l attribute
volatile dng tr<?c khai bo bi>n val, bi>n val .<Xc khai bo l unsigned
char (8 bit, khng d5u) dng chGa gi trS t:m thQi .1 xu5t ra PORTB khi c
ngMt x2y ra. bi/u .Dc biBt l t; kha volatile .Dt tr<?c n, volatile l m*t
thu*c tnh (attribute) câ b* bin dSch gcc-avr, n ni v?i trnh dSch rZng
bi>n val sc .<Xc dng trong ch<@ng trnh chnh v c2 trong cc trnh phHc
vH ngMt. N>u b:n muRn cAp nhAp gi trS 1 bi>n ton cHc trong cc trnh phHc
vH ngMt m bi>n . khng .<Xc chU .Snh thu*c tnh volatile tr<?c th qu
trnh cAp nhAt th5t b:i. M*t cch dI hi1u h@n, b:n xem trnh ISR trong v dH
trn, cG mYi lLn c ngMt Compare Match x2y ra, bi>n val .<Xc tKng thm 1
(dng 21) sau . ki1m tra .i/u kiBn bZng 10 hay khng v cuRi cng l gn
cho PORTB. N>u trong khai bo câ val (dng 4) chng ta khng chU .Snh
volatile th gi trS xu5t ra PORTB sc lun l 1 khi c ngMt. Ch l .i/u ny
chU .ng it nh5t l v?i phin b2n WinAVR thng 12 nKm 2007, cc phin
b2n sau c th1 khng cLn dng volatile (ti sc cAp nhAt sau).
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Dng 8 set cc bit .i/u khi1n: TCCR1B=(1<<WGM12)|(1<<CS12)|(1<<CS11); b:n th5y ti chU set bit
WGM12 trong 4 bit WGM v ti muRn ch-n mode CTC 4 (xem b2ng 3). Hai bit CS12 v CS11 .<Xc set bZng 1
trong khi CS10 .<Xc gi[ W 0 .1 ch-n xung clock l t; bn ngoi, chn T1 (xem b2ng 2). Trong dng 10,
OCR1A=4; l gi trS cLn so snh, chng ta bi>t rZng TCNT1 tKng ln t; 0, v th> .1 .>m 5 s` kiBn th cLn .Dt gi
trS so snh l 4 (0, 1, 2, 3, 4). Dng 11 set bit cho php ngMt khi c Compare match x2y ra (dng cho channel A).
Mode 12 câ CTC (WGM13=1, WGM12=1, WGM11=0, WGM10=0) c7ng t<@ng t` mode 4 nh<ng ci
khc l gi trS cLn so snh .<Xc chGa trong thanh ghi ICR1 (khng ph2i OCR1A hay OCR1B). Khi . n>u muRn
dng ngMt th b:n ph2i dng ngMt Input capture. CH th1 dng 8 trong list 4 .ei thnh: TCCR1B=(1<<WGM13)|(
(1<<WGM12)|(1<<CS12)|(1<<CS11); dng 10: ICR1=4 v dng 20: ISR (TIMER1_CAPT_vect ){
M*t kh2 nKng khc câ CTC l xu5t tn hiBu xung vung trn chn OC1A (chn 15 trn Atmega8) bZng
cch set cc bit Compare Output Mode trong thanh ghi TCCR1A. Tuy nhin viBc t:o cc tn hiBu output trong
mode CTC khng thAt s` th vS. V vAy chng ta sc kh2o st cch t:o tn hiBu output trong 1 ch> .* chuyn
nghiBp v th vS h@n, ch> .* PWM.
Tr<?c khi bMt .Lu lm viBc v?i cc ch> .* PWM ti ngh\ cLn thi>t gi?i thiBu th> no l PWM v nhMc l:i
cc khi niBm gi trS .>m câ Timer1 (hay b5t kN timer no khc) trn AVR. Tr<?c h>t, PWM hay Pulse Width
Modulation .<Xc hi1u theo ngh\a ti>ng ViBt l xung .i/u r*ng l khi niBm chU tn hiBu xung m th<Qng th
chu kN (Time period) câ n .<Xc cR .Snh, duty cycle (thQi thQi gian tn hiBu W mGc HIGH) câ n c th1 .<Xc
thay .ei. B:n xem 1 v dH v/ PWM trong hnh 5.

Hnh 5. V dH v/ tn hiBu PWM.
T:o ra PWM tGc l t:o ra nh[ng tn hiBu xung m ta c th1 .i/u khi1n
duty cycle (v c2 tLn sR ~ Time period n>u cLn thi>t). Timer 1 trsn
Atmega8 l 1 module l t<Wng .1 t:o ra cc tn hiBu d:ng ny. Nh<ng PWM
dng .1 lm g v cch m n .<Xc sC dHng nh< th> no? Ti l5y m*t v dH
nh< trong hnh 6: m*t .*ng c@ DC v m*t switch button.
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Hnh 6. Motor v switch.
N>u nh5n button th .*ng c@ ho:t .*ng, th2 button th .*ng c@ d;ng.
Tuy nhin do tRc .* nh5n v th2 câ con ng<Qi c h:n, b:n sc th5y .*ng c@
ho:t .*ng h@i s<Xng (ripple). bi/u g x2y ra n>u b:n nh5n v th2 button
v?i vAn tRc 5000 lLn/giy. Cu tr2 lQi l tay b:n sc bS gy v button sc bS
h_ng (^^). 5000 lLn/s l .i/u khng t<Wng, tuy nhin n>u b:n lm .<Xc nh<
th> th teng thQi gian cho 1 lLn nh5n+th2 l 1:5000=0.0002s = 200us. C s`
khc biBt no khng gi[a tr<Qng hXp thQi gian nh5n = 150us, thQi gian th2
50us v tr<Qng hXp thQi gian nh5n l 50us cn thQi gian th2 l 150us. B:n sc
dI dng tm cu tr2 lQi, trong tr<Qng hXp 1 .*ng c@ sc quay v?i vAn tRc
nhanh h@n tr<Qng hXp 2. b l t<Wng c@ b2n .1 sC dHng PWM .i/u khi1n
vAn tRc .*ng c@ (v .i/u khi1n nhi/u thG khc n[a). .1 bi>n ci khng t<Wng
trn (5000 lLn/s) thnh hiBn th`c, chng ta sc thay th> ci button c@ kh kia
bZng 1 cng tMc .iBn tC (electronics switch). Th<Qng th cc chip MOSFET
.<Xc dng lm cc kha .iBn tC. MOSFET th<Qng c 3 chn G (gate), D
(drain) v S (source). V dH 1 MOSFET knh N W tr:ng thi thng th<Qng 2
chn D v S ko c dng .iBn ch:y qua, n>u .iBn p chn G l?n h@n chn S
kho2ng 3V trW ln th dng .iBn c th1 ch:y t; D sang S. hy xem cch m
t2 t<@ng .<@ng 1 MOSFET v?i 1 button trong hnh 7.
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Hnh 7. MOSFET v button.
ViBc kch cc MOSFET c th1 th`c hiBn bZng cc tn hiBu PWM. V
th> t<Wng .i/u khi/n .*ng c@ trong hnh 6 c th1 .<Xc th`c hiBn l:i thng
qua PWM nh< trong hnh 8.

Hnh 8. M hnh .i/u khi1n tRc .* .*ng c@ bZng PWM .@n gi2n.
Nh< vAy l xong phLn gi?i thiBu v/ PWM, by giQ chng ta sang cc
khi niBm sR .>m trong Timer. Hnh 9 minh h-a cch bR tr cc sR .>m
trong Timer1 trn hB trHc .>m.

Hnh 9: cc mRc gi trS câ T/C1.
BOTTOM lun .<Xc cR .Snh l 0 (gi trS nh_ nh5t), MAX lun l
0xFFFF (65535). TOP l gi trS .Unh do ng<Qi dng .Snh ngh\a, gi trS câ
TOP c th1 .<Xc cR .Snh l 0xFF (255), 0x1FF (511), 0x3FF 91023) hoDc
.Snh ngh\a bWi cc thanh ghi ICR1 hoDc OCR1A. th`c ch5t .Ri v?i Gng dHng
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PWM th TOP chnh l Time period câ PWM. Do mHc .ch sC dHng m c
th1 ch-n TOP l cc gi trS cR .Snh hay cc thanh ghi, ring v?i ti, cho mHc
.ch t:o tn hiBu PWM ti ch-n TOP .Snh ngh\a bWi thanh ghi ICR1. Ouput
Compare l gi trS so snh câ b* Timer. Trong ch> .* PWM th Output
Compare quy .Snh Duty cycle. V?i T/C1, Output Comapre l gi trS trong
cc thanh ghi OCR1A v OCR1B. Do c 2 thanh ghi .*c lAp A v B, t<@ng
Gng chng ta c th1 t:o ra 2 tn hiBu PWM trn 2 chn OC1A v OC1B bZng
T/C1. b .>n lc chng ta tm hi1u cch t:o PWM trn AVR.
2.3 Fast PWM (PWM t5n s6 cao).
Trong ch> .* Fast PWM, 1 chu kN .<Xc tnh trong 1 lLn .>m t;
BOTTOM ln TOP (single-slope), v th> m ch> .* ny g-i l Fast PWM
(PWM nhanh). C t5t c2 5 mode trong Fast PWM t<@ng Gng v?i 5 cch
ch-n gi trS TOP khc nhau (tham kh2o b2ng 3). ViBc xc lAp ch> .* ho:t
.*ng cho Fast PWM th`c hiBn thng qua 4 bit WGM v cc bit ch-n d:ng
xung ng ra, Compare Output Mode trong thanh ghi TCCR1A, nhn l:i 2
thanh ghi TCCR1A v TCCR1B.

Ch cc bit COM1A1, COM1A0 v COM1B1, COM1B0 l cc bit
ch-n d:ng tn hiBu ra câ PWM (Compare Output Mode bits). COM1A1,
COM1A0 dng cho knh A v COM1B1, COM1B0 dng cho knh B. Hy
.Ri chi>u b2ng 4.
B2ng 4: m t2 cc bit COM trong ch> .* fast PWM.

Ti sc gi2i thch ho:t .*ng câ Fast PWM knh A thng qua 1 tr<Qng
hXp cH th1, mode 14 (WGM13=1, WGM12=1, WGM11=1, WGM10=0).
Trong mode 14, gi trS TOP (c7ng l chu kN câ PWM) .<Xc chGa trong
thanh ghi ICR1, khi ho:t .*ng thanh ghi TCNT1 tKng gi trS t; 0, gi2 sC cc
bit phH COM1A=1, COM1A0=0, lc ny tr:ng thi câ chn OC1A (chn
15) l HIGH (5V), khi TCNT1 tKng .>n bZng gi trS câ thanh ghi OCR1A
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th chn OC1A .<Xc xa v/ mGc LOW (0V), thanh ghi .>m TCNT1 van
ti>p tHc tKng .>n khi no n bZng gi trS TOP chGa trong thanh ghi ICR1 th
TCNT1 t` .*ng reset v/ 0 v chn OC1A trW v/ tr:ng thi HIGH, ci ny
g-i l Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at TOP
m b:n th5y trong hng 4 b2ng 4. Hnh 10 m t2 cch t:o xung PWM trn
chn OC1A W mode 14.

Hnh 10: Fast PMW mode 14.
R rng chng ta c th1 .i/u khi1n c2 time period v duty cycle câ
PWM bZng 2 thanh ghi ICR1 v OCR1A. Thng th<Qng gi trS câ ICR1
.<Xc tnh ton v gn cR .Snh, gi trS câ OCR1A .<Xc thay .ei .1 th`c
hiBn mHc .ch .i/u khi1n (nh< thay .ei vAn tRc .*ng c@). Ch l n>u
chng ta set cc bit phH ng<Xc l:i: COM1A=0, COM1A0=1, th tn hiBu
PWM trn chn OC1A sc c phLn LOW t; 0 .>n OCR1A v HIGH t;
OCR1A .>n ICR1, .y g-i l set OC1A/OC1B on Compare Match, clear
OC1A/OC1B at TOP (ng<Xc v?i tn hiBu trn hnh 10). Ho:t .*ng câ fast
PWM knh B hon ton t<@ng t`, trong . thanh ghi ICR1 c7ng chGa TOP
câ PWM knh B v thanh ghi ICR1B chGa duty cycle. Nh< vAy 2 knh A
v B c cng tLn sR hay Time period v duty cycle .<Xc .i/u khi1n .*c lAp.
Chn xu5t tn hiBu PWM câ knh B l chn OC1B (chn 16 trn Atmega8).
Cc mode 5, 6 v 7 câ Fast PWM ho:t .*ng hon ton t<@ng t` mode 14.
bi1m khc nhau c@ b2n l gi trS TOP(Time period). Trong cc mode ny
gi trS TOP khng do thanh thi ICR1 .Snh ngh\a m l cc hZng sR khng
.ei. V?i mode 5, tGc mode 8 bits, (WGM13=0, WGM12=1, WGM11=0,
WGM10=1) gi trS TOP l 1 hZng sR, TOP = 255 (sR 8 bits l?n nh5t). V?i
mode 6, tGc mode 9 bits, (WGM13=0, WGM12=1, WGM11=1, WGM10=0)
gi trS TOP l 1 hZng sR, TOP = 511 (sR 9 bits l?n nh5t). V v?i mode 7, tGc
mode 10 bits, (WGM13=0, WGM12=1, WGM11=1, WGM10=1) TOP
=1023 (sR 10 bits l?n nh5t). Mode 15 c7ng l Fast PWM trong . TOP do
OCR1A quy .Snh, v th> m tn hiBu ra W knh A hLu nh< khng ph2i l 1
xung, n chU thay .ei tr:ng thi trong 1 clock. Theo ti, .1 sC dHng Fast
PWM b:n nn dng mode 14 . .<Xc gi2i thch trn. Cc mode 5, 6, 7 c7ng
c th1 dng nh<ng khng nn dng mode 15.
Chng ta ti>n hnh vi>t 1 v dH minh h-a dng 2 knh W ch> .* fast
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PWM .i/u khi1n 2 .*ng c@ RC servo (g-i tMt l Servo). M:ch .iBn minh h-a
nh< trong hnh 11.

Hnh 11: bi/u khi1n 2 RC servo bZng PWM.
Hai button .<Xc nRi v?i 2 ng ngMt ngoi INT0 v INT1 .1 .i/u khi1n
gc xoay câ 2 Servo. Tn câ Servo trong phLn m/m Proteus l MOTOR-
PWMSERVO. Tr<?c khi vi>t code .i/u khi1n cc Servo, b:n cLn bi>t cch
.i/u khi1n chng, ti gi?i thiBu ngMn g-n nh< sau:
RC servo l m*t te hXp gPm 1 .*ng c@ DC cng su5t nh_, h*p gi2m tRc
v b* .i/u khi1n gc quay. C 2 lo:i chnh l Servo th<Qng v digital Servo,
trong v dH ny ti gi?i thiBu Servo th<Qng (phe bi>n). Servo th<Qng c 3
dy, dy mu .en l dy GND, dy ._ l dy nguPn (th<Qng l 5V) v 1 dy
trMng hoDc vng v dy .i/u khi1n (c m*t sR lo:i Servo c mu dy khc,
b:n cLn tham kh2o datasheet câ chng). V cc Servo . c sdn m:ch .i/u
khi1n gc quay bn trong nn chng ta khng cLn b5t cG gi2i thuAt g m chU
cLn c5p tn hiBu PWM cho dy .i/u khi1n l Servo c th1 xoay .>n 1 vS tr
no . (ch l Servo th<Qng chU xoay n[a vng, .i/u khi1n servo l .i/u
khi1n gc xoay chG khng ph2i .i/u khi1n cAn tRc xoay). Hnh 12 l hnh
2nh servo v cch .i/u khi1n servo.
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Hnh 12. Servo v cch .i/u khi1n.
B:n xem hnh 12b, .1 .i/u khi1n servo b:n cLn c5p cho dy .i/u khi1n
m*t tn hiBu PWM c Time Period kho2ng 20ms, duty cycle câ PWM sc
quy>t .Snh gc xoay câ servo. V?i Duty cycle l 1ms, servo xoay v/ vS tr
0o, khi duty cycle =2ms, gc xoay sc l 180o, t; . b:n c th1 tnh .<Xc
duty cycle cLn thi>t khi b:n muRn servo xoay .>n 1 vS tr b5t kN gi[a 0o v
180o. Sau khi hi1u cch .i/u khi1n servo, chng ta c th1 dI dng vi>t code
.i/u khi1n chng, chU cLn t:o cc xung PWM bZng T/C1. bo:n code cho v
dH ny .<Xc trnh by trong list 5.
List 5. bi/u khi1n Servo bZng PWM.

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#include <avr/io.h>

int main(void){
PORTB=0x00;

MCUCR|=(1<<ISC11)|(1<<ISC01); //ngat canh xuong
GICR |=((1<<INT1)|(1<<INT0); //cho php 2 ngat hoat dong

TCCR1A=(1<<COM1A1)|(1<<COM1B1)|(1<<WGM11);
TCCR1B=(1<<WGM13)|(1<<WGM12)|(1<<CS10);
OCR1A=1000; //Duty cycle servo1=1000us=1ms (0 degree)
OCR1B=1500; //Duty cycle servo2=1500us=1.5ms (90 degree)
ICR1=20000; //Time period = 20000us=20ms

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//do nothing
}
return 0;
}

//trinh phuc vu ngat ngoai
ISR (INT0_vect ){
if (OCR1A==1000) OCR1A=1500; //thay doi goc xoay servo1 den 90 do
else OCR1A = 1000; // thay doi goc xoay servo1 den 0 do
}
ISR (INT1_vect ){
if (OCR1B==1000) OCR1B=1500; //thay doi goc xoay servo1 den 90 do
else OCR1B = 1000; // thay doi goc xoay servo1 den 0 do
}

V?i v dH ny ti chU cLn gi2i thch cc dng t; 11 .>n 15 lin quan .>n
viBc xc lAp ch> .* ho:t .*ng Fast PWM mode 14 inverse, phLn cn l:i b:n
.-c t` .Ri chi>u v?i cc bi tr<?c. Dng 11 v 12 th`c hiBn set cc bit .i/u
khi1n Timer1, tr<?c h>t l cc bit COM. B:n th5y ti chU set 2 bit COM1A1
v COM1B1: (1<<COM1A1)|(1<<COM1B1). Hai bit COM1A0 v
COM1B0 khng set tGc mDc .Snh bZng 0. bRi chi>u v?i b2ng 4 b:n th5y
chng ta sc dng Clear OC1A/OC1B on Compare Match, set OC1A/OC1B
at TOP cho t5t c2 2 knh A v B. Chng ta set 3 bit WGM13, WGM12
(thanh ghi TCCR1B, dng 12) v WGM11 (thanh ghi TCCR1A, dng 11)
nh< th> thu .<Xc te hXp (WGM13=1, WGM12=1, WGM11=1, WGM10=0)
tGc l mode 14 .<Xc ch-n (b2ng 3). Cn l:i chng ta set bit CS10 .1 khai
bo rZng nguPn xung clock cho Timer1 bZng clock cho vi .i/u khi1n
(prescaler=1) tGc l 1us trong t<Qng hXp f=1Mhz. (n>u b:n dng cc trnh
bin dSch khc khng hY trX .Snh ngh\a tn cc bit th 2 dng 11 v 12 t<@ng
.<@ng: TCCR1A=0xA2; TCCR1B=0x19).
Dng 15 chng ta khai nhAp gi trS cho ICR1 c7ng l Time period cho
PWM, ICR1=20000 chng ta thu .<Xc Time period =20000 us = 20ms th_a
yu cLu câ servo. Hai dng 13 v 14 khai bo gi trS ban .Lu câ cc duty
cycle câ 2 knh PWM, cc gi trS ny .Snh vS tr gc xoay câ cc servo.
Trong 2 trnh phHc vH ngMt, cc gi trS ny .<Xc thay .ei khi cc button .<Xc
nh5n.
Phase correct PWM cung c5p m*t ch> .* t:o xung PWM c .* phn
gi2i cao (high resolution) nn .<Xc g-i l Phase correct PWM. T<@ng t`
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Fast PWM, c7ng c 5 mode ho:t .*ng thu*c Phase correct PWM . l cc
mode 1, 2, 3, 10 v 11 (xem b2ng 3). NKm mode ny t<@ng Gng cc mode 5,
6, 7, 14 v 15 câ fast PWM. V/ cch .i/u khi1n, Phase correct hLu nh<
giRng fast PWM, ngh\a l n>u b:n . bi>t cch sC dHng cc mode câ fast
PWM th b:n sc hon ton .i/u khi1n .<Xc Phase correct PWM. Khc nhau
c@ b2n câ 2 ch> .* ny l trong cch ho:t .*ng, n>u Fast PWM c chu kN
ho:t .*ng trong 1 single-slope (m*t s<Qn) th Phase correct PWM l:i dual-
slope (hai s<Qn). L5y v dH mode 10 câ Phase correct PWM t<@ng Gng v?i
mode 14 câ Fast PWM, trong mode ny thanh ghi ICR1 chGa TOP v
OCR1A (hoDc OCR1B .Ri v?i knh B) chGa gi trS so snh. Khi ho:t .*ng,
thanh ghi TCNT1 tKng t; 0, khi TCNT1 bZng v?i OCR1A th chn OC1A
.<Xc xa xuRng mGc LOW (ti .ang ni tr<Qng hXp COM1A1=1,
COM1A0=0), TCNT1 ti>p tHc tKng .>n TOP, khi TCNT1=TOP th TCNT1
KHNG .<Xc t` .*ng reset v/ 0 nh< tr<Qng hXp Fast PWM m TCNT1 bMt
.Lu .>m ng<Xc, tGc gi2m t;ng gi trS t; TOP v/ 0. Trong lc TCNT1 gi2m,
.>n 1 lc n sc bZng gi trS câ OCR1A lLn thG 2, v lLn ny, chn OC1A
.<Xc set ln mGc HIGH, TCNT1 ti>p tHc gi2m .>n 0 th 1 chu kN hon t5t.
R rng 1 chu kN l qu trnh .>m trong 2 s<Qn nn ta g-i Phase correct
PWM l dual-slope. C7ng v tnh ch5t dual-slope m tn hiBu PWM trong
ch> .* ny c tnh .Ri xGng, thch hXp cho cc Gng dHng .i/u khi1n .*ng
c@. Hnh 13 m t2 cch m Phase correct PWM ho:t .*ng tron mode 10 v?i
ng ra .2o (COM1A1=1, COM1A0=0).

Hnh 13. Phase correct PWM mode 10.
ViBc vi>t code cho ch> .* Phase correct PWM gLn nh< t<@ng t` fast
PWM, b:n chU cLn thay .ei te hXp cc bit WGM dà theo b2ng 3 v sau .
nhp cc gi trS ph hXp cho ICR1 v ORC1A, OCR1B l .<Xc.
Ch> .* ny c 2 mode l 8 v 9. V/ hLu h>t cc ph<@ng diBn, 2 mode
ny giRng v?i 2 mode 10 v 11 câ Phase correct PWM. Ci khc nhau duy
nh5t l thQi .i1m m thanh ghi OCR1A v OCR1B .<Xc cAp nhAt d[ liBu
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n>u c s` thay .ei. ViBc ny, nhn chung khng 2nh h<Wng .>n hLu h>t
ng<Qi dng PWM .1 .i/u khi1n. B:n sc r5t kh .1 th5y s` khc biBt n>u b:n
khng ph2i .ang vi>t 1 Gng dHng m sai sR trong 1 micro giy l .i/u tB h:i.
V th> ti khng ./ cAp chi ti>t ch> .* ny, b:n .-c c th1 tham kh2o
datasheet câ chip .1 hi1u r h@n n>u cLn thi>t.
Ngoi ra trn chip atmega8 cn c b* timer2 8 bits c PWM v
asynchronous operation. V/ mDt chGc nKng timer2 giRng nh< phin b2n 8 bit
câ timer1 (.* phn gi2i th5p h@n nh<ng c cng ch> .* v ph<@ng thGc
ho:t .*ng). bi1m khc biBt v c7ng l .i1m .Dc biBt câ Timer2 l kh2 nKng
ho:t .*ng khng .Png b* v?i chip, n giRng nh< viBc b:n tch timer2 ra
thnh 1 chip timer ring, v th> cLn cung c5p 1 nguPn xung clock khc cho
timer ny (1 th:ch anh khc). Ch> .* ny c th1 .<Xc dng .1 calip
(calibrate), canh chUnh sai sR v b cho nguPn xung clock chnh trn chip.

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Bi 5 - Giao ti#p UART

I. Gi-i thi0u.
Bi ny gip cc b:n bi>t cch sC dHng cch truy/n thng nRi ti>p
UART trn AVR. Cng cH chnh c7ng l 2 b* phLn m/m quen thu*c
WinAVR v Proteus nh<ng trong bi ny (v cc bi sau n[a) chng ta sc sC
dHng chip Atmega32 lm chip minh h-a. V/ c@ b2n viBc thay .ei chip minh
h-a khng 2nh h<Wng l?n .>n tnh m:ch l:c câ lo:t bi v s` khc biBt câ
hai chip Atmega8 v Atmega32 l khng .ng k1. Tuy nhin, n>u c s`
khc biBt l?n W phLn no . ti sc k1 ra cho b:n tiBn so snh.
Sau bi ny, ti hy v-ng b:n c th1 hi1u v th`c hiBn .<Xc:
Nguyn l truy/n thng nRi ti>p .Png b* v khng .Png b*.
Module truy/n thng nRi ti>p USART trn AVR.
Truy/n thng .a xC l bZng UART.
II. TruyTn thng nIi tiQp khng =Vng bD.
ThuAt ng[ USART trong ti>ng anh l vi>t tMt câ cHm t;: Universal
Synchronous & Asynchronous serial Reveiver and Transmitter, ngh\a l b*
truy/n nhAn nRi ti>p .Png b* v khng .Png b*. CLn ch rZng khi niBm
USART (hay UART n>u chU ni .>n b* truy/n nhAn khng .Png b*) th<Qng
.1 chU thi>t bS phLn cGng (device, hardware), khng ph2i chU m*t chu]n giao
ti>p. USART hay UART cLn ph2i k>t hXp v?i m*t thi>t bS chuy1n .ei mGc
.iBn p .1 t:o ra m*t chu]n giao ti>p no .. V dH, chu]n RS232 (hay
COM) trn cc my tnh c nhn l s` k>t hXp câ chip UART v chip
chuy1n .ei mGc .iBn p. Tn hiBu t; chip UART th<Qng theo mGc TTL:
mGc logic high l 5, mGc low l 0V. Trong khi ., tn hiBu theo chu]n
RS232 trn my tnh c nhn th<Qng l -12V cho mGc logic high v +12 cho
mGc low (tham kh2o hnh 1). Ch l cc gi2i thch trong ti liBu ny theo
mGc logic TTL câ USART, khng theo RS232.
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Hnh 1. Tn hiBu t<@ng .<@ng câ UART v RS232.
TruyTn thng nIi tiQp: gi2 sC b:n .ang xy d`ng m*t Gng dHng phGc
t:p cLn sC dHng nhi/u vi .i/u khi1n (hoDc vi .i/u khi1n v my tnh) k>t nRi
v?i nhau. Trong qu trnh lm viBc cc vi .i/u khi1n cLn trao .ei d[ liBu cho
nhau, v dH tnh huRng Master truy/n lBnh cho Slaver hoDc Slaver gWi tn
hiBu thu thAp .<Xc v/ Master xC lGi2 sC d[ liBu cLn trao .ei l cc m c
chi/u di 8 bits, b:n c th1 sc ngh\ .>n cch k>t nRi .@n gi2n nh5t l k>t nRi
1 PORT (8 bit) câ mYi vi .i/u khi1n v?i nhau, mYi line trn PORT sc chSu
trch nhiBm truy/n/nhAn 1 bit d[ liBu. by g-i l cch giao ti>p song song,
cch ny l cch .@n gi2n nh5t v d[ liBu .<Xc xu5t v nhAn tr`c ti>p khng
thng qua b5t kN m*t gi2i thuAt bi>n .ei no v v th> tRc .* truy/n c7ng r5t
nhanh. Tuy nhin, nh< b:n th5y, nh<Xc .i1m câ cch truy/n ny l sR
.<Qng truy/n qu nhi/u, b:n hy t<Wng t<Xng n>u d[ liBu câ b:n c gi trS
cng l?n th sR .<Qng truy/n c7ng sc nhi/u thm. HB thRng truy/n thng
song song th<Qng r5t cPng k/nh v v th> km hiBu qu2. Truy/n thng nRi
ti>p sc gi2i quy>t vLn ./ ny, trong tuy/n thng nRi ti>p d[ liBu .<Xc truy/n
t;ng bit trn 1 (hoDc m*t t) .<Qng truy/n. V l do ny, cho d d[ liBu câ
b:n c l?n .>n .u b:n c7ng chU dng r5t t .<Qng truy/n. Hnh 2 m t2 s`
so snh gi[a 2 cch truy/n song song v nRi ti>p trong viBc truy/n con sR
187 thAp phn (tGc 10111011 nhS phn).
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Hnh 2. Truy/n 8 bit theo ph<@ng php song song v nRi ti>p.
M*t h:n ch> r5t dI nhAn th5y khi truy/n nRi ti>p so v?i song song l tRc
.* truy/n v .* chnh xc câ d[ liBu khi truy/n v nhAn. V d[ liBu cLn
.<Xc chia nh_ thnh t;ng bit khi truy/n/nhAn, tRc .* truy/n sc bS gi2m.
MDt khc, .1 .2m b2o tnh chnh xc câ d[ liBu, b* truy/n v b* nhAn cLn
c nh[ng th_a hiBp hay nh[ng tiu chu]n nh5t .Snh. PhLn ti>p theo trong
ch<@ng ny gi?i thiBu cc tiu chu]n trong truy/n thng nRi ti>p khng .Png
b*.
Khi niBm .Png b* .1 chU s` bo tr<?c trong qu trnh truy/n. L5y
v dH thi>t bS 1 (tb1) k>t v?i v?i thi>t bS 2 (tb2) bWi 2 .<Qng, m*t .<Qng d[
liBu v 1 .<Qng xung nhSp. CG mYi lLn tb1 muRn send 1 bit d[ liBu, tb1 .i/u
khi1n .<Qng xung nhSp chuy1n t; mGc th5p ln mGc cao bo cho tb2 sdn
sng nhAn m*t bit. BZng cch bo tr<?c ny t5t c2 cc bit d[ liBu c th1
truy/n/nhAn dI dng v?i t rî ro trong qu trnh truy/n. Tuy nhin, cch
truy/n ny .i h_i t nh5t 2 .<Qng truy/n cho 1 qu trnh (send or receive),
tRc .* truy/n c7ng bS h:n ch> v .i h_i bn nhAn ph2i lin tHc quan st
.<Qng xung nhSp tr<?c khi .-c b5t kN bit d[ liBu no. Giao ti>p gi[a my
tnh v cc bn phm (tr; bn phm k>t nRi theo chu]n USB) l m*t v dH
câ cch truy/n thng nRi ti>p .Png b*.
Khc v?i cch truy/n .Png b*, truy/n thng khng .Png b* chU cLn
m*t .<Qng truy/n cho m*t qu trnh. Khung d[ liBu . .<Xc chu]n ha
bWi cc thi>t bS nn khng cLn .<Qng xung nhSp bo tr<?c d[ liBu .>n. V dH
2 thi>t bS .ang giao ti>p v?i nhau theo ph<@ng php ny, chng . .<Xc th_a
thuAn v?i nhau rZng cG 1ms th sc c 1 bit d[ liBu truy/n .>n, nh< th> thi>t
bS nhAn chU cLn ki1m tra v .-c .<Qng truy/n mYi mili-giy .1 .-c cc bit
d[ liBu v sau . k>t hXp chng l:i thnh d[ liBu c ngh\a. Truy/n thng
nRi ti>p khng .Png b* v th> nhanh v hiBu qu2 h@n truy/n thng .Png b*.
Tuy nhin, .1 qu trnh truy/n thnh cng th viBc tun th^ cc tiu chu]n
truy/n l h>t sGc quan tr-ng. Chng ta sc bMt .Lu tm hi1u cc khi niBm
quan tr-ng trong ph<@ng php truy/n thng ny.
Baud rate (tIc =D Baud): nh< trong v dH trn v/ viBc truy/n 1 bit
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trong 1ms, b:n th5y rZng .1 viBc truy/n v nhAn khng .Png b* x2y ra thnh
cng th cc thi>t bS tham gia ph2i thRng nh5t nhau v/ kho2ng thQi dnh
cho 1 bit truy/n, hay ni cch khc tRc .* truy/n ph2i .<Xc ci .Dt nh< nhau
tr<?c, tRc .* ny g-i l tRc .* Baud. Theo .Snh ngh\a, tRc .* baud l sR bit
truy/n trong 1 giy. V dH n>u tRc .* baud .<Xc .Dt l 19200 th thQi gian
dnh cho 1 bit truy/n l 1/19200 ~ 52.083us.
Frame (khung truyTn): do truy/n thng nRi ti>p m nh5t l nRi ti>p
khng .Png b* r5t dI m5t hoDc sai lBch d[ liBu, qu trnh truy/n thng theo
ki1u ny ph2i tun theo m*t sR quy cch nh5t .Snh. Bn c:nh tRc .* baud,
khung truy/n l m*t y>u tRc quan tr-ng t:o nn s` thnh cng khi truy/n v
nhAn. Khung truy/n bao gPm cc quy .Snh v/ sR bit trong mYi lLn truy/n,
cc bit bo nh< bit Start v bit Stop, cc bit ki1m tra nh< Parity, ngoi ra
sR l<Xng cc bit trong m*t data c7ng .<Xc quy .Snh bWi khung truy/n. Hnh
1 l m*t v dH câ m*t khung truy/n theo UART, khung truy/n ny .<Xc bMt
.Lu bZng m*t start bit, ti>p theo l 8 bit data, sau . l 1 bit parity dng
ki1m tra d[ liBu v cuRi cng l 2 bits stop.
Start bit: start l bit .Lu tin .<Xc truy/n trong m*t frame truy/n, bit
ny c chGc nKng bo cho thi>t bS nhAn bi>t rZng c m*t gi d[ liBu sMp .<Xc
truy/n t?i. % module USART trong AVR, .<Qng truy/n lun W tr:ng thi
cao khi nghU (Idle), n>u m*t chip AVR muRn th`c hiBn viBc truy/n d[ liBu
n sc gWi m*t bit start bZng cch ko .<Qng truy/n xuRng mGc 0. Nh<
vAy, v?i AVR bit start l mang gi trS 0 v c gi trS .iBn p 0V (v?i chu]n
RS232 gi trS .iBn p câ bit start l ng<Xc l:i). start l bit bMt bu*c ph2i c
trong khung truy/n.
Data: data hay d[ liBu cLn truy/n l thng tin chnh m chng ta cLn gWi
v nhAn. Data khng nh5t thi>t ph2i l gi 8 bit, v?i AVR b:n c th1 quy
.Snh sR l<Xng bit câ data l 5, 6, 7, 8 hoDc 9 (t<@ng t` cho hLu h>t cc thi>t
bS hY trX UART khc). Trong truy/n thng nRi ti>p UART, bit c 2nh h<Wng
nh_ nh5t (LSB Least Significant Bit, bit bn ph2i) câ data sc .<Xc truy/n
tr<?c v cuRi cng l bit c 2nh h<Wng l?n nh5t (MSB Most Significant
Bit, bit bn tri).
Parity bit: parity l bit dng ki1m tra d[ liBu truy/n .ng khng (m*t
cch t<@ng .Ri). C 2 lo:i parity l parity chdn (even parity) v parity lf
(odd parity). Parity chdn ngh\a l sR l<Xng sR 1 trong d[ liBu bao gPm bit
parity lun l sR chdn. Ng<Xc l:i teng sR l<Xng cc sR 1 trong parity lf lun
l sR lf. V dH, n>u d[ liBu câ b:n l 10111011 nhS phn, c t5t c2 6 sR 1
trong d[ liBu ny, n>u parity chdn .<Xc dng, bit parity sc mang gi trS 0 .1
.2m b2o teng cc sR 1 l sR chdn (6 sR 1). N>u parity lf .<Xc yu cLu th gi
trS câ parity bit l 1. Hnh 1 m t2 v dH ny v?i parity chdn .<Xc sC dHng.
Parity bit khng ph2i l bit bMt bu*c v v th> chng ta c th1 lo:i bit ny
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kh_i khung truy/n (cc v dH trong bi ny ti khng dng bit parity).
Stop bits: stop bits l m*t hoDc cc bit bo cho thi>t bS nhAn rZng m*t
gi d[ liBu . .<Xc gWi xong. Sau khi nhAn .<Xc stop bits, thi>t bS nhAn sc
ti>n hnh ki1m tra khung truy/n .1 .2m b2o tnh chnh xc câ d[ liBu. Stop
bits l cc bits bMt bu*c xu5t hiBn trong khung truy/n, trong AVR USART
c th1 l 1 hoDc 2 bits (Trong cc thi>t bS khc Stop bits c th1 l 2.5 bits).
Trong v dH W hnh 1, c 2 stop bits .<Xc dng cho khung truy/n.Gi trS câ
stop bit lun l gi trS nghU (Idle) v l ng<Xc v?i gi trS câ start bit, gi trS
stop bit trong AVR lun l mGc cao (5V).
(Ch v gWi : khung truyTn phK biQn nhLt l : start bit+ 8 bit
data+1 stop bit)
Sau khi nMm bMt cc khi niBm v/ truy/n thng nRi ti>p, phLn ti>p theo
chng ta sc kh2o st cch th`c hiBn ph<@ng php truy/n thng ny trn chip
AVR (cH th1 l chip Atmega32).
III. TruyTn thng nIi tiQp khng =Vng bD v-i AVR (UART).
Vi .i/u khi1n Atmega32 c 1 module truy/n thng nRi ti>p USART. C
3 chn chnh lin quan .>n module ny . l chn xung nhSp - XCK (chn
sR 1), chn truy/n d[ liBu TxD (Transmitted Data) v chn nhAn d[ liBu
RxD (Reveived Data). Trong . chn XCK chU .<Xc sC dHng nh< l chn
pht hoDc nhAn xung gi[ nhSp trong ch> .* truy/n .*ng b*. Tuy nhin bi
ny chng ta khng kh2o st ch> .* truy/n thng .Png b*, v th> b:n chU cLn
quan tm .>n 2 chn TxD v RxD. V cc chn truy/n/nhAn d[ liBu chU .2m
nhiBm 1 chGc nKng .*c lAp (hoDc l truy/n, hoDc l nhAn), .1 k>t nRi cc
chip AVR v?i nhau (hoDc k>t nRi AVR v?i thi>t bS hY trX UART khc) b:n
ph2i .5u cho 2 chn ny. TxD câ thi>t bS thG nh5t k>t nRi v?i RxD câ
thi>t bS 2 v ng<Xc l:i. Module USART trn chip Atmega32 ho:t .*ng
song cng (Full Duplex Operation), ngh\a l qu trnh truy/n v nhAn d[
liBu c th1 x2y ra .Png thQi.
1. Thanh ghi:
C7ng nh< cc thi>t bS khc trn AVR, t5t c2 ho:t .*ng v trng thi câ
module USART .<Xc .i/u khi1n v quan st thng qua cc thanh ghi trong
vng nh? I/O. C 5 thanh ghi .<Xc thi>t k> ring cho ho:t .*ng v .i/u
khi1n câ USART, . l:
UDR: hay thanh ghi d[ liBu, l 1 thanh ghi 8 bit chGa gi trS nhAn
.<Xc v pht .i câ USART. Th`c ch5t thanh ghi ny c th1 coi nh< 2 thanh
ghi TXB (Transmit data Buffer) v RXB (Reveive data Buffer) c chung .Sa
chU. b-c UDR thu .<Xc gi trS thanh ghi .Bm d[ liBu nhAn, vi>t gi trS vo
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UDR t<@ng .<@ng .Dt gi trS vo thanh ghi .Bm pht, chu]n bS .1 gWi .i.
Ch trong cc khung truy/n sC dHng 5, 6 hoDc 7 bit d[ liBu, cc bit cao câ
thanh ghi UDR sc khng .<Xc sC dHng

UCSRA (USART Control and Status Register A): l 1 trong 3 thanh
ghi .i/u khi1n ho:t .*ng câ module USART.

Thanh ghi UCSRA ch^ y>u chGa cc bit tr:ng thi nh< bit bo qu trnh
nhAn k>t thc (RXC), truy/n k>t thc (TXC), bo thanh ghi d[ liBu trRng
(UDRE), khung truy/n c lYi (FE), d[ liBu trn (DOR), ki1m tra parity c lYi
(PE)B:n ch m*t sR bit quan tr-ng câ thanh ghi ny:
* UDRE (USART Data Register Empty) khi bit by bZng 1 ngh\a l thanh
ghi d[ liBu UDR .ang trRng v sdn sng cho m*t nhiBm vH truy/n hay nhAn
ti>p theo. V th> n>u b:n muRn truy/n d[ liBu .Lu tin b:n ph2i ki1m tra xem
bit UDRE c bZng 1 hay khng, sau khi chMc chMn rZng UDRE=1 hy vi>t
d[ liBu vo thanh ghi UDR .1 truy/n .i.
* U2X l bit chU .Snh g5p .i tRc .* truy/n, khi bit ny .<Xc set ln 1, tRc .*
truy/n so cao g5p 2 lLn so v?i khi bit ny mang gi trS 0.
* MPCM l bit ch-n ch> .* ho:t .*ng .a xC l (multi-processor).
UCSRB (USART Control and Status Register B): .y l thanh ghi
quan tr-ng .i/u khi1n USART. V th> chng ta sc kh2o st chi ti>t t;ng bit
câ thanh ghi ny.

* RXCIE (Receive Complete Interrupt Enable) l bit cho php ngMt khi qu
trnh nhAn k>t thc. ViBc nhAn d[ liBu truy/n bZng ph<@ng php nRi ti>p
khng .Png b* th<Qng .<Xc th`c hiBn thng qua ngMt, v th> bit ny th<Qng
.<Xc set bZng 1 khi USART .<Xc dung nhAn d[ liBu.
* TXCIE (Transmit Complete Interrupt Enable) bit cho php ngMt khi qu
trnh truy/n k>t thc.
Ntinside 70
* UDRIE (USART Data Register Empty Interrupt Enable) l bit cho php
ngMt khi thanh ghi d[ liBu UDR trRng.
* RXEN (Receiver Enable) l m*t bit quan tr-ng .i/u khi1n b* nhAn câ
USART, ./ kch ho:t chGc nKng nhAn d[ liBu b:n ph2i set bit ny ln 1.
* TXEN (Transmitter Enable) l bit .i/u khi1n b* pht. Set bit ny ln 1 b:n
sc khWi .*ng b* pht câ USART.
* UCSZ2 (Chracter size) bit ny k>t hXp v?i 2 bit khc trong thanh ghi
UCSRC quy .Snh .* di câ d[ liBu truy/n/nhAn. Chng ta sc kh2o st chi
ti>t khi tm hi1u thanh ghi UCSRC.
* RXB8 (Receive Data Bit 8) g-i l bit d[ liBu 8. B:n nh? l:i rZng USART
trong AVR c hY trX truy/n d[ liBu c .* di tRi .a 9 bit, trong khi thanh ghi
d[ liBu l thanh ghi 8 bit. Do ., khi c gi d[ liBu 9 bit .<Xc nhAn, 8 bit .Lu
sc chGa trong thanh ghi UDR, cLn c 1 bit khc .ng vai tr bit thG chn,
RXD8 l bit thG chn ny. B:n ch l cc bit .<Xc .nh sR t; 0, v th> bit
thG chn sc c chU sR l 8, v lc . m bit ny c tn l RXD8 (khng ph2i
RXD9).
* TXB8 (Transmit Data Bit 8), t<@ng t` nh< bit RXD8, bit TXB8 c7ng .ng
vai tr bit thG 9 truy/n thng, nh<ng bit ny .<Xc dung trong lc truy/n d[
liBu.
UCSRC (USART Control and Status Register C): thanh ghi ny ch^
y>u quy .Snh khung truy/n v ch> .* truy/n. Tuy nhin, c m*t rMc rRi nho
nh_ l thanh ghi ny l:i c cng .Sa chU v?i thanh ghi UBRRH (thanh ghi
chGa byte cao dng .1 xc lAp tRc .* baud), ni m*t cch khc 2 thanh ghi
ny l 1. V th> bit 7 trong thanh ghi ny, tGc bit URSEL l bit ch-n thanh
ghi. Khi URSEL=1, thanh ghi ny .<Xc chip AVR hi1u l thanh ghi .i/u
khi1n UCSRC, nh<ng n>u bit URSEL=0 th thanh ghi UBRRH sc .<Xc sC
dHng.

Cc bit cn l:i trong thanh ghi UCSRC .<Xc m t2 nh< sau:
* UMSEL (USART Mode Select) l bit là ch-n gi[a 2 ch> .* truy/n thng
.Png b* v khng .Png b*. N>u UMSEL=0, ch> .* khng .Png b* .<Xc
ch-n, ng<Xc l:i n>u UMSEL=1, ch> .* .Png b* .<Xc kch ho:t.
* Hai bit UPM1 v UPM0( Parity Mode) .<Xc dng .1 quy .Snh ki1m tra
pariry. N>u UPM1:0=00, parity khng .<Xc sC dHng (mode ny kh thng
Ntinside 71
dHng), UPM1:0=01 khng .<Xc sC dHng, UPM1:0=10 th parity chdn .<Xc
dng, UPM1:0=11 parity lf .<Xc sC dHng (xem thm b2ng 1).
B2ng 1: ch-n ki1m tra parity.

* USBS (Stop bit Select), bit Stop trong khung truy/n bZng AVR USART c
th1 l 1 hoDc 2 bit, n>u USBS=0 th Stop bit chU l 1 bit trong khi USBS=1
sc c 2 Stop bit .<Xc dng.
* Hai bit UCSZ1 v UCSZ2 (Character Size) k>t hXp v?i bit UCSZ2 trong
thanh ghi UCSRB t:o thnh 3 bit quy .Snh .* di d[ liBu truy/n. B2ng 2 tm
tMt cc gi trS c th1 c câ te hXp 3 bit ny v .* di d[ liBu truy/n t<@ng
Gng.
B2ng 2: .* di d[ liBu truy/n.

* UCPOL (Clock Pority) l bit chU c`c câ xung kch trong ch> .* truy/n
thng .Png b*. n>u UCPOL=0, d[ liBu sc thay .ei thay .ei W c:nh ln câ
xung nhSp, n>u UCPOL=1, d[ liBu thay .ei W c:nh xuRng xung nhSp. N>u
b:n sC dHng ch> .* truy/n thng khng .Png b*, hy set bit ny bZng 0..
UBRRL v UBRRH (USART Baud Rate Register): 2 thanh ghi th5p
v cao quy .Snh tRc .* baud.

NhMc l:i l thanh ghi UBRRH dng chung .Sa chU thanh ghi UCSRC,
b:n ph2i set bit ny bZng 0 n>u muRn sC dHng thanh ghi UBRRH. Nh< b:n
Ntinside 72
quan st trong hnh trn, chU c 4 bit th5p câ UBRRH .<Xc dng, 4 bit ny
k>t hXp v?i 8 bit trong thanh ghi UBRRL t:o thnh thanh ghi 12 bit quy .Snh
tRc .* baud. Ch l n>u b:n vi>t gi trS vo thanh ghi UBRRL, tRc .* baud
sc tGc th .<Xc cAp nhAt, v th> b:n ph2i vi>t gi trS vo thanh ghi UBRRH
tr<?c khi vi>t vo thanh ghi UBRRL.
Gi trS gn cho thanh ghi UBRR khng ph2i l tRc .* baud, n chU .<Xc
USART dng .1 tnh tRc .* baud. B2ng 3 h<?ng dan cch tnh tRc .* baud
dà vo gi trS câ thanh ghi UBRR v ng<Xc l:i, cch tnh gi trS cLn thi>t
gn cho thanh ghi UBRR khi . bi>t tRc .* baud.
B2ng 3: tnh tRc .* baud.

Trong cc cng thGc trong b2ng 3, fOSC l tRc tLn sR xung nhSp câ hB
thRng (th:ch anh hay nguPn xung n*i). b1 tiBn cho b:n theo di, ti .nh
km b2ng v dH cch .Dt gi trS cho UBRR theo tRc .* baud mau.
B2ng 4: m*t sR tRc .* baud mau.

Ntinside 73

Ntinside 74

2. SU d5ng UART:.
Thng th<Qng, .1 sC dHng module USART trn AVR b:n ph2i th`c
hiBn 3 viBc quan tr-ng, . l: ci .Dt tRc .* baud (thanh ghi UBRR), .Snh
d:ng khung truy/n (UCSRB, UCSRC) v cuRi cng kch ho:t b* truy/n, b*
nhAn, ngMtNh< . ./ cAp, trong ti liBu ny ti ch^ y>u ./ cAp .>n ph<@ng
php truy/n thng khng .Png b*, viBc xc lAp cc thng sR ho:t .*ng ch^
y>u dà trn ch> .* ny. Trong hLu h>t cc Gng dHng, tRc .* baud v khung
truy/n th<Qng khng .ei, trong tr<Qng hXp ny chng ta c th1 khWi t:o tr`c
ti>p USART W phLn .Lu trong main v sau . chU cLn truy/n hoDc nhAn d[
liBu m khng cLn thay .ei cc ci .Dt. Tuy nhin, n>u tr<Qng hXp giao ti>p
linh ho:t v dH b:n .ang ch> t:o m*t thi>t bS c kh2 nKng giao ti>p v?i m*t
thi>t bS .Lu cuRi khc (nh< my tnh chFng h:n), lc ny b:n nn cho php
ng<Qi dng thay .ei tRc .* baud hoDc cc thng sR khc .1 ph hXp v?i thi>t
bS .Lu cuRi. bRi v?i nh[ng Gng dHng ki1u ny b:n nn vi>t 1 ch<@ng trnh
con .1 khWi .*ng USART v c th1 g-i l:i nhi/u lLn khi cLn thay .ei. PhLn
ti>p theo chng ta sc vi>t m*t sR ch<@ng trnh v dH minh h-a cch sC dHng
module truy/n thng USART t; .@n gi2n .>n phGc t:p. Cc v dH sc .<Xc
th`c hiBn cho chip Atmega32 v?i gi2 sC nguPn xung nhSp hB thRng l 8MHz.
2.1 Truy7n d8 li/u.
Tr<?c h>t chng ta sc th`c hiBn m*t v dH r5t .@n gi2n .1 hi1u cch khWi
.*ng USART v truy/n cc gi d[ liBu 8 bit. M:ch .iBn m ph_ng trong
hnh 3. Gi2 sC chng ta muRn .Snh d:ng cho khung truy/n gPm 1 bit start, 8
Ntinside 75
bit d[ liBu, khng ki1m tra parity v 1 bit stop. TRc .* baud 57600 (57.6k).
D[ liBu cLn truy/n l cc gi trS lin tHc câ b2ng m ASCII. bo:n code
trong list 1 trnh by cch th`c hiBn v dH ny.
List 1. KhWi .*ng v truy/n d[ liBu khng .Png b* bZng USART

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#include <avr/io.h>
#include <avr/delay.h>

//chuong trinh con phat du lieu
void uart_char_tx(unsigned char chr){
while (bit_is_clear(UCSRA,UDRE)) {}; //cho den khi bit UDRE=1
UDR=chr;
}

int main(void){
//set baud, 57.6k ung voi f=8Mhz, xem bang 70 trang 165, Atmega32 datasheet
UBRRH=0;
UBRRL=8;

//set khung truyen va kich hoat bo nhan du lieu
UCSRA=0x00;
UCSRC=(1<<URSEL)|(1<<UCSZ1)|(1<<UCSZ0);
UCSRB=(1<<TXEN);

while(1){
for (char i=32; i<128; i++){
uart_char_tx(i); //phat du lieu
_delay_ms(100);
}
}
}
Tr<?c h>t ti sc gi2i thch cch khWi .*ng USART trong cc dng code
t; 12 .>n 18. N>u b:n xem l:i b2ng 3 trong trang 9 câ ti liBu ny (hoDc
b2ng 70, trang 165 datasheet câ chip atmega32), Gng v?i tLn sR xung nhSp
8Hhz, khng sC dHng ch> .* nhn .i tRc .* (U2X=0), .1 .:t .<Xc tRc b*
baud 57600 th gi trS cLn gn cho thanh ghi UBRR l 8 (xem c*t 2, b2ng 3).
Hai dng 12 v 13 trong list 1 th`c hiBn gn 8 cho thanh ghi UBRR thng
qua 2 thanh ghi UBRRH v UBRRL. Trong dng 16, thanh ghi UCSRA
.<Xc gn bZng 0. N>u b:n xem l:i phLn gi2i thch b:n sc th5y thanh ghi
Ntinside 76
UCSRA ch^ y>u chGa cc bit tr:ng thi, ring 2 bit U2X v MPCM l 2 bit
.i/u khi1n, 2 bit ny bZng 0 ngh\a l chng ta khng sC dHng ch> .* nhn
.i tRc .* v khng sC dHng truy/n thng .a xC l. PhLn quan tr-ng nh5t
chnh l .Dt gi trS cho 2 thanh ghi USCRB v UCSRC. V?i thanh ghi
UCSRC (dng 17) tr<?c h>t chng ta ph2i set bit URSEL .1 bo rZng chng
ta khng muRn truy cAp thanh ghi UBRRH m l thanh ghi UCSRC (2 thanh
ghi ny c cng .Sa chU), ti>p theo chng ta chU set 1 cho 2 bit UCSZ1 v
UCSZ0, b:n xem l:i b2ng 2 .1 th5y rZng n>u UCSZ1=1, UCSZ0=1 cng v?i
viBc bit UCSZ2=0(nZm trong thanh ghi UCSRB) th .* di d[ liBu truy/n
.<Xc ch-n l 8 bit. Cc bit trong thanh ghi UCSRC khng .<Xc set sc mDc
.Snh mang gi trS 0, bao gPm UMSEL = 0 (ch> .* truy/n thng khng .Png
b*), UPM1:0=00 ( khng sC dHng ki1m tra parity, xem b2ng 1), USBS=0 (1
bit stop) v UCPOL=0 (bit ny khng sC dHng khi truy/n khng .Png b*).
Sau cng, trong dng 18, chng ta chU set bit TXEN =1 ngh\a l chU kch
ho:t b* pht d[ liBu, cc thnh phLn khc nh< b* nhAn, cc ngMtkhng
.<Xc sC dHng trong v dH ny.
Trong cc bi tr<?c ti . gi?i thiBu b:n v/ trnh phHc vH ngMt v trong
phLn ny ti sc trnh by cch vi>t m*t ch<@ng trnh con bZng ngn ng[ C
trong WinAVR, . l .o:n ch<@ng trnh uart_char_tx W dng 5. Ch<@ng
trnh con l 1 .o:n code bao gPm cc cu lBnh cng th`c hiBn m*t nhiBm vH
chung cH th1 no .. Trong tr<Qng hXp ny l nhiBm vH truy/n 1 tham sR 8
bit ra .<Qng TxD câ USART thng qua thanh ghi UDR. Nh< trnh by
trong phLn m t2 bit UDRE câ thanh ghi UCSRA, qu trnh truy/n chU
.<Xc bMt .Lu khi bit UDRE bZng 1, v th> dng code 6 lm nhiBm vH ki1m
tra bit UDRE, cu lBnh while(bit_is_clear(UCSRA,UDRE)) {}; .<Xc hi1u
l qu trnh lDp sc l]n qu]n n>u bit UDRE bZng 0 (bit_is_clear). Khi bit
UDRE bZng 1 th dng code 7 sc xu5t bi>n chr ra thanh ghi UDR c7ng l
xu5t ra chn TxD câ module USART. Trong ngn ng[ C c 2 cch c@ b2n
.1 vi>t ch<@ng trnh con. V?i cch 1 ch<@ng trnh con .<Xc khai bo v vi>t
tr`c ti>p pha tr<?c ch<@ng trnh chnh main nh< cch m ti th`c hiBn trong
v dH 1 ny. Cch vi>t ny .I hi1u v thch hXp cho cc .o:n ch<@ng trnh
con ngMn nh<ng chng c th1 lm teng quan ch<@ng trnh câ b:n trW nn
rMc rRi khi c qu nhi1u ch<@ng trnh con vi>t tr<?c main. B:n c th1 khMc
phHc nh<Xc .i1m ny bZng cch .Dt cc ch<@ng trnh con pha sau main nh<
cch m chng ta . lm v?i cc trnh phHc vH ngMt. N>u theo .ng quy
cch câ ngn ng[ C, khi .Dt ch<@ng trnh con sau main b:n ph2i khai bo
tn ch<@ng trnh pha tr<?c main, n>u b:n .Dt ch<@ng trnh con uart_char_tx
pha sau main th phLn tr<?c main b:n sc .Dt dng khai bo
tr<?c: void uart_char_tx(unsigned char chr);. Tuy WinAVR cho php b:n
Ntinside 77
b_ qua khai bo tr<?c ny nh<ng ti khuyn b:n nn vi>t .ng cch .1 t:o
thi quen v c7ng nh< .1 dI chuy1n ch<@ng trnh sang cc trnh bin dSch C
khc sau ny n>u cLn thi>t. PhLn cuRi cng trong .o:n code l g-i l:i
ch<@ng trnh uart_char_tx .1 truy/n cc d[ liBu l cc sR t; 32 .>n 127.
b1 th`c hiBn m ph_ng bZng proteus b:n hy vc m*t m:ch .iBn .@n
gi2n nh< trong hnh 3. Chip Atmega32 c th1 .<Xc tm v?i t; kha mega32.
Trong m:ch .iBn m ph_ng c m*t thi>t bS .Lu cuRi 2o (Virtual Terminal) l
m*t thi>t bS k>t nRi v hi1n thS k>t qu2 truy/n thng khng .Png b*, chng
ta dng .1 ki1m tra d[ liBu .<Xc truy/n bZng chip AVR. B:n c th1 tm thi>t
bS ny trong trong danh sch cc dH cH 2o (virtual instruments), nh5n vo nt
cng cH v sau . ch-n terminal trong danh sch .1 ch-n thi>t bS .Lu cuRi
2o. K>t nRi thi>t bS 2o v?i chip Atmega32 nh< trong hnh 3, ch l ph2i
.5u cho 2 chn TxD v RxD. Bn c:nh viBc gn ch<@ng trnh cho chip
AVR, b:n ph2i set thng sR cho thi>t bS 2o tr<?c khi th`c hiBn m ph_ng.
Hy mW h*p tho:i edit component câ thi>t bS 2o (bZng cch right click rPi
left click trn thi>t bS 2o). Theo mDc .Snh thi>t bS .Lu cuRi .<Xc .Snh d:ng
khung truy/n l 1 bit start+8 bit d[ liBu+1 bit stop t<@ng t` nh< cch chng
ta ci .Dt cho AVR trong v dH 1, v th> b:n chU cLn thay .ei tRc .* baud
thnh 57600 trong h*p tho:i edit component l hon t5t (xem hnh 4). Khi
ch:y m ph_ng, thi>t bS .Lu cuRi 2o sc hi1n thS cc k t` ASCII câ cc sR
t; 32 .>n 127.

Ntinside 78
Hnh 3. M ph_ng v dH 1.

Hnh 4. Ci .Dt thng sR cho thi>t bS 2o.
2.2 Nh:n d8 li/u.
Qu trnh nhAn d[ liBu chU x2y ra khi bit RXEN trong thanh ghi UCSRB
.<Xc set bZng 1 v t5t nhin chn nhAn d[ liBu RxD ph2i .<Xc nRi v?i m*t
nguPn pht (chn TxD câ m*t chip UART khc chFng h:n). Cc thng sR
truy/n thng nh< tRc .* baud v khung truy/n trong b* nhAn ph2i .<Xc ci
.Dt nh< câ b* pht. N>u khng c lYi trong qu trnh truy/n v nhAn d[
liBu, sau khi nhAn d[ liBu sc .<Xc chGa trong thanh ghi UDR v bit RXC
(Reveice Complete) trong thanh ghi UCSRA sc t` .*ng .<Xc set ln 1. Sau
khi thanh ghi UDR .<Xc .-c, bit RXC l:i t` .*ng reset v/ 0 .1 chu]n bS cho
qu trnh nhAn d[ liBu k> ti>p. Nh< th> v/ c@ b2n chng ta c 2 cch .-c d[
liBu nhAn v/. Cch thG nh5t l cch h_i vng (polling), ki1m tra n>u bit
RXC = 1 th .-c gi trS thanh ghi UDR (v .-c c2 bit RXB8 trong thanh ghi
UCSRB n>u frame truy/n 9 bit .<Xc dng). Cch thG hai l sC dHng ngMt
nhAn hon t5t (Receive Complete Interrupt), bZng cch set bit cho php
ngMt nhAn hon t5t, tGc bit RXCIE trong thanh ghi UCSRB, v bit cho php
ngMt ton cHc (bit I, xem l:i bi 3) th m*t ngMt sc x2y ra khi d[ liBu . .<Xc
nhAn v chGa trong thanh ghi UDR, chng ta chU cLn .-c gi trS câ thanh
ghi UDR trong trnh phHc vH ngMt l xong. Theo kinh nghiBm, sC dHng ngMt
l ph<@ng php tRt nh5t cho .a sR cc tr<Qng hXp nhAn d[ liBu UART, v
chng ta khng cLn quan tm thQi .i1m m d[ liBu gWi .>n, trnh lng ph
thQi gian dnh cho viBc h_i vng. V th> trong phLn ti>p theo ti sc trnh
Ntinside 79
by m*t v dH minh h-a qu trnh nhAn d[ liBu bZng ph<@ng php ngMt. b1
phHc vH cho v dH ny, chng ta sc kh2o st m*t m:ch m ph_ng gPm 2 chip
Atmega32 nRi v?i nhau qua cc .<Qng TxD v RxD. Chip thG l chip pht
d[ liBu, nhiBm vH câ chip ny l pht chuYi d[ liBu t; 32 .>n 127 nh< chip
Atmega32 trong v dH 1. Chn pht TxD câ chip 1 sc .<Xc nRi v?i chn
nhAn RxD câ chip thG 2 (chip thG 2 .<Xc g-i l chip nhAn d[ liBu). Chip
thG 2 sau khi nhAn d[ liBu sc pht d[ liBu ny ra chn TxD câ chnh n .1
c th1 hi1n thS ln thi>t bS .Lu cuRi 2o cho chng qua quan st v so snh k>t
qu2. B:n xem m:ch .iBn m ph_ng trong hnh 5 .1 hi1u r h@n. Chng ta sC
dHng .o:n code trong v dH 1 cho chip thG nh5t v th> chU cLn vi>t .o:n code
nhAn v pht l:i d[ liBu cho chip thG hai. List 2 trnh by .o:n code cho chip
thG hai..
List 2. NhAn d[ liBu USART khng .Png b* bZng ph<@ng php ngMt.

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#include <avr/io.h>
//chuong trinh con phat du lieu
void uart_char_tx(unsigned char chr){
while (bit_is_clear(UCSRA,UDRE)) {}; //cho den khi bit UDRE=1
UDR=chr;
}
volatile unsigned char u_Data;

int main(void){
//set baud, 57.6k ung voi f=8Mhz, xem bang 70 trang 165, Atmega32 datasheet
UBRRH=0;
UBRRL=8;
//set khung truyen va kich hoat bo nhan du lieu
UCSRA=0x00;
UCSRC=(1<<URSEL)|(1<<UCSZ1)|(1<<UCSZ0);
UCSRB=(1<<RXEN)|(1<<TXEN)|(1<<RXCIE);//cho phep ca 2 qua trinh nhan va//truyen, va cho
phep ngat sau khi nhan xong
sei(); //cho phep ngat toan cuc

while(1){
}
}
ISR(SIG_UART_RECV){ //trinh phuc vu ngat USART hoan tat nhan
u_Data=UDR;
Ntinside 80
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uart_char_tx(u_Data);
}
bo:n code trong v dH nhAn v pht d[ liBu khng khc .o:n code trong v dH 1 l m5y. % dng thG 3 ti
include file header interrupt.h v chng ta sc sC dHng ngMt .1 nhAn d[ liBu. Chng ta khai bo m*t bi>n u_Data
d:ng 8 bit khng d5u .1 ln ny sc .<Xc truy cAp trong trnh phHc vH ngMt nn chng
ta .Dt attribute volatile (dng 9). bi1m quan tr-ng khi khWi .*ng UART trong v dH ny l dng code 18, n>u
trong v dH 1 chng ta chU khWi .*ng duy nh5t b* pht bZng cch set bit TXEN trong thanh ghi UCSRB
(UCSRB=(1<<TXEN);) th trong v dH ny chng ta set thm 2 bit cho php nhAn RXEN v cho php ngMt
RXCIE trong thanh ghi UCSRB. Bit RXEN khWi .*ng b* nhAn v bit RXCIE khWi .*ng ch> .* ngMt khi d[ liBu
. nhAn trong UDR, tuy nhin .1 c th1 sC dHng ngMt, chng ta cLn set them bit I trong thanh ghi tr:ng thi bZng
dng code 20 (sei();). PhLn quan tr-ng nh5t trong .o:n code trn l trnh phHc ngMt nhAn d[ liBu ISR. Khi d[ liBu
. .<Xc nhAn .Ly trong UDR, trnh ngMt ISR(SIG_UART_RECV) sc .<Xc th`c hiBn, chng ta sc .-c gi trS v;a
nhAn .<Xc vo bi>n u_Data (dng 26) v sau . pht gi trS ny ra chn TxD .1 hi1n thS ln thi>t bS .Lu cuRi 2o
bZng dng lBnh 27.
PhLn m:ch .iBn m ph_ng .<Xc trnh by trong hnh 5. Ch<@ng trnh cho chip TRANSMITTER l
ch<@ng trnh trong v dH 1 v ch<@ng trnh cho chip RECEIVER l ch<@ng trnh trong .o:n code trn. B:n ph2i
set xung clock cho c2 2 chip l 8MHz v set tRc .* baud cho thi>t bS .Lu cuRi 2o l 56700. N>u khi ch:y m
ph_ng, thi>t bS .Lu cuRi hi1n thS cc k t` ASCII câ cc sR t; 32 .>n 127 nh< trong hnh 5 th m-i thG . .<Xc
th`c hiBn chnh xc.

Hnh 5. Truy/n v nhAn bZng UART.

Ntinside 81
Bi 6 - Chuy%n &'i ADC

I. B3n sE =i =Qn =u.
Bi h-c ny, nh< tn câ n, sc gi?i thiBu cch sC dHng b* chuy1n .ei
t<@ng t` - sR (analog to digital converter - ADC). Cng cH chnh c7ng l 2
b* phLn m/m quen thu*c WinAVR v Proteus.
- Nguyn l chuy1n .ei AD.
- Chuy1n .ei ADC .@n knh trn AVR.
- SC dHng chuy1n .ei ADC .@n knh trn AVR, hi1n thS sR 4 digit bZng
LED 7 .o:n.
II. ChuyGn =Ki dP li0u t9.ng tX (analog) sang dP li0u sI (digital).
Trong cc Gng dHng .o l<Qng v .i/u khi1n bZng vi .i/u khi1n b*
chuy1n .ei t<@ng t`-sR (ADC) l m*t thnh phLn r5t quan tr-ng. D[ liBu
trong th> gi?i câ chng ta l cc d[ liBu t<@ng t` (analog). V dH nhiBt .*
khng kh buei sng l 25oC v buei tr<a l 32oC, gi[a hai mGc gi trS ny
c v sR cc gi trS lin tHc m nhiBt .* ph2i .i qua .1 c th1 .:t mGc
32oC t; 25oC, .:i l<Xng nhiBt .* nh< th> g-i l m*t .:i l<Xng analog.
Trong khi ., r rng vi .i/u khi1n l m*t thi>t bS sR (digital), cc gi trS m
m*t vi .i/u khi1n c th1 thao tc l cc con sR rQi r:c v th`c ch5t chng
.<Xc t:o thnh t; s` k>t hXp câ hai mGc 0 v 1. V dH chng ta muRn dng
m*t thanh ghi 8 bit trong vi .i/u khi1n .1 ln 255 oC, nh< chng ta . bi>t, m*t thanh ghi 8 bit c th1 chGa tRi .a 256
(2
8
) gi trS nguyn t; 0 .>n 255, nh< th> cc mGc nhiBt .* khng nguyn
nh< 28.123 oC sc khng .<Xc ghi l:i. Ni cch khc, chng ta . sR ha
(digitalize) m*t d[ liBu analog thnh m*t d[ liBu digital. Qu trnh sR ha
ny th<Qng .<Xc th`c hiBn bWi m*t thi>t bS g-i l b* chuy1n .ei t<@ng t` -
sR hay .@n gi2n l ADC (Analog to Digital Converter).
C r5t nhi/u ph<@ng php chuy1n .ei ADC, ti khng c .Snh gi2i
thch cH th1 cc nguyn l chuy1n .ei ny trong bi h-c v/ AVR, tuy nhin
ti sc gi?i thiBu m*t cch chuy1n .ei r5t c@ b2n v phe bi>n .1 cc b:n phLn
no nMm .<Xc cch m m*t b* ADC lm viBc. Ph<@ng php chuy1n .ei m
ti ni l ph<@ng php chuy1n .ei tr`c ti>p (direct converting) hoDc flash
ADC. Cc b* chuy1n .ei ADC theo ph<@ng php ny .<Xc c5u thnh t;
m*t dy cc b* so snh (nh< opamp), cc b* so snh .<Xc mMc song song
v .<Xc k>t nRi tr`c ti>p v?i tn hiBu analog cLn chuy1n .ei. M*t .iBn p
tham chi>u (reference) v m*t m:ch chia p .<Xc sC dHng .1 t:o ra cc mGc
Ntinside 82
.iBn p so snh khc nhau cho mYi b* so snh. Hnh 1 m t2 m*t b* chuy1n
.ei flash ADC c 4 b* so snh, Vin l tn hiBu analog cLn chuy1n .ei v gi
trS sau chuy1n .ei l cc con sR t:o thnh t; s` k>t hXp cc mGc nhS phn
trn cc chn Vo. Trong hnh 1, b:n th5y rZng do anh h<Wng câ m:ch chia
p (cc .iBn trW mMc nRi ti>p t; .iBn p +15V .>n ground), .iBn p trn chn
m (chn -) câ cc b* so snh sc khc nhau. Trong lc chuy1n .ei, gi2 sC
.iBn p Vin l?n h@n .iBn p V- câ b* so snh 1 (opamp W pha th5p nh5t
trong m:ch) nh<ng l:i nh_ h@n .iBn p V- câ cc b* so snh khc, khi .
ng Vo1 W mGc 1 v cc ng Vo khc W mGc 0, chng ta thu .<Xc m*t k>t
qu2 sR. M*t cch t<@ng t`, n>u tKng .iBn p Vin ta thu .<Xc cc te hXp sR
khc nhau. V?i m:ch .iBn c 4 b* so snh nh< trong hnh 1, sc c t5t c2 5
tr<Qng hXp c th1 x2y ra, hay ni theo cch khc .iBn p analog Vin .<Xc
chia thnh 5 mGc sR khc nhau. Tuy nhin, b:n ch l cc ng Vo khng
ph2i l cc bit câ tn hiBu sR ng ra, chng chU l .:i diBn .1 te hXp thnh
tn hiBu sR ng ra, dI hi1u h@n chng ta khng sC dHng .<Xc cc bit Vo tr`c
ti>p m cLn m*t b* gi2i m (decoder). Trong b2ng 1 ti trnh by k>t qu2 sau
khi gi2i m Gng v?i cc te hXp câ cc ng Vo.

Hnh 1. M:ch flash ADC v?i 4 b* so snh.
B2ng 1 Gi trS sR ng ra sau khi gi2i m.
Ntinside 83

(D phn gi@i (resolution): nh< trong v dH trn, n>u m:ch .iBn c 4 b*
so snh, ng ra digital sc c 5 mGc gi trS. T<@ng t` n>u m:ch .iBn c 7 b*
so snh th sc c 8 mGc gi trS c th1 W ng ra digital, kho2ng cch gi[a cc
mGc tn hiBu trong tr<Qng hXp 8 mGc sc nh_ h@n tr<Qng hXp 4 mGc. Ni
cch khc, m:ch chuy1n .ei v?i 7 b* so snh c gi trS digital ng ra mSn
h@n khi chU c 4 b*, .* mSn cng cao tGc .* phn gi2i (resolution) cng
l?n. Khi niBm .* phn gi2i .<Xc dng .1 chU sR bit cLn thi>t .1 chGa h>t
cc mGc gi trS digital ng ra. Trong tr<Qng hXp c 8 mGc gi trS ng ra,
chng ta cLn 3 bit nhS phn .1 m ha h>t cc gi trS ny, v th> m:ch chuy1n
.ei ADC v?i 7 b* so snh sc c .* phn gi2i l 3 bit. M*t cch teng qut,
n>u m*t m:ch chuy1n .ei ADC c .* phn gi2i n bit th sc c 2
n
mGc gi trS
c th1 c W ng ra digital. b1 t:o ra m*t m:ch chuy1n .ei flash ADC c .*
phn gi2i n bit, chng ta cLn .>n 2
n
-1 b* so snh, gi trS ny r5t l?n khi thi>t
k> b* chuy1n .ei ADC c .* phn gi2i cao, v th> cc b* chuy1n .ei flash
ADC th<Qng c .* phn gi2i t h@n 8 bit. b* phn gi2i lin quan mAt thi>t
.>n ch5t l<Xng chuy1n .ei ADC, viBc là ch-n .* phn gi2i ph2i ph hXp
v?i .* chnh xc yu cLu v kh2 nKng xC l câ b .i/u khi1n. Trong 2 m
t2 m*t v dH sR ha m*t hm sin analog thnh d:ng digital.

Hnh 2. Analog v digital câ hm sin.
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(i0n p tham chiQu (reference voltage): Cng m*t b* chuy1n .ei ADC
nh<ng c ng<Qi muRn dng cho cc mGc .iBn p khc nhau, v dH ng<Qi A
muRn chuy1n .ei .iBn p trong kho2ng 0-1V trong khi ng<Qi B muRn dng
cho .iBn p t; 0V .>n 5V. R rng n>u hai ng<Qi ny dng 2 b* chuy1n .ei
ADC ./u c kh2 nKng chuy1n .ei .>n .iBn p 5V th ng<Qi A .ang ph
ph:m tnh chnh xc câ thi>t bS. V5n ./ sc .<Xc gi2i quy>t bZng m*t .:i
l<Xng g-i l .iBn p tham chi>u - Vref (reference voltage). biBn p tham
chi>u th<Qng l gi trS .iBn p l?n nh5t m b* ADC c th1 chuy1n .ei.
Trong cc b* ADC, Vref th<Qng l thng sR .<Xc .Dt bWi ng<Qi dng, n l
.iBn p l?n nh5t m thi>t bS c th1 chuy1n .ei. V dH, m*t b* ADC 10 bit
(.* phn gi2i) c Vref=3V, n>u .iBn p W ng vo l 1V th gi trS sR thu
.<Xc sau khi chuy1n .ei sc l: 1023x(1/3)=314. Trong . 1023 l gi trS l?n
nh5t m m*t b* ADC 10 bit c th1 t:o ra (1023=2
10
-1). V .iBn p tham
chi>u 2nh h<Wng .>n .* chnh xc câ qu trnh chuy1n .ei, chng ta cLn
tnh ton .1 ch-n 1 .iBn p tham chi>u ph hXp, khng .<Xc nh_ h@n gi trS
l?n nh5t câ input nh<ng c7ng .;ng qu l?n.
II. ChuyGn =Ki ADC trn AVR.
Chip AVR ATmega32 câ Atmel c tch hXp sdn cc b* chuy1n .ei
ADC v?i .* phn gi2i 10 bit. C t5t c2 8 knh .@n (cc chn ADC0 .>n
ADC7), 16 te hXp chuy1n .ei d:ng so snh, trong . c 2 knh so snh c
th1 khuy>ch .:i. B* chuy1n .ei ADC trn AVR khng ho:t .*ng theo
nguyn l flash ADC m ti ./ cAp W phLn trn, ADC trong AVR l lo:i
chuy1n .ei x5p xU lLn l<Xt (successive approximation ADC).
ADC trn AVR cLn .<Xc nui bZng nguPn .iBn p ring W chn
AVCC, gi trS .iBn p c5p cho AVCC khng .<Xc khc nguPn nui chip
(VCC) qu +/-0.3V. NhiIu (noise) l v5n ./ r5t quan tr-ng khi sC dHng cc
b* ADC, .1 gi2m thi1u sai sR chuy1n .ei do nhiIu, nguPn c5p cho ADC cLn
ph2i .<Xc l-c (filter) kg cng. M*t cch .@n gi2n .1 t:o nguPn AVCC l
dng m*t m:ch LC k>t nRi t; nguPn VCC câ chip nh< minh h-a trong hnh
3, .y l cch .<Xc gXi bWi nh s2n xu5t AVR.
Ntinside 85

Hnh 3. T:o nguPn AVCC t; VCC.
biBn p tham chi>u cho ADC trn AVR c th1 .<Xc t:o bWi 3 nguPn:
dng .iBn p tham chi>u n*i 2.56V (cR .Snh), dng .iBn p AVCC hoDc .iBn
p ngoi .Dt trn chn VREF. M*t lLn n[a, b:n cLn ch .>n noise khi .Dt
.iBn p tham chi>u, n>u dng .iBn p ngoi .Dt trn chn VREF th .iBn p
ny ph2i .<Xc l-c thAt tRt, n>u dng .iBn p tham chi>u n*i 2.56V hoDc
AVCC th chn VREF cLn .<Xc nRi v?i m*t tH .iBn. ViBc ch-n .iBn p tham
chi>u sc .<Xc ./ cAp chi ti>t trong phLn sC dHng ADC.
Cc chn trn PORTA câ chip ATmega32 .<Xc dng cho b* ADC,
chn PA0 t<@ng Gng knh ADC0 v chn PA7 t<@ng Gng v?i knh ADC7.
Ntinside 86
1. Thanh ghi.
C 4 thanh trong b* ADC trn AVR trong . c 2 thanh ghi data chGa
d[ liBu sau khi chuy1n .ei, 2 thanh ghi .i/u khi1n v chGa tr:ng thi câ
ADC.
- ADMUX (ADC Multiplexer Selection Register): l 1 thanh ghi 8 bit
.i/u khi1n viBc ch-n .iBn p tham chi>u, knh v ch> .* ho:t .*ng câ
ADC. ChGc nKng câ t;ng bit trn thanh ghi ny sc .<Xc trnh by cH th1
nh< sau:

Bit 7:6- REFS1:0 (Reference Selection Bits): l cc bit ch-n .iBn p
tham chi>u cho ADC, 1 trong 3 nguPn .iBn p tham chi>u c th1 .<Xc ch-n
l: .iBn p ngoi t; chn VREF, .iBn p tham chi>u n*i 2.56V hoDc .iBn p
AVCC. B2ng 2 tm tMt gi trS cc bit v .iBn p tham chi>u t<@ng Gng.
B2ng 2: Ch-n .iBn p tham chi>u

Bit 5-ADLAR (ADC Left Adjust Result): l bit cho php hiBu chUnh
tri k>t qu2 chuy1n .ei. SW d\ c bit ny l v ADC trn AVR c .* phn
gi2i 10 bit, ngh\a l k>t qu2 thu .<Xc sau chuy1n .ei l 1 sR c .* di 10 bit
(tRi .a 1023), AVR bR tr 2 thanh ghi data 8 bit .1 chGa gi trS sau chuy1n
.ei. Nh< th> gi trS chuy1n .ei sc khng lMp .Ly 2 thanh ghi data, trong m*t
sR tr<Qng hXp ng<Qi dng muRn 10 bit k>t qu2 nZm lBch v/ pha tri trong
khi c7ng c tr<Qng hXp ng<Qi dng muRn k>t qu2 nZm v/ pha ph2i. Bit
ADLAR sc quy>t .Snh vS tr câ 10 bit k>t qu2 trong 16 bit câ 2 thanh ghi
data. N>u ADLAR=0 k>t qu2 sc .<Xc hiBu chUnh v/ pha ph2i (thanh ghi
ADCL chGa tr-n 8 bit th5p v thanh ghi ADCH chGa 2 bit cao trong 10 bit
k>t qu2), v n>u ADLAR=1 th k>t qu2 .<Xc hiBu chUnh tri (thanh ghi
ADCH chGa tr-n 8 bit cao nh5t, cc bit t; 9 .>n 2, v thanh ADCL chGa 2
Ntinside 87
bit th5p nh5t trong 10 bit k>t qu2 (b:n xem hnh cch bR tr 2 thanh ghi
ADCL v ADCH bn d<?i .1 hi1u r h@n).
Bits 4:0-MUX4:0 (Analog Channel and Gain Selection Bits): l 5 bit
cho php ch-n knh, ch> .* v c2 hB sR khuy>ch .:i cho ADC. Do b* ADC
trn AVR c nhi/u knh v cho php th`c hiBn chuy1n .ei ADC ki1u so
snh (so snh .iBn p gi[a 2 chn analog) nn tr<?c khi th`c hiBn chuy1n
.ei, chng ta cLn set cc bit MUX .1 ch-n knh v ch> .* cLn sC dHng.
B2ng 3 tm tMt cc ch> .* ho:t .*ng câ ADC thng qua cc gi trS câ cc
bit MUX. Trong b2ng ny, Gng v?i cc gi trS t; 00000 .>n 00111 (nhS
phn), cc knh ADC .<Xc ch-n W ch> .* .@n knh (tn hiBu input l5y tr`c
ti>p t; cc chn analog v so snh v?i 0V), gi trS t; 01000 .>n 11101 t<@ng
Gng v?i ch> .* chuy1n .ei so snh.
B2ng 3: Ch-n ch> .* chuy1n .ei.
Ntinside 88

- ADCSRA (ADC Control and Status RegisterA): l thanh ghi chnh
.i/u khi1n ho:t .*ng v chGa tr:ng thi câ module ADC.
Ntinside 89

T;ng bit câ thanh ghi ADCSRA .<Xc m t2 nh< bn d<?i:
Bit 7 - ADEN(ADC Enable): vi>t gi trS 1 vo bit ny tGc b:n . cho
php module ADC .<Xc sC dHng. Tuy nhin khi ADEN=1 khng c ngh\a l
ADC . ho:t .*ng ngay, b:n cLn set m*t bit khc ln 1 .1 bMt .Lu qu trnh
chuy1n .ei, . l bit ADSC.
Bit 6 - ADSC(ADC Start Conversion): set bit ny ln 1 l bMt .Lu
khWi .*ng qu trnh chuy1n .ei. Trong suRt qu trnh chuy1n .ei, bit ADSC
sc .<Xc gi[ nguyn gi trS 1, khi qu trnh chuy1n .ei k>t thc (t` .*ng), bit
ny sc .<Xc tr2 v/ 0. V vAy b:n khng cLn v c7ng khng nn vi>t gi trS 0
vo bit ny W b5t kN tnh huRng no. b1 th`c hiBn m*t chuy1n .ei, thng
th<Qng chng ta sc set bit ADEN=1 tr<?c v sau . set ADSC=1.
Bit 4 ADIF(ADC Interrupt Flag): cQ bo ngMt. Khi m*t chuy1n .ei
k>t thc, bit ny t` .*ng .<Xc set ln 1, v th> ng<Qi dng cLn ki1m tra gi
trS bit ny tr<?c khi th`c hiBn .-c gi trS chuy1n .ei .1 .2m b2o qu trnh
chuy1n .ei . th`c s` hon t5t.
Bit 3 ADIE(ADC Interrupt Enable): bit cho php ngMt, n>u bit ny
.<Xc set bZng 1 v bit cho php ngMt ton cHc (bit I trong thanh ghi tr:ng
thi câ chip) .<Xc set, m*t ngMt sc x2y ra khi m*t qu trnh chuy1n .ei
ADC k>t thc v cc gi trS chuy1n .ei . .<Xc cAp nhAt (cc gi trS chuy1n
.ei chGa trong 2 thanh ghi ADCL v ADCH).
Bit 2:0 ADPS2:0(ADC Prescaler Select Bits): cc bit ch-n hB sR
chia xung nhSp cho ADC. ADC, c7ng nh< t5t c2 cc module khc trn AVR,
cLn .<Xc gi[ nhSp bZng m*t nguPn xung clock. Xung nhSp ny .<Xc l5y t;
nguPn xung chnh câ chip thng qua m*t hB sR chia. Cc bit ADPS cho
php ng<Qi dng ch-n hB sR chia t; nguPn clock chnh .>n ADC. Tham
kh2o b2ng 4 .1 bi>t cch ch-n hB sR chia.
B2ng 4: HB sR chia xung nhSp cho ADC.
Ntinside 90

- ADCL v ADCH (ADC Data Register): 2 thanh ghi chGa gi trS câ
qu trnh chuy1n .ei. Do module ADC trn AVR c .* phn gi2i tRi .a 10
bits nn cLn 2 thanh ghi .1 chGa gi trS chuy1n .ei. Tuy nhin teng sR bt
câ 2 thanh ghi 8 bit l 16, con sR ny nhi/u h@n 10 bit câ k>t qu2 chuy1n
.ei, v th> chng ta .<Xc php ch-n cch ghi 10 bit k>t qu2 vo 2 thanh ghi
ny. Bit ADLAR trong thanh ghi ADMUX quy .Snh cch m k>t qu2 .<Xc
ghi vo.
ADLAR=0:

ADLAR=1:

Thng th<Qng, 2 thanh ghi data .<Xc sMp x>p theo .Snh d:ng
ADLAR=0, ADCL chGa 8 bit th5p v 2 bit th5p câ ADCH chGa 2 bit cao
nh5t câ gi trS thu .<Xc. Ch thG t` .-c gi trS t; 2 thanh ghi ny, .1
trnh .-c sai k>t qu2, b:n cLn .-c thanh ghi ADCL tr<?c v ADCH sau, v
sau khi ADCH .<Xc .-c, cc thanh ghi data c th1 .<Xc cAp nhAt gi trS ti>p
theo.
- SFIOR(Special FunctionIO Register C): thanh ghi chGc nKng .Dc
biBt, 3 bit cao trong thanh ghi ny quy .Snh nguPn kch ADC n>u ch> .*
Auto Trigger .<Xc sC dHng. b l cc bit ADTS2:0 (Auto Trigger Source
2:0). Cc lo:i nguPn kch .<Xc trnh by trong b2ng 5.
Ntinside 91

B2ng 5: NguPn kch ADC trong ch> .* Auto Trigger.

2. SU d5ng ADC- ChuyGn =Ki =.n knh.
Khi niBm .@n knh .<Xc hi1u l .:i l<Xng cLn chuy1n .ei l cc .iBn
p .Dt tr`c ti>p trn cc chn analog câ chip, gi trS .iBn p ny .<Xc so
snh v?i 0V câ chip, hay ni m*t cch khc, .iBn p cLn chuy1n .ei v chip
AVR c mass chung. Chng ta sc minh h-a cch sC dHng ADC trn AVR
W ch> .* .@n knh bZng v dH .-c v hi1n thS gi trS ADC trn cc LED 7
.o:n. Nh< minh h-a trong hnh 4, chng ta sc dng 4 LED .1 hi1n thS 4 ch[
sR câ k>t qu2, do chng ta ./u bi>t ADC trn AVR c .* phn gi2i 10 bit
nn k>t qu2 chuy1n .ei tRi .a l 1023, 4 LED l .^ .1 hi1n thS k>t qu2 ny. 4
chip 7447 .<Xc dng .1 .i/u khi1n 4 LED, chng ta cLn 16 .<Qng .1 xu5t
d[ liBu hi1n thS ln 4 LED v th> PORTB v PORTC sc .<Xc dng cho mHc
.ch ny. 4 bit cao câ PORTC(PC4:7) chGa ch[ sR hng nghn câ k>t qu2,
4 bit th5p PC0:3 chGa ch[ sR hng trKm, 4 bit cao câ PORTB(PB4:7) dng
xu5t ch[ sR hng chHc v 4 bit PB0:3 dnh cho ch[ sR hng .@n vS. b:i
l<Xng cLn chuy1n .ei l .iBn p trn chn ADC0 (knh 0 câ ADC, chn 0
trong PORTA chip ATmega32), .iBn p .<Xc t:o ra bZng m*t bi>n trW RV1.
Thay .ei gi trS bi>n trW, .iBn p r@i trn ADC0 thay .ei v .<Xc cAp nhAt
tr`c ti>p trn cc LED. Gi trS hi1n thS trn LED khng ph2i l gi trS .iBn p
m l gi trS t<@ng .Ri sau khi chuy1n .ei. Trong v dH ny, ti sc trnh by
d:ng teng qut, viBc .-c ADC v hi1n thS LED .<Xc vi>t trong cc ch<@ng
trnh con t<@ng Gng. BZng cch ny, cc b:n c th1 dI dng sCa .ei v mW
r*ng v dH sau ny.
Ntinside 92

Hnh 4. b-c ADC .@n knh.
List 1 trnh by .o:n code minh h-a .-c ADC .@n knh v hi1n thS k>t
qu2 trn LED 7 .o:n.
List 1. b-c ADC .@n knh v hi1n thS bZng LED 7 .o:n.
Ntinside 93
Ntinside 94

Ti t:m thQi chia .o:n ch<@ng trnh thnh 4 phLn, phLn 1 l cc .Snh
ngh\a (dng 4 .>n 7), phLn 2 l ch<@ng trnh con .-c ADC .@n knh (dng
10 .>n 14), phLn 3 l ch<@ng trnh con hi1n thS mt gi trS 4 ch[ sR ln 4
LED 7 .o:n (t; dng 17 .>n 30) v phLn 4 l ch<@ng trnh chnh. Chng ta
sc tm hi1u theo t;ng phLn.
- Ph>n 1: ba dng 4, 5 v 6 chng ta .Snh ngh\a 3 bi>n .:i diBn tn câ 3
mode .iBn p tham chi>u c th1 dng cho ADC. Xem l:i b2ng 2 chng ta
bi>t rZng .iBn p tham chi>u .<Xc ch-n thng qua 2 bit REFS trong thanh
ghi ADMUX, c 3 lo:i .iBn p c th1 .<Xc ch-n. Bi>n AREF_MODE t<@ng
Gng v?i tr<Qng hXp chng ta muRn l5y .iBn p trn chn AREF lm .iBn p
tham chi>u, .Ri chi>u b2ng 2 chng ta cLn set 2 bit REFS bZng 0, v dng 4
#define AREF_MODE 0 th`c hiBn viBc ny. T<@ng t`, bi>n
INT_MODE .:i diBn cho tr<Qng hXp .iBn p tham chi>u n*i 2.56V v .<Xc
.Snh ngh\a cho php set 1 bit REFS ln 1 #define INT_MODE
(1<<REFS1)|(1<<REFS0). Bi>n AVCC_MODE .:i diBn tr<Qng hXp .iBn
p tham chi>u l5y t; chn AVCC. CuRi cng, bi>n ADC_VREF_TYPE
.<Xc .Snh ngh\a l bi>n ch-n mode m chng ta th`c s` muRn dng cho
ADC, trong v dH ny ti ch-n .iBn p tham chi>u l5y t; chn AVCC v th>
ti .Snh ngh\a #define ADC_VREF_TYPE AVCC_MODE. Bit
ADC_VREF_TYPE sc .<Xc gn cho thanh ghi ADMUX khi khWi .*ng
ADC trong ch<@ng trnh chnh.
- Ph>n 2-ch9.ng trnh con =Rc ADC =.n knh uint16_t
read_adc(unsigned char adc_channel): tn ch<@ng trnh l read_adc v
adc_channel l tham sR cLn truy/n cho ch<@ng trnh con, tham sR ny l chU
sR knh muRn .-c (t; knh 0 .>n knh 7). Gi trS tr2 v/ l m*t sR nguyn
khng d5u 16 bit (ki1u unsigned int câ C), tuy nhin trong v dH ny ti
dng ki1u d[ liBu uint16_t thay cho unsigned int, uint16_t l m*t cch .Snh
ngh\a ki1u d[ liBu nguyn khng d5u 16 bit câ ring th< viBn gcc-avr.
Dng .Lu tin câ .o:n ch<@ng trnh con (dng 11) l khai bo knh muRn
.-c bZng cch ghp gi trS knh cho thanh ghi ADMUX ADMUX
|=adc_channel;. Xem l:i c5u trc thanh ghi ADMUX, trong thanh ghi ny,
ngoi cc bit ch-n nguPn .iBn p tham chi>u REFS th 5 bit th5p MUX4:0
cho php ch-n knh ADC cLn .-c. Tham kh2o them b2ng 3 chng ta th5y
rZng 8 gi trS .Lu tin câ cc bit MUX4:0 (t; 00000 .>n 00111 nhS phn)
t<@ng Gng v?i 8 knh .@n ADC0:7. Chnh s` sMp x>p ny cho php chng ta
ghp tr`c ti>p gi trS knh muRn .-c vo thanh ghi ADMUX thng qua dng
lBnh ADMUX |=adc_channel. Chng ta dng php OR | v chng ta chU
muRn thay .ei gi trS c bit MUX m khng muRn lm 2nh h<Wng .>n gi trS
Ntinside 95
cc bit khc trong thanh ghi ADMUX khi ch-n knh. M*t ch quan tr-ng
l gi trS câ tham sR adc_channel chU trong kho2ng t; 0 .>n 7 t<@ng Gng v?i
8 ch> .* .-c .@n knh ADC trong b2ng 3. Sau khi knh . .<Xc ch-n, dng
12 set bit ADCS trong thanh ghi ADCSRA .1 bMt .Lu qu trnh chuy1n .ei
ADCSRA|=(1<<ADSC);. Nh< . ./ cAp trong khi kh2o st chGc nKng câ
bit ADIF trong thanh ghi ADCSRA, sau khi qu trnh chuy1n .ei k>t thc
bit ADIF sc .<Xc t` .*ng set ln 1, v th> dng code 13 .<Xc dng .1 chQ
cho bit ny ln 1, tGc chQ cho qu trnh chuy1n .ei k>t thc. Cu lBnh
loop_until_bit_is_set(ADCSRA,ADIF); .<Xc hi1u l lDp cho .>n khi bit
ADIF trong thanh ghi ADCSRA .<Xc set ln 1, lBnh loop_until_bit_is_set
ny .<Xc .Snh ngh\a sdn trong th< viBn gcc-avr. N>u qu trnh chuy1n .Yi
. k>t thc, k>t qu2 chuy1n .ei sc .<Xc chGa trong 2 thanh ghi ADCL v
ADCH, 2 thanh ghi ny .<Xc t` .*ng g-p thnh thanh ghi 16 bit ADCW
(ADC WORD), dng 14 return ADCW tr2 v/ k>t qu2 chuy1n .ei.
- Ph>n 3-ch9.ng trnh con hiGn th7 sI c 4 chP sI ln 4 LED 7 =o3n
void LED7_out(uint16_t val) : val l sR cLn hi1n thS, chng ta khai bo
4 bi>n t:m dvi, chuc, tram, nghin .:i diBn cho cc ch[ sR .@n vS, chHc,
trKm v nghn W dng 18. bPng thQi, m*t bi>n t:m temp_val .<Xc dng .1
ln 26 th`c hiBn qu trnh tch sR val ra thnh 4 cc ch[ sR
hng .@n vS, chHc, trKm v nghn. by chU l ph<@ng php .:i sR thng
th<Qng nn ti sc khng gi2i thch thm cho .o:n ny. Hai dng 28 v 29
xu5t gi trS ra 4 LED 7 .o:n. BRn LED 7 .o:n .<Xc .i/u khi1n bWi cc IC
chuy1n m 7447, gi trS input choc cc IC 7447 l cc sR BCD 4 bit. V th>,
.1 xu5t 4 ch[ sR ra 4 LED thng qua 7447 chng ta cLn 4x4=16 bit, trong v
dH ny ti dng PORTB v PORTC cho nhiBm vH ny. BRn bit cao câ
PORTC sc chGa ch[ sR hng nghn, bRn bit th5p chGa ch[ sR hng trKm, bRn
bit cao câ PORTB chGa ch[ sR hng chHc v bRn bit th5p PORTB chGa sR
.@n vS. Dng code 28 PORTB=(chuc<<4)+dvi; xu5t 2 ch[ sR chHc v .@n
vS ra PORTB, trong . hm chuc<<4 ngh\a l dSch ch[ sR hng chHc sang
tri 4 vS tr .1 .<a ch[ sR ny ln 4 bit cao câ PORTB, sau . c*ng ch[ sR
.@n vS vo 4 bit th5p v cuRi cng l xu5t ra PORTB. T<@ng t` chng ta c
th1 xu5t 2 ch[ sR hng nghn v hng trKm ra PORTC thng qua dng code
29 PORTC=(nghin<<4)+tram.
- Ph>n 4-ch9.ng trnh chnh: do hLu h>t cc nhiBm vH . .<Xc th`c
hiBn trong cc .o:n ch<@ng trnh con nn ch<@ng trnh chnh trong v dH ny
kh .@n gi2n. Hai dng code 32 v 33 set cc thng sR cho ADC, dng 32
ADCSRA=(1<<ADEN)|(1<<ADPS2)|(1<<ADPS0); set cc bit trong
Ntinside 96
thanh ghi .i/u khi1n ADCSRA, ADC .<Xc cho php ho:t .*ng bWi bit
ADEN, cc bit ADPS2:0 .1 ch-n prescaler xung clock (xem l:i phLn m t2
thanh ghi ADCSRA), trong v dH ny ti ch-n prescaler = 32 (b:n c th1
ch-n gi trS khc). Dng 33 ADMUX=ADC_VREF_TYPE; cho php
ch-n .iBn p tham chi>u bZng cch gn bi>n ADC_VREF_TYPE m chng
ta . .Snh ngh\a trong dng code 7 cho thanh ghi ADMUX. B:n cLn ch l
sau khi th`c hiBn 2 dng code ny, ADC chU m?i W t< th> sdn sng nh<ng
van ch<a ho:t .*ng, ADC sc ho:t .*ng khi chng ta g-i ch<@ng trnh con
.-c adc. Trong vng lDp while câ ch<@ng trnh chnh chng ta lLn l<Xt .-c
gi trS ADC W knh 0 bZng cch g-i ch<@ng trnh con read_adc(0) W dng
lBnh 39 ADC_val=read_adc(0); sau . hi1n thS ra LED 7 .o:n W dng 40
LED7_out(ADC_val); v cuRi cng l delay 1 kho2ng thQi gian nh_
(100ms) tr<?c khi lDp l:i qu trnh .-c v hi1n thS.
M ph_ng v dH: T:o 1 project bZng Programmer Notepad v type .o:n code
trn vo file source (xem phLn t:o Project v?i WinAVR). Bin dSch v ch:y
m ph_ng v?i m:ch .iBn trong hnh 4. bi/u chUnh gi trS bi>n trW RV1 .1
thay .ei gi trS .iBn p input câ ADC knh 0 v xem gi trS hi1n thS trn cc
LED 7 .o:n. Hy thay .ei gi trS bi>n ADC_VREF_TYPE trong dng code
7 sang cc mode khc nh< INT_MODE, bin dSch v m ph_ng l:i ch<@ng
trnh, quan st v so snh s` khc nhau gi[a cc mode .iBn p tham chi>u.
B:n sc dI dng nhAn th5y rZng khi ch-n .iBn p tham chi>u n*i 2.56V, khi
tKng bi>n trW .>n kho2ng gi[a th k>t qu2 chuy1n .ei sc l 1023(gi trS l?n
nh5t câ sR 10 bit) v n>u ti>p tHc tKng bi>n trW gi trS ny sc khng thay .ei.
bi/u ny c ngh\a l n>u .iBn p input l?n h@n .iBn p tham chi>u th k>t
qu2 chuy1n .ei sc l 1023.
PhLn chuy1n .ei ADC W ch> .* so snh sc .<Xc trnh by trong 1 dSp
khc W phLn Gng dHng.

Ntinside 97
Bi 7 - Giao ti#p SPI

I. Gi-i thi0u.
Bi ny gip cc b:n bi>t cch sC dHng cch truy/n thng nRi ti>p .Png
b* SPI. Cng cH chnh c7ng l 2 b* phLn m/m AVRStudio (+gcc-avr) v
Proteus. Th`c ch5t ngn ng[ lAp trnh van l gcc-avr nh<ng ti khng dng
Programmer Notepad .1 bi>t code nh< thng th<Qng, thay vo . ti dng
AVRStudio lm trnh bin tAp, b:n tham kh2o thm phLn LAp trnh C bZng
AVRStudio trong bi h<?ng dan sC dHng AVRStudio .1 bi>t thm cch
th`c hiBn. Ti sc dng chip ATmega32 lm minh h-a.
Nguyn l truy/n thng nRi ti>p SPI.
SC dHng module SPI trong AVR W cc ch> .* Master v Slave.
II. ChuYn truyTn thng SPI,
SPI (Serial Peripheral Bus) l m*t chu]n truy/n thng nRi ti>p tRc .*
cao do hang Motorola ./ xu5t. by l ki1u truy/n thng Master-Slave, trong
. c 1 chip Master .i/u phRi qu trnh tuy/n thng v cc chip Slaves .<Xc
.i/u khi1n bWi Master v th> truy/n thng chU x2y ra gi[a Master v Slave.
SPI l m*t cch truy/n song cng (full duplex) ngh\a l t:i cng m*t thQi
.i1m qu trnh truy/n v nhAn c th1 x2y ra .Png thQi. SPI .i khi .<Xc g-i
l chu]n truy/n thng 4 dy v c 4 .<Qng giao ti>p trong chu]n ny . l
SCK (Serial Clock), MISO (Master Input Slave Output), MOSI (Master
Ouput Slave Input) v SS (Slave Select). Hnh 1 th1 hiBn m*t k>t SPI gi[a
m*t chip Master v 3 chip Slave thng qua 4 .<Qng.
SCK: Xung gi[ nhSp cho giao ti>p SPI, v SPI l chu]n truy/n .Png b*
nn cLn 1 .<Qng gi[ nhSp, mYi nhSp trn chn SCK bo 1 bit d[ liBu .>n
hoDc .i. by l .i1m khc biBt v?i truy/n thng khng .Png b* m chng ta
. bi>t trong chu]n UART. S` tPn t:i câ chn SCK gip qu trnh tuy/n t
bS lYi v v th> tRc .* truy/n câ SPI c th1 .:t r5t cao. Xung nhSp chU .<Xc
t:o ra bWi chip Master.
MISO Master Input / Slave Output: n>u l chip Master th .y l
.<Qng Input cn n>u l chip Slave th MISO l:i l Output. MISO câ Master
v cc Slaves .<Xc nRi tr`c ti>p v?i nhau..
MOSI Master Output / Slave Input: n>u l chip Master th .y l
Ntinside 98
.<Qng Output cn n>u l chip Slave th MOSI l Input. MOSI câ Master v
cc Slaves .<Xc nRi tr`c ti>p v?i nhau.
SS Slave Select: SS l .<Qng ch-n Slave cLn giap ti>p, trn cc chip
Slave .<Qng SS sc W mGc cao khi khng lm viBc. N>u chip Master ko
.<Qng SS câ m*t Slave no . xuRng mGc th5p th viBc giao ti>p sc x2y ra
gi[a Master v Slave .. ChU c 1 .<Qng SS trn mYi Slave nh<ng c th1 c
nhi/u .<Qng .i/u khi1n SS trn Master, ty thu*c vo thi>t k> câ ng<Qi
dng.
.
Hnh 1. Giao diBn SPI.
Ho3t =Dng: mYi chip Master hay Slave c m*t thanh ghi d[ liBu 8 bits.
CG mYi xung nhSp do Master t:o ra trn .<Qng gi[ nhSp SCK, m*t bit trong
thanh ghi d[ liBu câ Master .<Xc truy/n qua Slave trn .<Qng MOSI, .Png
thQi m*t bit trong thanh ghi d[ liBu câ chip Slave c7ng .<Xc truy/n qua
Master trn .<Qng MISO. Do 2 gi d[ liBu trn 2 chip .<Xc gWi qua l:i .Png
thQi nn qu trnh truy/n d[ liBu ny .<Xc g-i l song cng. Hnh 2 m t2
qu trnh truy/n 1 gi d[ liBu th`c hiBn bWi module SPI trong AVR, bn tri
l chip Master v bn ph2i l Slave.
Ntinside 99

Hnh 2. Truy/n d[ liBu SPI.
C`c câ xung gi[ nhSp, phase v cc ch> .* ho:t .*ng: c`c câ xung
gi[ nhSp (Clock Polarity) .<Xc g-i tMt l CPOL l khi niBm dng chU tr:ng
thi câ chn SCK W tr:ng thi nghU. % tr:ng thi nghU (Idle), chn SCK c
th1 .<Xc gi[ W mGc cao (CPOL=1) hoDc th5p (CPOL=0). Phase (CPHA)
dng .1 chU cch m d[ liBu .<Xc l5y mau (sample) theo xung gi[ nhSp. D[
liBu c th1 .<Xc l5y mau W c:nh ln câ SCK (CPHA=0) hoDc c:nh xuRng
(CPHA=1). S` k>t hXp câ SPOL v CPHA lm nn 4 ch> .* ho:t .*ng câ
SPI. Nhn chung viBc ch-n 1 trong 4 ch> .* ny khng 2nh h<Wng .>n ch5t
l<Xng truy/n thng m chU cRt sao cho c s` t<@ng thch gi[a Master v
Slave.
III. TruyTn thng SPI trn AVR.
Module SPI trong cc chip AVR hLu nh< hon ton giRng v?i chu]n SPI
m t2 trong phLn trn. V th>, n>u . hi1u cch truy/n thng SPI th sc
khRng qu kh .1 th`c hiBn viBc truy/n thng ny v?i AVR. PhLn bn d<?i
ti trnh by m*t sR .i1m quan tr-ng khi .i/u khi1n SPI trn AVR.
Cc chn SPI: Cc chn giao ti>p SPI c7ng chnh l cc chn PORT thng
th<Qng, v th> n>u muRn sC dHng SPI chng ta cLn xc lAp h<?ng cho cc
chn ny. Trn chip ATmega32, cc chn SPI nh< sau:
SCK PB7 (chn 8)
MISO PB6 (chn 7)
MOSI PB5 (chn 6)
SS PB4 (chn 5)
Khi chip AVR .<Xc sC dHng lm Slave, b:n cLn set cc chn SCK input,
MOSI input, MISO output v SS input. N>u l Master th SCK output,
MISO output, MOSI input v khi ny chn SS khng quan tr-ng, chng ta
Ntinside 100
c th1 dng chn ny .1 .i/u khi1n SS câ Slaves hoDc b5t kN chn PORT
thng th<Qng no.
Thanh ghi: SPI trn AVR .<Xc vAn hnh bWi 3 thanh ghi bao gPm
thanh ghi .i/u khi1n SPCR , thanh ghi tr:ng thi SPSR v thanh ghi d[ liBu
SPDR.
SPCR (SPI Control Register): l 1 thanh ghi 8 bit .i/u khi1n t5t c2
ho:t .*ng câ SPI.

* Bit 7- SPIE (SPI Interrupt Enable) bit cho php ngMt SPI. N>u bit ny .<Xc
set bZng 1 v bit I trong thanh ghi tr:ng thi .<Xc set bZng 1 (sei), 1 ngMt sc
x2y ra sau khi m*t gi d[ liBu .<Xc truy/n hoDc nhAn. Chng ta nn dng
ngMt (nh5t l .Ri v?i chip Slave) khi truy/n nhAn d[ liBu v?i SPI.
* Bit 6 SPE (SPI Enable). set bit ny ln 1 .1 cho php b* SPI ho:t .*ng.
N>u SPIE=0 th module SPI d;ng ho:t .*ng.
* Bit 5 DORD (Data Order)
bit ny chU .Snh thG t` d[ liBu cc bit .<Xc truy/n v nhAn trn cc .<Qng MISO v MOSI,

khi DORD=0 bit c tr-ng sR l?n nh5t câ d[ liBu .<Xc truy/n tr<?c (MSB) ng<Xc l:i khi DORD=1, bit LSB
.<Xc truy/n tr<?c. ThAt

ra khi giao ti>p gi[a 2 AVR v?i nhau, thG t` ny khng quan tr-ng nh<ng ph2i .2m b2o cc bit DORD giRng
nhau trn c2 Master v

Slaves.
bit ny chU .Snh thG t` d[ liBu cc bit .<Xc truy/n v nhAn trn cc .<Qng
MISO v MOSI, khi DORD=0 bit c tr-ng sR l?n nh5t câ d[ liBu .<Xc
truy/n tr<?c (MSB) ng<Xc l:i khi DORD=1, bit LSB .<Xc truy/n tr<?c.
ThAt ra khi giao ti>p gi[a 2 AVR v?i nhau, thG t` ny khng quan tr-ng
nh<ng ph2i .2m b2o cc bit DORD giRng nhau trn c2 Master v Slaves.
* Bit 4 MSTR (Master/Slave Select) n>u MSTR =1 th chip .<Xc nhAn
diBn l Master, ng<Xc l:i MSTR=0 th chip l Slave..
* Bit 3 v 2 CPOL v CPHA .y chnh l 2 bit xc lAp c`c câ xung gi[
nhSp v c:nh sample d[ liBu m chng ta . kh2o st trong phLn .Lu. S` k>t
hXp 2 bit ny t:o thnh 4 ch> .* ho:t .*ng câ SPI. M*t lLn n[a, ch-n ch>
.* no khng quan tr-ng nh<ng ph2i .2m b2o Master v Slave cng ch> .*
ho:t .*ng. V th> c th1 .1 2 bit ny bZng 0 trong t5t c2 cc chip. Hnh 3
trnh by cch sample d[ liBu trong 4 ch> .* câ SPI trn AVR.
CPHA=0.
Ntinside 101

CPHA=1.

Hnh3 Cc ch> .* ho:t .*ng câ SPI.
* Bit 1:0 CPR1:0 hai bit ny k>t hXp v?i bit SPI2X trong thanh ghi SPSR
cho php ch-n tRc .* giao ti>p SPI, tRc .* ny .<Xc xc lAp dà trn tRc .*
nguPn xung clock chia cho m*t hB sR chia. B2ng 1 tm tMt cc tRc .* m SPI
trong AVR c th1 .:t. Thng th<Qng, tRc b* ny khng .<Xc l?n h@n 1/4 tRc
.* xung nhSp cho chip.

Ntinside 102
SPSR (SPI Status Register): l 1 thanh ghi tr:ng thi câ module SPI.
Trong thanh ghi ny chU c 3 bit .<Xc sC dHng. Bit 7 SPIF l cQ bo SPI,
khi m*t gi d[ liBu . .<Xc truy/n hoDc nhAn t; SPI, bit SPIF sc t` .*ng
.<Xc set len 1. Bit 6 WCOL l bt bo va ch:m d[ liBu (Write Colision),
bit ny .<Xc AVR set ln 1 n>u chng ta cR tnh vi>t 1 gi d[ liBu m?i vo
thanh ghi d[ liBu SPDR trong khi qu trnh truy/n nhAn tr<?c ch<a k>t thc.
Bit 0 SPI2X g-i l bit nhn .i tRc .* truy/n, bit ny k>t hXp v?i 2 bit
SPR1:0 trong thanh ghi .i/u khi1n SPCR xc lAp tRc .* cho SPI.

SPDR (SPI Data Register): l thanh ghi d[ liBu câ SPI. Trn chip
Master, ghi gi trS vo thanh ghi SPDR sc kch qu trnh tuy/n thng SPI.
Trn chip Slave, d[ liBu nhAn .<Xc t; Master sc l<u trong thanh ghi SPDR,
d[ liBu .<Xc l<u sdn trong SPDR sc .<Xc truy/n cho Master.
SU d5ng SPI trn AVR: SPI trn AVR ho:t .*ng khng khc nguyn l
chung câ chu]n SPI l m5y. VAn hnh SPI trn AVR .<Xc th`c hiBn dà
trn viBc ghi v .-c 3 cc thanh ghi SPCR, SPSR v SPDR. Tr<?c khi
truy/n nhAn bZng SPI chng ta cLn khWi .*ng SPI, qu trnh khWi .*ng
th<Qng bao gPm ch-n h<?ng giao ti>p cho cc chn SPI, ch-n lo:i giao ti>p:
Master hay Slave, ch-n ch> .* SPI (SPOL, SPHA) v ch-n tRc .* giao ti>p.
Truy/n thng SPI lun .<Xc khWi x<?ng bWi chip Master, khi Master muRn
giao ti>p v?i 1 Slave no ., n sc ko chn SS câ Slave xuRng mGc th5p
(g-i l ch-n .Sa chU) v sau . vi>t d[ liBu cLn truy/n vo thanh ghi d[ liBu
SPDR, khi d[ liBu v;a .<Xc vi>t vo SPDR xung gi[ nhSp sc .<Xc t` .*ng
t:o ra trn SCK v qu trnh truy/n nhAn bMt .Lu. bRi v?i cc chip Slave, khi
chn SS bS ko xuRng n sc sdn sng cho qu trnh truy/n nhAn. Khi pht
hiBn xung gi[ nhSp trn SCK, Slave sc bMt .Lu sample d[ liBu .>n trn
.<Qng MOSI v gWi d[ liBu di trn MISO.
b1 minh h-a cho cch truy/n v nhAn d[ liBu SPI trn AVR, ti sc th`c
hiBn m*t v dH truy/n nhn 1 chi/u v?i 1 chip Master v 3 chip Slaves. T5t
c2 cc chip .<Xc dng l ATmega32, chip Master sc .i/u khi1n cc chip
Slaves thng qua 3 .<Qng ch-n chip PB0, PD1 v PD2. Cng viBc th`c hiBn
trong v dH ny nh< sau: Master sc lLn l<Xt ch-n 1 trong 3 chip Slaves v gWi
cc gi d[ liBu t<@ng Gng .>n chng, chip Slave0 sc nhAn .<Xc cc con sR
t; 0 .>n 80, Slave1 nhAn 80 .>n 160 v Slave2 nhAn d[ liBu t; 160 .>n 240.
Cc Slave sc hi1n thS gi trS m mnh nhAn .<Xc trn cc Text LCD k>t nRi
Ntinside 103
v?i PORTD W mYi Slave. S@ .P m:ch .iBn vc bZng Proteus cho v dH ny
.<Xc trnh by trong hnh 4.

Hnh 4. M phngv d" giao ti$p SPI trn AVR.
Ntinside 104
Trong bi ny, ti sc dng phLn m/m AVRStudio k>t hXp v?i gcc-avr
trong WinAVR .1 lAp trnh bZng ngn ng[ C cho AVR. B:n hy tham kh2o
thm bi AVRStudio .1 bi>t cch t:o 1 Project lAp trnh C cho AVR bZng
AVRStudio. Hy t:o 2 Project ring, 1 Project c tn SPI_Master cho chip
Master v 1 Project c tn SPI_Slave dng chung cho c2 3 Slaves. Copy file
myLCD.h dng cho .i/u khi1n Text LCD .<Xc t:o trong bi Text LCD
vo c2 2 th< mHc chGa 2 Projects m?i t:o. Vi>t .o:n code trong list 0 vo
file SPI_Master.c v .o:n code trong list 1 vo file SPI_Slave.c.
List 1. bo:n code cho SPI Master.
Ntinside 105
Ntinside 106

Ti sc gi2i thch s@ l<Xt m*t sR .i1m chnh trong .o:n code cho chip
Master. Cc phLn .Snh ngh\a t; dng thG 10 .>n dng 17 chU c tc dHng
lm cho ch<@ng trnh dI .-c hi1u h@n v c tnh t<@ng thch cao h@n, v dH
n>u b:n muRn sC dHng v dH ny cho cc chip khc b:n chU cLn thay .ei cc
.Snh ngh\a ny m khng ph2i thay .ei trong n*i dung cc ch<@ng trnh con.
Chng ta .Snh ngh\a .1 ch-n PORTB .i/u khi1n cc .<Qng ch-n chip SS
câ Slave (g-i l cc .<Qng .Sa chU), dng 18 .Snh ngh\a Slave(i) l thG t`
chn trn PORT dng cho chip Slave thG i. DI hi1u h@n, .<Qng SS trn
Slave0 sc .<Xc k>t nRi v .i/u khi1n bWi chn 0 câ PORTB (chn PB0 v
t<@ng t` cho cc Slaves cn l:i. Bi>n wData .Snh ngh\a trn dng 20 l m*t
m2ng 3 phLn tC chGa cc con sR 8 bits sc truy/n .>n cc Slaves.
Ch9.ng trnh con void SPI_MasterInit(void): Ch<@ng trnh ny
khWi .*ng cho chip Master, viBc khWi .*ng tr<?c h>t l set h<?ng cho cc
chn SPI. bRi v?i Master, cc chn t:o xung gi[ nhSp SCK v chn truy/n
d[ liBu MOSI cLn .<Xc set Output nh< trong dng 24, cc chn SPI cn l:i
l input. Dng 25 gip ko .iBn trW ko ln W chn nhAn d[ liBu MISO câ
Master. Dng lBnh 26
SPCR=(1<<SPIE)|(1<<SPE)|(1<<MSTR)|(1<<CPHA)|(1<<SPR1)|(1<<SP
R0); thAt s` khWi .*ng SPI v?i viBc set bit SPIE: cho php ngMt SPI=1, bit
SPE=1 cho php SPI ho:t .*ng, MSTR=1 xc lAp chip l chip Master.
CPHA=1 tGc chn SCK sc W mGc th5p khi SPI khng ho:t .*ng, trong khi
CPOL=0 (khng set CPOL th mDc .Snh l 0) th d[ liBu sc .<Xc sample (l5y
mau) W c:nh xuRng câ xung SCK. CuRi cng c2 2 bit SPR1 v SPR0 ./u
.<Xc set ln 1, tRc .* SPI sc bZng tRc .* nguPn cung nui chip chia cho 128
(xem b2ng 1). Dng code 29 set h<?ng Output cho cc chn dng lm chn
.Sa chU ch-n chip Slaves (cc chn PB0, PB1, PB2), sau . ko cc chn ny
ln mGc cao .1 disable t5t c2 cc Slaves (sau ny sc kch ho:t sau).
Ch9.ng trnh con void SPI_Transmit(uint8_t i, uint8_t
data): ch<@ng trnh truy/n d[ liBu qua SPI câ chip Master, ch<@ng trnh
c 2 tham sR l .Sa chU chip Slave (bi>n i) v d[ liBu cLn truy/n (bi>n data).
Tr<?c khi truy/n d[ liBu, Master sc th`c hiBn viBc ch-n Slave, dng 35
cbi(ADDRESS_PORT, Slave(i)); th`c hiBn viBc ny. Th`c ch5t dng ny
l ko chn i câ PORTB xuRng mGc th5p, c7ng l ko chn SS câ Slave
xuRng mGc th5p. Dng 36 gn gi trS cLn truy/n cho thanh ghi d[ liBu
SPDR=data, sau khi gn gi trS cho SPDR, xung clock sc t` .*ng .<Xc
Master t:o ra trn SCK, qu trnh truy/n bMt .Lu. Qu trnh truy/n k>t thc
th bit cQ SPIF trong thanh ghi tr:ng thi SPSR .<Xc set ln 1, dng 36 th`c
hiBn viBc chQ bit cQ SPIF .1 k>t thc qu trnh truy/n. Khi k>t thc truy/n 1
Ntinside 107
byte cho Slave, set chn SS câ Slave ln mGc cao .1 v hiBu ha SPI, dng
37.
Ch9.ng trnh chnh: ch<@ng trnh chnh cho chip Master SPI t<@ng
.Ri .@n gi2n, tr<?c h>t chng ta cLn g-i ch<@ng trnh con khWi .*ng SPI W
dng 43. Trong vng lDp v tAn while, lLn l<Xt gWi cc gi trS .>n cc Slaves.
Dng 46 g-i ch<@ng trnh con gWi gi trS bi>n wData[0] .>n Slave0, dng 50
truy/n bi>n wData[1] cho Slave1 v dng 54 truy/n bi>n wData[2] cho
Slave2
List 2.bo:n code cho Slave SPI.
Ntinside 108

bo:n code trong list 2 l .o:n code cho chip Slaves, ch dng 3 chng
ta include file header interrupt.h v viBc nhAn d[ liBu SPI câ SLave .<Xc
th`c hiBn bZng ngMt SPI. Cc .Snh ngh\a bi>n trong cc dng code t; 8 .>n
Ntinside 109
15 t<@ng t` nh< trong ch<@ng trnh cho chip Master. Ti sc tAp trung gi2i
thch cc .i1m khc biBt cho Slaves.
Ch9.ng trnh con void SPI_SlaveInit(void): Ch<@ng trnh ny khWi
.*ng cho chip Slave, c7ng giRng nh< tr<Qng hXp câ Master, viBc khWi .*ng
tr<?c h>t l set h<?ng cho cc chn SPI. bRi v?i Slave, chU c chn truy/n
d[ liBu MISO l cLn .<Xc set Output nh< trong dng 19, cc chn SPI cn
l:i l input. Dng 20 gip ko .iBn trW ko ln W cc chn nhAn d[ liBu
MOSI câ Slave, v chn ch-n Slave SS. ViBc ti>p theo l ci .Dt cc thanh
ghi SPI nh< trong dng lBnh 21,
SPCR=(1<<SPIE)|(1<<SPE)|(1<<CPHA)|(1<<SPR1)|(1<<SPR0); , n>u
quan st dng lBnh 26 trong List 1 chop chip Master, dng ny khng khc
l m5y, qu trnh khWi .*ng SPI cho Slave t<@ng t` Master v?i m*t .i1m
khc duy nh5t l bit MSTR, bit ny khng .<Xc set ln 1 .Ri v?i Slaves.
Trnh ph5c v5 ngSt ISR(SPI_STC_vect): SPI trn AVR chU c duy
nh5t m*t s` kiBn gy ra ngMt . l khi qu trnh truy/n-nhAn k>t thc. Tn
vector ngMt SPI trong ngn ng[ lAp trnh avr-gcc l SPI_STC_vect. Trong
v dH ny, khi m*t ngMt SPI x2y ra W Slave, chng ta sc .-c thanh ghi SPDR
v sau . hi1n thS gi trS .-c .<Xc trn LCD. Dng 37, rData=SPDR, gn
thanh ghi SPDR cho bi>n rData. T; dng 38 .>n 42 l cch hi1n thS gi trS
.-c v/ trn Text LCD bZng th< viBn myLCD (xem bi Text LCD). Dng 39
chng ta khai bo 1 bi>n t:m d:ng m2ng .*ng, dis, lm buffer chGa gi trS
ascii câ cc k t` cLn hi1n thS ln LCD. Ch l gi trS nhAn v/ l 1 con sR
8 bit, muRn hi1n thS gi trS ny ln LCD chng ta khng th1 hi1n thS tr`c ti>p
bZng lBnh putChar_LCD v hm putChar_LCD xem tham sR nhAp vo l m
Ascii, v dH chng ta nhAn v/ sR rData=65, n>u dng hm
putChar_LCD(rData) th trn LCD chU th5y k t` A v 65 l m Ascii câ
k t` A. b1 LCD hi1n thS 65 chng ta xem 65 l m*t chuYi cc k t`,
tr<?c h>t cLn chuy1n sR 65 thnh cc k t` 6 v 5, hm
sprintf(dis,"%i",rData) trong dng code 40 th`c hiBn viBc .Snh d:ng l:i
bi>n rData thnh chuYi cc k t` v chGa trong buffer dis, %i l cQ .Snh
d:ng, bo cho hm sprintf xem rData l m*t sR nguyn. Sau dng 40, v dH
rData=65, th dis=65. Dng 42 in chuYi dis ln LCD: print_LCD(dis);.
Ch9.ng trnh chnh: ch<@ng trnh chnh cho chip Slave khng lm nhi/u viBc
v cc viBc chnh nh< nhAn v hi1n thS . .<Xc th`c hiBn trong trnh phHc vH ngMt SPI.
Dng 27 sei() cho php ngMt ton cHc, .i/u ny l cLn thi>t .1 ngMt SPI c th1 x2y ra,
dng 28 g-i ch<@ng trnh con khWi .*ng SPI cho Slave, sau . khWi .*ng LCD W dng 29
v k>t thc. Khng c viBc g cLn th`c hiBn trong vng lDp while().

Ntinside 110
Bi 8 - Giao ti#p TWI - I2C

Bi ny gi?i thiBu cch giao ti>p bZng truy/n thng nRi ti>p .Png b*
Two-Wire Serial (TWI) t<@ng thch v?i chu]n I
2
C. Trong bi ny chng ta
sc kh2o st 2 mode truy/n v nhAn trn chip Master cng v?i 2 mode truy/n
v nhAn trn chip Slave. Cng cH chnh c7ng l 2 b* phLn m/m WinAVR v
Proteus. Vi .i/u khi1n ATmega32 sc .<Xc dng lm minh h-a.
- Nguyn l truy/n thng nRi ti>p TWI v I
2
C.
- SC dHng module TWI trong AVR W cc ch> .* Master.
- SC dHng module TWI trong AVR W cc ch> .* Slave.
- V dH giao ti>p gi[a cc AVR bZng TWI.
II. Giao di0n TWI I
2
C.
TWI (Two-Wire Serial Intereafce) l m*t module truy/n thng nRi ti>p
.Png b* trn cc chip AVR dà trn chu]n truy/n thng I
2
C. I
2
C l vi>t tMc
câ t; Inter-Integrated Circuit l m*t chu]n truy/n thng do hng .iBn tC
Philips Semiconductor sng lAp v xy d`ng thnh chu]n nKm 1990. Phin
b2n m?i nh5t câ I2C l V3.0 pht hnh nKm 2007. b1 hi1u thm v/ I2C
b:n c th1 tham kh2o cc ti liBu I2C Specification t; trang web câ NXP-
http://www.nxp.com (lAp bWi Philips). Trong ph:m vi bi h-c ny ti chU
gi?i thiBu giao thGc TWI .<Xc gi?i thiBu trong datasheet câ cc chip AVR
t; Atmel. Tuy nhin, v/ c@ b2n TWI trong AVR hon ton t<@ng thch I2C,
do . tm hi1u TWI câ AVR khng chU gip b:n giao ti>p gi[a cc AVR
v?i nhau m c th1 dng TWI .1 .i/u khi1n b5t kN m*t thi>t bS no theo
chu]n I2C (cc chip nh?, b* chuy1n .ei ADC, DCA, .Png hP thQi gian
th`c).
TWI (I2C) l m*t truy/n thng nRi ti>p .a chip ch^ (t:m dSch câ cHm t;
multi-master serial computer bus). Khi niBm multi-master (ti sc dng t;
ti>ng anh multi-master thay v dng .a chip ch^) .<Xc hi1u l trong trn
cng m*t bus c th1 c nhi/u h@n m*t thi>t bS lm Master, .Png thQi m*t
Slave c th1 trW thnh m*t Master n>u n c kh2 nKng. V dH trong m*t
m:ng TWI câ nhi/u AVR k>t nRi v?i nhau, b5t kN m*t AVR no ./u c th1
trW thnh Master W m*t thQi .i1m no .. Tuy nhin n>u m*t m:ng dng
m*t AVR .i/u khi1n cc chip nh? (nh< EEPROM AT24C1024 chFng h:n)
th khi niBm multi-master khng tPn t:i v cc chip nh? .<Xc thi>t k> sdn
l Slave, khng c kh2 nKng trW thnh master. TWI (I2C) .<Xc th`c hiBn
Ntinside 111
trn 2 .<Qng SDA (Serial DATA) v SCL (Serial Clock) trong . SDA l
.<Qng truy/n/nhAn d[ liBu v SCL l .<Qng xung nhSp. CKn cG theo chu]n
I2C, cc .<Qng SDA v SCL trn cc thi>t bS c c5u hnh c`c gp mW
(open-drain hoDc open-collector, tham kh2o cc m:ch sR dng transistor .1
hi1u thm), ngh\a l cLn c cc .iBn trW ko ln (pull-up resistor) cho cc
.<Qng ny. % tr:ng thi nghU (Idle), 2 chn SDA v SCL W mGc cao. Hnh 1
m t2 m*t m hnh m:ng TWI (I2C) c@ b2n.

Hnh 1. M:ng TWI (I2C) v?i nhi/u thi>t bS v 2 .iBn trW ko ln cho SDA,
SCL.
Ti>p theo chng ta tm hi1u m*t sR khi niBm v .Dc .i1m câ TWI.
Cc khi niBm v .Dc .i1m ti ./ cAp d<?i .y .<Xc dng cho c2 TWI v
I2C, n>u c s` khc biBt ti sc gi2i thch thm.
Master: l chip khWi .*ng qu trnh truy/n nhAn, pht .i .Sa chU câ
thi>t bS cLn giao ti>p v t:o xung gi[ nhSp trn .<Qng SCL.
Slave: l chip c m*t .Sa chU cR .Snh, .<Xc g-i bWi Master v phHc vH
yu cLu t; Master.
SDA- Serial Data: l .<Qng d[ liBu nRi ti>p, t5t c2 cc thng tin v/ .Sa
chU hay d[ liBu ./u .<Xc truy/n trn .<Qng ny theo thG t` t;ng bit m*t.
Ch l trong chu]n I2C, bit c tr-ng sR l?n nh5t (MSB) .<Xc truy/n tr<?c
nh5t, .Dc .i1m ny ng<Xc l:i v?i chu]n UART.
SCL Serial Clock: l .<Qng gi[ nhSp nRi ti>p. TWI (I2C) l chuLn
truy/n thng nRi ti>p .Png b*, cLn c 1 .<Qng t:o xung gi[ nhSp cho qu
trnh truy/n/nhAn, cG mYi xung trn .<Qng gi[ nhSp SCL, m*t bit d[ liBu
trn .<Qng SDA sc .<Xc l5y mau (sample). D[ liBu nRi ti>p trn .<Qng SDA
.<Xc l5y mau khi .<Qng SCL W mGc cao trong m*t chu kN gi[ nhSp, v th>
.<Qng SDA khng .<Xc .ei tr:ng thi khi SCL W mGc cao (tr; START v
STOP condition). Chn SDA c th1 .<Xc .ei tr:ng thi khi SCL W mGc th5p.
Ntinside 112

START Condition-bi/u kiBn bMt .Lu: t; tr:ng thi nghU, khi c2 SDA
v SCL W mGc cao n>u Master muRn th`c hiBn m*t cu*c g-i, Master sc
ko chn SDA xuRng th5p trong khi SCL van cao. Tr:ng thi ny g-i l
START Condition (chng ta g-i tMt l S).
STOP Condition-bi/u kiBn k>t thc: sau khi th`c hiBn truy/n/nhAn d[
liBu, n>u Master muRn k>t thc qu trnh n sc t:o ra m*t STOP condition.
STOP condition .<Xc Master th`c hiBn bZng cch ko chn SDA ln cao khi
.<Qng SCL .ang W mGc cao. STOP condition chU .<Xc t:o ra sau khi .Sa chU
hoDc d[ liBu . .<Xc truy/n/nhAn.
REPEAT START BSt =>u lZp l3i: kho2ng gi[a START v STOP
condition l kho2ng bAn câ .<Qng truy/n, cc Master khc khng tc .*ng
.<Xc vo .<Qng truy/n trong kho2ng ny. Tr<Qng hXp sau khi k>t thc
truy/n/nhAn m Master khng gWi STOP condition l:i gWi thm 1 START
condition g-i l REPEAT START. Kh2 nKng ny th<Qng .<Xc dng khi
Master muRn l5y d[ liBu lin ti>p t; cc Slaves. Hnh bn d<?i m t2 cc
Master t:o ra START, STOP v REPEAT START.

Ntinside 113
Address Packet Format (7nh d3ng gi =7a ch[: trn m:ng TWI
(I2C), t5t c2 cc thi>t bS (chip) ./u c th1 l Master hay Slave. MYi thi>t bS
c m*t .Sa chU cR .Snh g-i l Device address. Khi m*t Master muRn giao ti>p
v?i m*t Slave no ., n tr<?c h>t t:o ra m*t START condition v ti>p theo
l gWi .Sa chU Device address câ Slave cLn giao ti>p trn .<Qng truy/n, v
th> xu5t hiBn khi niBm gi .Sa chU (Address Packet). Gi .Sa chU trong
TWI (I2C) c .Snh d:ng 9 bits trong . 7 bit .Lu (g-i l SLA, .<Xc gWi li/n
sau START condition) chGa .Sa chU Slave, m*t bit READ/WRITE v m*t bit
ACK-Ackknowledge (xc nhAn). Do bit .Sa chU c .* di 7 bits nn v/ mDt
l thuy>t, trn 1 m:ng TWI (I2C) c th1 tPn t:i tRi .a 27=128 thi>t bS c .Sa
chU ring biBt. Tuy nhin, c m*t sR .Sa chU khng .<Xc sC dHng nh< cc .Sa
chU c .Snh d:ng 1111xxx (tGc cc .Sa chU l?n h@n hoDc bZng 120 khng
.<Xc dng). Ring .Sa chU 0 .<Xc dng cho cu*c g-i chung (General call).
Bit READ/WRITE (R/W) .<Xc truy/n ti>p sau 7 bit .Sa chU l bit bo cho
Slave bi>t Master muRn .-c hay ghi vo Slave. N>u bit ny bZng 0 (g-i
l W) th qu trnh Ghi d[ liBu t; Master .>n Slave .<Xc yu cLu, n>u bit
ny bZng 1 (g-i l R) th Master muRn .-c d[ liBu t; Slave v/. Tm bits
trn (SLA+R/W) .<Xc Master pht ra sau khi pht START condition, n>u
m*t Slave trn m:ng nhAn ra rZng .Sa chU m Master yu cLu trng kh?p v?i
Device address câ chnh mnh, n sc .p tr2 l:i Master bZng cch pht ra
1 tn hiBu xc nhAn ACK bZng cch ko chn SDA xuRng th5p trong xung
thG 9. Ng<Xc l:i, n>u khng c Slave .p Gng l:i, chn SDA van W mGc cao
trong xung gi[ nhSp thG 9 th g-i l tn hiBu khng xc nhAn NOT ACK,
lc ny Master cLn c nh[ng Gng xC ph hXp ty theo mYi tr<Qng hXp cH
th1, v dH Master c th1 gWi STOP condition v sau . pht l:i .Sa chU Slave
khcNh< vAy, trong 9 bit câ gi .Sa chU th chU c 8 bit .<Xc gWi bWi
Master, bit cn l:i l do Slave. V dH Master muRn yu cLu .-c d[ liBu t;
Slave c .Sa chU 43, n cLn pht .i m*t byte nh< sau trn .<Qng truy/n:
(43<<1)+1, trong . (43<<1) l dSch sR 43 v/ bn tri 1 vS tr v 7 bit .Sa chU
nZm W cc vS tr cao trong gi .Sa chU, sau . c*ng gi trS ny v?i 1 tGc l
qu trnh .-c .<Xc yu cLu.
Ntinside 114

General call CuDc gRi chung: khi Master pht .i gi .Sa chU c d:ng
0 (th`c ch5t l 0+W) tGc n muRn th`c hiBn m*t cu*c g-i chung .>n t5t c2
cc Slave. T5t nhin, cho php hay khng cho php cu*c g-i chung l do
Slave quy>t .Snh. N>u cc Slave .<Xc ci .Dt cho php cu*c g-i chung,
chng sc .p l:i Master bZng ACK. Cu*c g-i chung th<Qng x2y ra khi
Master muRn gWi d[ liBu chung .>n cc Slaves. Ch l cu*c g-i chung c
d:ng 0+R l v ngh\a v khng th1 c chuyBn Master nhAn d[ liBu t; t5t c2
cc Slave cng thQi .i1m.
Data Packet Format (7nh d3ng gi dP li0u: sau khi .Sa chU .
.<Xc pht .i, Slave . .p l:i Master bZng ACK th qu trnh truy/n/nhAn
d[ liBu sc diIn ra gi[a cDp Master/Slave ny. Ty vo bit R/W trong gi .Sa
chU, d[ liBu c th1 .<Xc truy/n theo h<?ng t; Master .>n Slave hay t; Slave
.>n Master. D di chuy1n theo h<?ng no, gi d[ liBu lun bao gPm 9 bits
trong . 8 bits .Lu l d[ liBu v 1 bit cuRi l bit ACK. Tm bits d[ liBu do
thi>t bS pht gWi v bit ACK do thi>t bS nhAn t:o ra. V dH khi Master th`c
hiBn qu trnh gWi d[ liBu .>n Slave, n sc pht ra 8 bits d[ liBu, Slave nhAn
v pht l:i ACK (ko SDA xuRng 0 W xung thG 9), sau . Master sc quy>t
.Snh gXi ti>p byte d[ liBu khc hay khng. N>u Slave pht tn hiBu NOT
ACK (khng tc .*ng SDA W xung thG 9) sau khi nhAn d[ liBu th Master sc
k>t thc qu trnh gWi bZng cch pht .i STOP condition. Hnh bn d<?i m
t2 .Snh d:ng gi d[ liBu trong TWI (I2C).
Ntinside 115

PhIi hWp gi =7a ch[ v dP li0u: m*t qu trnh truy/n/nhAn TWI (I2C)
th<Qng .<Xc bMt .Lu t; Master, Master pht .i m*t START condition sau .
gWi gi .Sa chU SLA+R/W trn .<Qng truy/n. Ti>p theo n>u c m*t Slave
.p Gng l:i, d[ liBu c th1 truy/n/nhAn lin ti>p trn .<Qng truy/n (1 hoDc
nhi/u byte lin ti>p). Khung truy/n thng th<Qng .<Xc m t2 nh< hnh bn
d<?i.

Multi-Master Bus (9Ang truyTn =a chip ch?: nh< . trnh by W
trn, TWI (I2C) l chu]n truy/n thng .a chip ch^, ngh\a l t:i m*t thQi
.i1m c th1 c nhi/u h@n 1 chip lm Master n>u cc chip ny pht ra
START condition cng lc. N>u cc Master c cng yu cLu v thao tc .Ri
v?i Slave th chng c th1 cng tPn t:i v qu trnh truy/n/nhAn c th1
thnh cng. Tuy nhin, trong .a sR tr<Qng hXp sc c m*t sR Master bS th5t
l:c (lost). M*t Master bS lost khi n truy/n/nhAn 1 mGc cao trn SDA trong
khi cc Master khc truy/n/nhAn 1 mGc th5p. Truy/n thng .a chip ch^
t<@ng .Ri phGc t:p v v th> ti sc khng ./ cAp tr<Qng hXp ny trong lc
th`c hiBn v dH giao ti>p trong bi h-c ny.
NMm .<Xc cc khi niBm v .Dc .i1m trn câ truy/n thng TWI (I2C)
l b:n . sdn sng .1 .i/u khi1n module TWI trn AVR. PhLn ti>p theo ti
sc h<?ng dan cch thao tc module TWI trn AVR thng qua m*t v dH cH
th1.
Ntinside 116
III. TWI trn AVR.
1. Thanh ghi:
TWI trn AVR .<Xc vAn hnh bWi 5 thanh ghi bao gPm thanh ghi tRc .*
gi[ nhSp TWBR, thanh ghi .i/u khi1n TWCR , thanh ghi tr:ng thi TWSR,
thanh ghi .Sa chU TWAR v thanh ghi d[ liBu TWDR.
- TWBR (TWI Bit Rate Register): l 1 thanh ghi 8 bit quy .Snh tRc .*
pht xung gi[ nhSp trn .<Qng SCL câ chip Master.

TRc .* pht xung gi[ nhSp .<Xc tnh theo cng thGc:

Trong . CPU Clock frequency l tLn sR ho:t .*ng chnh câ AVR,
TWBR l gi trS thanh thi TWBR v TWPS l gi trS câ 2 bits TWPS1 v
TWPS0 nZm trong thanh thi tr:ng thi TWSR. Hai bits ny .<Xc g-i l bit
prescaler, thng th<Qng ng<Qi ta hay set TWPS1:0 =00 .1 ch-n Prescaler l
1 (40=1). B2ng 1 tm tMt tRc .* xung gi[ nhSp t:o ra trn SCL .Ri v?i cc
gi trS câ tham sR:
B2ng 1. TRc .* xung gi[ nhSp tham kh2o.
Ntinside 117

- TWCR (TWI Control Register): l thanh ghi 8 bit .i/u khi1n ho:t
.*ng câ TWI.

Bit 7- TWINT (TWI Interrupt Flag): l m*t cQ bo r5t quan tr-ng.
TWINT .<Xc t` .*ng set ln 1 khi TWI k>t thc m*t qu trnh b5t kN no .
(nh< pht/nhAn START, pht nhAn .Sa chU). Ch l bit ny khng t`
.*ng .<Xc xa bWi phLn cGng nh< cc cQ bo trong cc module khc. V th>,
khi lAp trnh .i/u khi1n TWI chng ta lun ph2i xa TWINT tr<?c khi muRn
th`c hiBn m*t qu trnh no .. M*t .i1m quan tr-ng cLn lt gi trS 1 vo n. Trong khi lAp trnh cho
TWI, chng ta th<Qng xa TWINT bZng cch vi>t 1 vo n, sau . lin tHc
ki1m tra TWINT, n>u bit ny .<Xc set ln 1 th qu trnh . hon thnh.
Bit 6 TWEA (TWI Enable Acknowledge Bit): t:m hi1u l bit kch
ho:t tn hiBu xc nhAn. bRi v?i chip Slave, n>u bit ny .<Xc set th tn hiBu
xc ACK sc .<Xc gWi trong cc tr<Qng hXp sau: .Sa chU do Master pht ra
trng kh?p v?i .Sa chU câ Slave; m*t cu*c g-i chung .ang x2y ra v Slave
ny cho php cu*c g-i chung; d[ liBu . .<Xc Slave nhAn t; Master. Nh<
Ntinside 118
th>, khi set m*t chip W ch> .* Slave, chng ta cLn set bit ny .1 n c th1
.p Gng l:i Master b5t cG khi no .<Xc g-i. bRi v?i chip Master, tn hiBu
ACK chU .<Xc pht trong 1 tr<Qng hXp duy nh5t . l khi Master nhAn d[
liBu t; Slave, Master pht ACK .1 bo cho Slave l mnh . nhAn .<Xc v
muRn ti>p tHc nhAn t; Slave.
Bit 5 TWSTA (TWI START Condition Bit): l bit t:o START
condition. Khi m*t chip muRn trW thnh Master .1 th`c hiBn 1 cu*c g-i, bit
ny cLn .<Xc set v m*t START condition .<Xc t:o ra trn .<Qng truy/n
n>u .<Qng truy/n .ang r2nh. N>u .<Qng truy/n khng r2nh, TWI sc chQ cho
.>n khi n r2nh (nhAn ra 1 STOP condition) v ti>p tHc gWi START
condition. Ch l l bit nay cLn .<Xc xa bWi phLn m/m sau khi START
condition . .<Xc gWi (vi>t 0 vo bit ny .1 xa n).
Bit 4 TWSTO (TWI STOP Condition Bit): l bit t:o STOP
condition cho TWI. Khi Master muRn k>t thc m*t cu*c g-i, n sc pht
STOP condition bZng cch vi>t gi trS 1 vo bit TWSTO. Slave c7ng c th1
tc .*ng vo bit ny, n>u m*t cu*c g-i bS lYi, vi>t 1 vo TWSTO trn Slave
sc reset .<Qng truy/n v/ tr:ng thi r2nh ban .Lu.
Bit 3 TWWC (TWI Write Collision Flag): khi cQ TWINT .ang W
mGc th5p tGc TWI .ang bAn, n>u chng ta vi>t d[ liBu vo thanh ghi d[ liBu
(TWDR) th m*t lYi x2y ra, khi . bit TWWC t` .*ng .<Xc set ln 1. V
th>, trong qu trnh truy/n d[ liBu, bit TWINT cLn .<Xc gi[ mGc cao khi ghi
d[ liBu vo thanh ghi TWDR v sau . xa khi d[ liBu . sdn sng.
Bit 2 TWEN (TWI Enable Bit): bit kch ho:t TWI trn AVR, khi
TWEN .<Xc set ln 1, TWI sdn sng ho:t .*ng.
Bit 1 Reserve: khng sC dHng.
Bit 0 TWIE (TWI Interrupt Enable Bit): bit cho php ngMt TWI, khi
bit nay .<Xc set bZng 1 .Png thQi bit I trong thanh ghi tr:ng thi chung .<Xc
set, m*t ngMt TWI x2y ra khi bit TWINT .<Xc set bWi phLn cGng. NgMt TWI
c th1 x2y ra sau b5t kN ho:t .*ng no lin quan .>n TWI. Do . cLn sC
dHng ngMt hXp l. Thng th<Qng, ngMt chU .<Xc sC dHng cho Slave, .Ri v?i
Master ngMt khng cLn thi>t v Master ch^ .*ng khWi .*ng m*t cu*c g-i.
M*t .i/u cLn ch l cc bit trong thanh ghi TWCR khng cLn .<Xc set
cng lc, ty vo t;ng giai .o:n trong qu trnh giao ti>p TWI cc bit c th1
.<Xc set ring lf.
- TWSR (TWI Status Register): l 1 thanh ghi 8 bit trong . c 5 bit
chGa code tr:ng thi câ TWI v 2 bit ch-n prescaler.
Ntinside 119

C r5t nhi/u b<?c, nhi/u tnh huRng x2y ra khi giao ti>p bZng TWI cho
c2 Master v Slave. (ng v?i mYi tr<Qng hXp TWI sc t:o ra 1 code trong
thanh ghi TWSR . LAp trnh cho TWI cLn xt code trong 5 bit cao câ thanh
ghi TWSR v .<a ra cc Gng xC hXp l Gng v?i t;ng code.
- TWDR (TWI Data Register): l thanh ghi d[ liBu chnh câ TWI.
Trong qu trnh nhAn, d[ liBu nhAn v/ sc .<Xc l<u trong TWDR. Trong qu
trnh gWi, d[ liBu chGa trong TWDR sc .<Xc chuy1n ra .<Qng SDA.
- TWAR (TWI Address Register): l thanh ghi chGa device address
câ chip Slave. C5u trc thanh ghi .<Xc trnh by trong hnh d<?i.

Nh? l:i .Sa chU Slave .<Xc t:o thnh t; 7 bits, trn thanh ghi TWAR 7
bits .Sa chU ny nZm W 7 vS tr cao. Tr<?c khi sC dHng TWI nh< Slave, chng
ta ph2i gn .Sa chU cho chip, viBc vi>t .Sa chU th<Qng .<Xc th`c hiBn bZng
lBnh TWAR = (Device_address<<1)+TWGCE. Trong . TWGCE (TWI
General Call Enable) l bit cho php cu*c g-i chung. Nh< ti ./ cAp bn
trn, Slave co quy/n cho php Master th`c hiBn cu*c g-i chung v?i n hay
khng. N>u TWGCE=1, Slave sc .p Gng l:i cu*c g-i chung n>u c, n>u
TWGCE=0 th Slave sc b_ qua cu*c g-i chung.
2. Ho3t =Dng c?a TWI:
TWI trn AVR .<Xc g-i l byte-oriented (t:m dSch l h<?ng byte) v
interrupt-based (dà trn ngMt). B5t kN m*t s` kiBn no trong qu trnh
truy/n/nhAn TWI c7ng c th1 gy ra 1 ngMt TWI. TWI trn AVR v th> ho:t
.*ng t<@ng .Ri .*c lAp v?i chip. Tuy nhin, cLn khai thc ngMt trn AVR
m*t cch h@p l. V dH, .Ri v?i Master, chng ta khng cLn sC dHng ngMt v
chip ny hon ton ch^ .*ng trong viBc truy/n v nhAn. Ring v?i Slave, sC
dHng ngMt .1 trnh b_ ll cc cu*c g-i l cLn thi>t.
T5t c2 cc AVR trn m:ng TWI ./u c th1 l Master hay Slave, c2 Master
v Slave ./u c th1 truy/n v nhAn d[ liBu. V th>, c t5t c2 4 mode trong
ho:t .*ng câ TWI trn AVR. Chng ta sc lLn l<Xt kh2o st cc mode ny
nh< sau: Master Transmitter (chip ch^ truy/n), Master Receiver (Chip ch^
nhAn), Slave Reicever (chip t? nhAn) v Slave Transmitter (Chip t? truy/n).
Ntinside 120
Tr<?c khi kh2o st cc ch> .* ho:t .*ng câ TWI chng ta qui <?c m*t sR
k hiBu th<Qng dng (.y c7ng l cc k hiBu dng trong datasheet câ cc
chip AVR).
S: START condition .i/u kiBn bMt .Lu
Rs: REPEAT START bMt .Lu lDp l:i
R: READ Bit, bit ny bZng 1 .<Xc gWi km v?i gi .Sa chU
W: WRITE Bit, bit ny mang gi trS 0, gWi km gi .Sa chU
ACK: Ackowledge, bit xc nhAn, chn SDA .<Xc ko xuRng 0 W
xung thG 9
NACK: Not Acknowledge, khng xc nhAn, SDA W mGc cao W bit
thG 9
Data: 8 bits d[ liBu
P: STOP condition .i/u kiBn k>t thc.
SLA: Slave address, .Sa chU câ Slave cLn giao ti>p.
A. Master Transmitter mode Master truyTn dP li0u:
Trong ch> .* ny, Master truy/n 1 hoDc m*t sR byte d[ liBu .>n m*t
hoDc cc Slave. b1 bMt .Lu, Master t:o ra m*t START condition trn .<Qng
SDA, n>u .<Qng truy/n .ang r2nh, Master sc ti>p tHc pht .i .Sa chU câ
Slave cLn giao ti>p cng v?i bit W (ghi) theo .Snh d:ng nh< sau: SLA+W.
N>u Slave .p l:i bZng m*t ACK trong xung gi[ nhSp thG 9, Master sc ti>p
tHc gWi 1 hoDc lin ti>p cc byte d[ liBu trn SDA. CG sau mYi byte d[ liBu,
Master sc ki1m tra ACK t; Slave. N>u Slave gWi m*t NACK hoDc Master
khng muRn gWi thm d[ liBu .>n Slave n sc pht .i m*t STOP condition
hoDc m*t REPEAT START (Rs). N>u STOP .<Xc pht, cu*c g-i k>t thc,
n>u Rs .<Xc pht, m*t cu*c g-i m?i bMt .Lu, sau Rs l .Sa chU câ Slave
m?ib l v/ mDt l thuy>t, trn th`c t> lm sao .1 ki1m tra mt START
condition c .<Xc gWi ch<a? lm sao bi>t c nhAn .<Xc ACK sau khi pht
.Sa chU hoDc d[ liBu? T5t c2 .<Xc TWI m ha thnh cc code chGa trong
thanh ghi TWSR (chU 5 bit cao). Chng ta chU thanh ghi ny v .Ri chi>u v?i
b2ng code quy .Snh sdn .1 bi>t tr:ng thi .<Qng truy/n v .<a ra quy>t .Snh
ti>p theo. Hnh 2 m t2 m*t qu trnh Master truy/n d[ liBu, cc kh2 nKng c
th1 x2y ra v gi trS t<@ng Gng câ thanh ghi TWSR. ngh\a cc code trong
thanh ghi TWSR trong lc Master truy/n d[ liBu c th1 tham kh2o thm
datasheet câ chip.
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Hnh 2. Master truy/n d[ liBu.
T; hnh 2, chng ta nhAn th5y khi Master truy/n d[ liBu, dy code 0x08
-> 0x18 -> 0x28 -> -> 0x28 (-> 0x30) l dy code thnh cng nh5t. Code
0x08 bo rZng START codition .<Xc truy/n thnh cng, code 0x18 bo .Sa
chU truy/n thnh cng v . c Slave xc nhAn bZng ACK, code 0x28 tGc d[
liBu .<Xc Master truy/n thnh cng v Slave . nhAn .<Xc, bo ACK l:i cho
Master, code 0x30 tGc d[ liBu . .<Xc truy/n nh<ng Slave khng xc nhAn
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l:i, lc ny Master c th1 pht .i m*t STOP codition sau code 0x30. Ngoi
ra cn m*t sR code khc t<@ng Gng v?i cc tr<Qng hXp khc nh< gWi .Sa chU
th5t b:i (code 0x20), Master bS lost (code 0x38)bRi v?i mYi lo:i Gng
dHng, cch hnh xC sc khc nhau .Ri v?i cc tr<Qng hXp th5t b:i ny.
Trong bi ny, ti sc b_ qua t5t c2 cc tr<Qng hXp th5t b:i, n>u m*t trong cc
code th5t b:i x2y ra chng ta sc thot kh_i cu*c g-i v .<a .<Qng truy/n v/
tr:ng thi nghU.
B. Master Receiver mode Master nh]n dP li0u:
Trong ch> .* ny, Master nhAn m*t hoDc m*t sR byte d[ liBu t; m*t
Slave. b1 bMt .Lu, Master t:o ra m*t START condition trn .<Qng SDA,
n>u .<Qng truy/n .ang r2nh, Master sc ti>p tHc pht .i .Sa chU câ Slave cLn
giao ti>p cng v?i bit R (.-c) theo .Snh d:ng nh< sau: SLA+R. N>u Slave
.p l:i bZng m*t ACK trong xung gi[ nhSp thG 9, Master sc bMt .Lu sample
d[ liBu trn SDA. CG sau mYi byte d[ liBu, n>u Master muRn nhAn ti>p byte
khc n ph2i pht ra 1 ACK W xung thG 9 bo cho Slave. Khi Master muRn
k>t thc qu trnh nhAn n sc pht m*t NOT ACK sau khi nhAn d[ liBu, li/n
sau . Master pht STOP .1 k>t thc cu*c g-i hoDc pht .i m*t REPEAT
START n>u n muRn ti>p tHc g-i cc Slaves khc. Hnh 3 m t2 m*t qu
trnh Master nhAn d[ liBu, cc kh2 nKng c th1 x2y ra v gi trS code t<@ng
Gng câ thanh ghi TWSR. ngh\a cc code trong thanh ghi TWSR trong lc
Master truy/n d[ liBu c th1 tham kh2o thm datasheet câ chip.
Ntinside 123

Hnh 3. Master nhAn d[ liBu.
T; hnh 3, trong qu trnh Master nhAn d[ liBu, dy code 0x08 -> 0x40
-> 0x50 -> -> 0x58 l dy code thnh cng nh5t. Code 0x08 bo rZng
START codition .<Xc truy/n thnh cng, code 0x40 bo .Sa chU + R .
.<Xc truy/n thnh cng v . c Slave xc nhAn bZng ACK, code 0x50 bo
d[ liBu .<Xc Master nhAn thnh cng v Master c7ng . pht m*t ACK bit
sau khi nhAn, code 0x58 x2y ra khi Master nhAn d[ liBu thnh cng nh<ng
n khng pht ACK m pht NOT ACK, bo cho Slave rZng Master khng
muRn nhAn thm d[ liBu, ti>p theo Master sc pht m*t STOP condition hoDc
m*t REPEAT START. Cc tr<Qng hXp khc chng ta khng kh2o st.
C. Slave Receiver mode Slave nh]n dP li0u:
Hnh 4 m t2 m*t qu trnh Slave nhAn d[ liBu, cc kh2 nKng c th1 x2y
ra v gi trS code t<@ng Gng câ thanh ghi TWSR. Ch> .* Slave nhAn d[ liBu
Ntinside 124
x2y ra khi Master th`c hiBn m*t cu*c g-i pht d[ liBu (SLA+W). Nh< quan
st trong hnh 4, Slave chU nhAn ra cu*c g-i ny khi .Sa chU câ n trng v?i
.Sa chU câ Master (Own address mode) hoDc khi Master th`c hiBn m*t cu*c
g-i chung. Khi ., bit TWINT câ Slave sc .<Xc set ln 1. N>u Slave cho
php ngMt TWI (bit TWIE trong thanh ghi TWCR .<Xc set t; lc .Lu) th
m*t ngMt x2y ra bo c m*t s` kiBn TWI. N>u code trong thanh ghi TWSR
l 0x60 th m*t cu*c g-i .Sa chU ring .<Xc yu cLu v Slave c7ng . .p
Gng l:i Master bZng m*t ACK, Slave sau . bMt .Lu nhAn d[ liBu t; .<Qng
SDA. CG sau m*t byte d[ liBu Slave ph2i xc nhAn m*t ACK n>u n cn
muRn ti>p tHc nhAn. N>u v m*t l do no . m Slave khng th1 ti>p tHc
nhAn n c th1 pht m*t NOT ACK sau m*t byte d[ liBu. Cu*c g-i k>t thc
khi Slave nhAn .<Xc STOP condition, t<@ng Gng code 0xA0. Cu*c g-i
chung c7ng diIn ra hon ton t<@ng t` cu*c g-i .Sa chU ring nh<ng code c
gi trS khc. Khi vi>t ch<@ng trnh cho Slave trong ch> .* nhAn d[ liBu,
chng ta cLn xt c2 2 tr<Qng hXp cu*c g-i .Sa chU ring v cu*c g-i chung.

Ntinside 125
Hnh 4. Slave nhAn d[ liBu.
D. Slave Transmitter mode Slave truyTn dP li0u:
by l ch> .* cuRi cng trong 4 ch> .* câ AVR TWI. Hnh 5 m t2
m*t qu trnh Slave truy/n d[ liBu, cc kh2 nKng c th1 x2y ra v gi trS code
t<@ng Gng câ thanh ghi TWSR. Ch> .* Slave pht d[ liBu x2y ra khi
Master muRn nhAn d[ liBu t; Slave, Master th`c hiBn m*t cu*c g-i nhAn d[
liBu (SLA+R). Nh< quan st trong hnh 5, Slave chU nhAn ra cu*c g-i ny khi
.Sa chU câ n trng v?i .Sa chU câ Master (Own address mode). Khi ., bit
TWINT câ Slave sc .<Xc set ln 1. N>u Slave .p l:i bZng m*t ACK W
xung nhSp thG 9, code trong thanh ghi TWSR sc l 0xA8, Slave sau . bMt
.Lu pht d[ liBu ln .<Qng SDA. CG sau mYi byte d[ liBu, Master sc xc
nhAn m*t ACK n>u n cn muRn ti>p tHc nhAn, code 0xB8 sc xu5t hiBn
trong tr<Qng hXp ny. N>u Master khng muRn ti>p tHc nhAn d[ liBu t;
Slave, m*t NOT ACK sc .<Xc pht v code 0xC0 xu5t hiBn, Slave k>t thc
qu trnh pht d[ liBu. M*t tr<Qng hXp .Dc biBt khi bit TWEA (bit ACK)
trong thanh ghi TWCR câ Slave .<Xc reset v/ 0 tr<?c khi Slave truy/n d[
liBu, tr<Qng hXp Slave muRn bo rZng n . h>t d[ liBu .1 truy/n, byte ti>p
theo c7ng l byte cuRi cng. Sau khi Master nhAn byte ny, n c th1 xc
nhAn 1 ACK cho Slave (v thAt ra Master khng h/ bi>t Slave .ang truy/n
byte cuRi), code trn Slave trong tr<Qng hXp ny l 0xC8 v Slave sc t` h>t
thc qu trnh truy/n m khng cLn chQ Master. Khi lAp trnh cho Slave
trong ch> .* pht, cLn ph2i c s` th_a hiBp v?i Master tr<?c .1 trnh code
0xC8 v code ny khng c nhi/u ngh\a.
Ntinside 126

Hnh 5. Slave truy/n d[ liBu.
Kg thuAt chnh dng cho Master khi truy/n hay nhAn cu*c g-i l h_i
vng v chQ (polling and waiting). (ng v?i mYi code nhAn v/ t; thanh ghi
TWSR (hay Gng v?i mYi tr:ng thi câ cu*c g-i) m Master set cc bit
t<@ng Gng trong thanh ghi .i/u khi1n TWCR v sau . chQ bit TWINT
.<Xc set (qu trnh k>t thc) .1 ti>p tHc .-c v xt code TWSR. Qu trnh
chQ v xt ny lDp l:i cho .>n khi Master k>t thc cu*c g-i bZng STOP
condition. Tuy nhin Slave th khc, Slave khng ch^ .*ng th`c hiBn cu*c
g-i m n ph2i chQ yu cLu t; Master .1 phHc vH. V th>, n>u dng h_i
vng cho Slave th sc tRn thQi gian chQ v ch v .i khi cn b_ ll cc cu*c
g-i. bRi v?i Slave, ngMt l ph<@ng php bMt cu*c g-i tRi <u nh5t. Trong bi
h-c ny, viBc truy/n v nhAn câ Slave sc .<Xc th`c hiBn trong cc trnh
phHc vH ngMt TWI.
IV. (iTu khiGn AVR TWI.
PhLn ny ti h<?ng dan lAp trnh .i/u khi1n module TWI AVR bZng
WinAVR. Cc hnh 2, 3, 4 v 5 cLn .<Xc tham kh2o km kg v code trong
phLn ny .<Xc pht tri1n t; cc hnh ny. b1 .@n gi2n, chng ta sc vi>t cc
hm giao ti>p TWI trong 1 file ring g-i l myTWI.h, .y c th1 coi l th<
viBn cho TWI dng trong trang web ny. Nh< . trnh by, chu]n I2C th
duy nh5t nh<ng cch sMp x>p d[ liBu câ cc chip I2C th r5t .a d:ng. V th>,
khi muRn giao ti>p v?i m*t chip I2C no b:n nh5t thi>t ph2i .-c datasheet
câ chip . .1 hi1u .Snh d:ng d[ liBu. Cc hm trong th< viBn myTWI chU
Ntinside 127
phHc vH giao ti>p gi[a cc AVR v?i nhau, n>u muRn sC dHng chng giao
chip v?i m*t chip EEPROM 24C1004 chFng h:n, b:n ph2i vi>t thm cc
hm mW r*ng khc dà trn cc hm ny.
N*i dung file myTWI.h .<Xc chia thnh 3 phLn, phLn .Lu l cc .Snh ngh\a
bi>n, tham sR chung, phLn 2 gPm cc hm truy/n/nhAn cho Master v phLn 3
l trnh phHc vH ngMt TWI cho Slave. List 1 trnh by cc .Snh ngh\a chung
trong file myTWI.h.
List 1. bSnh ngh\a chung.
Ntinside 128
Ntinside 129
PhLn ny ch^ y>u .Snh ngh\a cc code tr:ng thi trong qu trnh thao tc
TWI trn AVR m chng ta . bi>t khi kh2o st cc ch> .* ho:t .*ng câ
TWI. ThAt ra b:n c th1 tham kh2o cc hnh 2-5 v cc b2ng code trong
datasheet câ AVR v sC dHng cc code tr:ng thi tr`c ti>p trong lc lAp
trnh, ti .Snh ngh\a nh< trn chU .1 tiBn theo di trong lc lAp trnh. Cc
dng t; 12 .>n 25 .Snh ngh\a cc code tr:ng thi cho Slave (c2 truy/n v
nhAn). Chng ta c7ng .Snh ngh\a m*t sR bi>n ton cHc dng cho Slave, bi>n
SLAVE_wData[100] l m*t m2ng 100 phLn tC dng chGa d[ liBu m Slave
sc truy/n, bi>n Tran_Num l chU sR câ phLn tC trong m2ng SLAVE_wData
sc .<Xc truy/n .i. Bi>n SLAVE_buff[100] l d[ liBu nhAn v/ t; TWI v
Rec_Num l chU sR câ d[ liBu sau cng do TWI nhAn v/ (d[ liBu
SLAVE_buff[Rec_Num]). Bi>n Device_Addr chGa .Sa chU m khi l Slave
câ chnh AVR chng ta .ang lAp trnh. T<@ng t`, cc dng t; 47 .>n 57
.Snh ngh\a code tr:ng thi cho Master mode. Tr<?c ., chng ta c7ng .Snh
ngh\a cc gi trS tRc .* pht xung gi[ nhSp sc gn cho thanh ghi TWBR
(dng 37, 38). Hai bi>n TWI_R v TWI_W .:i diBn cho 2 bit R/W .<Xc
truy/n trong gi .Sa chU (bo cho Slave bi>t Master muRn truy/n hay nhAn
d[ liBu). M*t sR macro trong cc dng 42 .>n 45 bao gPm START, STOP
condition v xa bit TWINT bZng cch gn cc gi trS t<@ng Gng cho thanh
ghi .i/u khi1n TWI.
CuRi cng l ch<@ng trnh con void TWI_Init(void) khWi .*ng TWI.
Qu trnh khWi .*ng bao gPm set tRc .* xung gi[ nhSp cho Master (dng 61,
62), gn .Sa chU device (dng 63) v xc lAp TWI sdn sng W ch> .* Slave.
Xem l:i thanh ghi TWAR, do 7 bit .Sa chU nZm W vS tr cao nn chng ta cLn
ph2i dSch tri .Sa chU 1 vS tr tr<?c khi gn cho TWAR (Device_Addr <<1),
.Png thQi set bit 0 trong TWAR .1 cho php nhAn cu*c g-i chung khi .<Xc
yu cLu. Dng 64 khWi .*ng TWI v?i bit ACK sdn sng v cho php x2y ra
ngMt TWI. Nh< th>, sau khi khWi .*ng TWI sdn sng W ch> .* Slave.
List 2. Code cho Master.
Ntinside 130
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Hm TWI_Master_Send_array(uint8_t Addr, uint8_t Data[], uint8_t
len) th`c hiBn truy/n 1 dy cc byte d[ liBu trong mode Master. Tham sR
Addr l .Sa chU câ Slave cLn giao ti>p, Data[] l m2ng d[ liBu v len l
chi/u di (sR byte) câ d[ liBu cLn truy/n. ViBc .Lu tin khi chng ta vo
Master mode l tMt ngMt TWI bZng cch xa bit TWIE (dng 3). Trnh t`
Master truy/n d[ liBu hon ton t<@ng t` trnh t` trong hnh 2. Dng 5,
TWCR=TWI_START, Master bMt .Lu pht 1 START condition. N>u xem
l:i .Snh ngh\a câ macro TWI_START trong list 1 b:n sc th5y dng
TWCR=TWI_START t<@ng .<@ng
TWCR=(1<<TWINT)|(1<<TWSTA)|(1<<TWEN) tGc chng ta th`c hiBn
xa bit TWINT (bit ny ph2i lun .<Xc xa tr<?c khi muRn th`c hiBn vic
g) bZng cch ghi 1 vo TWINT, set bit START (bit TWSTA) v cho php
TWI ho:t .*ng bZng bit TWEN. Dng code 6 chQ cho .>n khi bit TWINT
.<Xc phLn cGng set ln 1 (k>t thc), sau . chng ta ki1m tra code trong
thanh ghi tr:ng thi TWSR. Ch l chU c 5 bit cao trong thanh ghi TWSR
chGa tr:ng thi nn chng ta cLn dng gi2i thuAt mDt n: che cc bit th5p l:i,
TWSR & 0xF8 chnh l cch .1 che 3 bit th5p câ TWSR. So snh code .-c
.<Xc v?i code t<@ng Gng trong hnh 1, trong tr<Qng hXp ny chng ta so
snh v?i _START_Sent, chnh l so snh v?i 0x80 (xem l:i .Snh ngh\a câ
_START_Sent trong list 1). N>u cc code khng trng nhau, m*t lYi truy/n
x2y ra v chng ta sc thot kh_i ch<@ng trnh truy/n, gi trS tr2 v/ chnh l
code c lYi (xem dng code 7). Cc dng code t; 10 .>n 13 th`c hiBn truy/n
.Sa chU + W, ch trong lc pht, d[ liBu cLn pht ph2i .<Xc ghi sdn vao
thanh ghi d[ liBu TWDR tr<?c khi xa bit TWINT (dng 10 v 11). Sau khi
truy/n .Sa chU chng ta truy/n m2ng d[ liBu lin ti>p v cuRi cng l pht
STOP condition, TWCR=TWI_STOP t<@ng .<@ng
TWCR=(1<<TWINT)|(1<<TWSTO)|(1<<TWEN). CLn khWi .*ng l:i TWI
.1 .<a n v/ ch> .* Slave tr<?c khi thot kh_i ch<@ng trnh con truy/n d[
liBu câ ch> .* Master (dng 24).
Hm TWI_Master_Read_array(uint8_t Addr, uint8_t Data[], uint8_t
len) th`c hiBn nhAn d[ liBu v/ Master. Cch gi2i thch cho hm ny khng
khc nhi/u so v?i hm .-c d[ liBu nn b:n .-c t` tm hi1u. M*t .i1m cLn
ch l khi nhAn 1 dy byte chng ta nn .-c n-1 byte .Lu bnh th<Qng, c
tr2 ACK cho Slave v byte cuRi cng sc .<Xc nhAn ring, tr2 NOT ACK .1
bo cho Slave rZng Master khng muRn nhAn thm(.o:n code t; dng 55
.>n 59 dng .-c byte cuRi cng).
List 3. Code cho Slave.
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Nh< ti . trnh by, ton b* qu trnh truy/n v nhAn câ Slave .<Xc
th<c hiBn trong ch<@ng trnh phHc vH ngMt TWI. Khi ngMt TWI x2y ra, trnh
phHc vH ngMt sc .-c v ki1m tra code trong thanh ghi TWSR .1 th`c hiBn
cc cng viBc ph hXp. B:n .-c l:i tham kh2o thm hnh 4 v hnh 5 cng
v?i cc code trong nh[ng case t<@ng Gng câ List 3 .1 hi1u .o:n ch<@ng
trnh ny. bi1m ln .<Xc dng cho
ch> .* Slave truy/n v nhAn. Ti dng 2 m2ng SLAVE_wData v
SLAVE_buff .1 chGa bi>n truy/n v nhn. Hai bi>n Tran_Num v
Rec_Num l chU sR câ byte hiBn hnh. V th> SLAVE_wData[Tran_Num]
chnh l byte ti>p theo sc .<Xc truy/n .i n>u Slave .<Xc yu cLu truy/n, v
SLAVE_buff[Rec_Num] l byte cuRi cng m Slave nhAn v/ trong ch> .*
Slave nhAn d[ liBu. Hy khi thc cc bi>n ny trong cc ch<@ng trnh Gng
dHng.
b1 minh h-a cho cc sC dHng cc hm trong th< viBn myTWI, ti th`c
hiBn m*t m:ch .iBn m ph_ng m:ng TWI gPm 3 chip ATmega32. Chip thG
nh5t l Master, 2 chip cn l:i l Slaves. Ti t:o 2 Project, m*t cho Master v
m*t cho 2 Slaves dng chung. PORTD .<Xc set input c .iBn trW ko ln.
Ti dng 2 chn PD6 v PD7 .1 ch-n .Sa chU cho 2 Slaves, Slave thG nh5t
ti nRi chn PD6 xuRng GND, do . chip ny c .Sa chU Device_Addr l
PD7:PD6=10=2 (thAp phn). Slave cn l:i ti .1 2 chn PD6 v PD7 trRng
nn .Sa chU câ n l PD7:PD6=11=3. Trong ch<@ng trnh câ Slave c phLn
.-c 2 chn PD6:PD7 v gn cho bi>n Device_Addr m chng ta . khai bo
trong List 1, nh< vAy c th1 dng cc ny .1 set .Sa chU cho Slaves m chng
ta g-i l set .Sa chU cGng. Trn chip Master, m*t swich .<Xc nRi v?i chn
PD0 .1 ch-n Slave cLn giao ti>p, n>u switch .ng th SLAVE c .Sa chU 2
.<Xc ch-n, n>u switch mW th SLAVE c .Sa chU 3 .<Xc ch-n .1 giao ti>p.
M*t nt nh5n .<Xc nRi v?i ngMt INT0 câ chip Master, khi nh5n nt ny
ch<@ng trnh cn .-c d[ liBu t; Slave .<Xc g-i, ty theo switch .ng hay
mW m Slave t<@ng Gng .<Xc g-i .1 gWi d[ liBu cho Master. D[ liBu nhAn v/
sc hi1n thS trn 1 Character LCD. Hnh 6 l s@ .P m:ch .iBn m ph_ng bZng
phLn m/m Proteus v List 4, List 5 lLn l<Xt trnh by .o:n code cho ch<@ng
trnh chnh câ Master v Slave.
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Hnh 6. Demo TWI.
List 4. Ch<@ng trnh chnh cho Master.
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V dH câ Master minh h-a cch dng 2 hm Master truy/n v nhAn
m2ng d[ liBu. % dng 27 ti dng hm TWI_Master_Send_array .1 gWi 40
phLn tC câ m2ng Data .>n Slave c .Sa chU 2,
TWI_Master_Send_array(2,Data,40). T<@ng t`, dng 31 gWi 50 phLn tC câ
m2ng Data .>n Slave c .Sa chU 3. Khi button trn m:ch m ph_ng .<Xc
nh5n, ngMt INT0 x2y ra, trong trnh phHc vH ngMt INT0 chng ta dng hm
TWI_Master_Read_array .1 .-c d[ liBu t; m*t trong 2 Slaves, xem dng
code 43: TWI_Master_Read_array(Slave_Addr,rData,1). bSa chU câ Slave
cLn .-c sc do switch nRi v?i chn PD0 quy>t .Snh (xem dng 42). bSa chU
câ Slave .ang giao ti>p sc hi1n thS trn dng 1 câ LCD, d[ liBu .<Xc hi1n
thS trn dng 2.
List 5. Ch<@ng trnh chnh cho Slaves.
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Ch<@ng trnh demo câ Slaves minh h-a cc ch> .* Slave truy/n v nhAn d[ liBu.
Tuy nhin do cc qu trnh truy/n v nhAn d[ liBu câ Slave .<Xc th`c hiBn trong trnh
phHc vH ngMt TWI .<Xc vi>t sdn trong file myTWI.h. trong ch<@ng trnh chnh câ Slave
chng ta khng cLn ph2i g-i b5t kN hm no trong myTWI. Cng viBc cLn lm trong
ch<@ng trnh demo cho Slave l khWi .*ng TWI sau . gn gi trS cho cc bi>n ton cHc
câ Slave (dng 21 gn gi trS cho m2ng SLAVE_wData).
Ti c .nh km v dH demo cho TWI, ti th`c hiBn 2 Projetc trong 2 th< mHc: TWI1
cho AMster v TWI2 cho Slave. b1 ch:y demo, ch:y file TWI bZng Proteus, dng switch
SW1 .1 ch-n Slave cLn giao ti>p, nh5n button .1 nhAn d[ liBu t; Slave. Thay .ei vS tr
switch v ki1m tra k>t qu2.
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KeyPad

I. Keypad 4x4.
Keypad l m*t "thi>t bS nhAp" chGa cc nt nh5n cho php ng<Qi dng
nhAp cc ch[ sR, ch[ ci hoDc k hiBu vo b* .i/u khi1n. Keypad khng
chGa t5t c2 b2ng m ASCII nh< keyboard v v th> keypad th<Qng .<Xc tm
th5y trong cc thi>t bS chuyn dHng. Cc nt nh5n trn cc my tnh .iBn tC
cLm tay l m*t v dH v/ keypad. SR l<Xng nt nh5n câ m*t keypad thay .ei
phH thu*c vo yu cLu Gng dHng. Trong bi ny ti gi?i thiBu cch .i/u
khi1n câ m*t lo:i keypad .@n gi2n, keypad 4x4.
G-i l keypad 4x4 v keypad ny c 16 nt nh5n .<Xc bR tr d:ng ma
trAn 4 hng v 4 c*t. Cch bR tr ma trAn hng v c*t l cch chung m cc
keypad sC dHng. C7ng giRng nh< cc ma trAn LED, cc nt nh5n cng hng
v cng c*t .<Xc nRi v?i nhau, v th> v?i keypad 4x4 sc c teng c*ng 8 ng
ra (4 hng v 4 c*t). M hnh Keypad 4x4 .<Xc th1 hiBn trong hnh 1.

a) b)
Hnh 1. Keypad 4x4.
Hnh 1b l m hnh thAt câ 1 keypad 4x4 v hnh 1a l c5u hnh bn trong câ n. BRn hng câ keypad .<Xc
.nh d5u l A, B, C v D trong khi 4 c*t .<Xc g-i l 1, 2, 3 v 4.
Ho3t =Dng c?a keypad: Gi2 sC nht '2' .<Xc nh5n, khi . .<Qng C v 2 .<Xc nRi v?i nhau. Gi2 sC .<Qng 2
.<Xc nRi v?i GND (mass, 0V) th C c7ng sc l GND. Tuy nhin, cu h_i .Dt ra l bZng cch ki1m tra tr:ng thi
.<Qng C chng ta sc c k>t luAn nt '2' .<Xc nh5n? Gi2 sC t5t c2 cc .<Qng 1, 2, 3, 4 ./u n?i v?i GND, n>u C=
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GND th r rng chng ta khng th1 k>t luAn nt '1',= hay nt '2' hay nt '3' hay nt '-' .<Xc nh5n. Kg thuAt .1
khMc phHc v5n ./ ny chnh l kg thuAt "qut" keypad. Kg thuAt qut keypad bZng AVR .<Xc trnh by nh< sau:
- NRi t5t c2 8 chn câ keypad v?i 1 PORT câ AVR, v dH PORTB theo thG t` bn d<?i:

- Cc chn 1, 2, 3, 4 .<Xc set nh< cc chn Output v gi[ W mGc cao, cc chn A, B, C, D l Input v c .iBn
trW ko ln.L>n l9Wt ko chn 1, 2, 3, 4 xuRng th5p (lLn l<Xt xu5t gi trS 0 ra t;ng chn), .-c tr:ng thi cc chn
A, B, C, D .1 k>t luAn nt no .<Xc nh5n. V dH nh< trong hnh 1, nt '2' .<Xc nh5n th qu trnh qut sc cho k>t
qu2 nh< sau:
B<?c 1: ko chn 1 xuRng 0 (cc chn 2,3,4 van W mGc cao), ki1m tra 4 chn A, B, C, D thu .<Xc k>t
qu2 D=1, C=1, B=1, A=1. (gi trS .-c v/ câ PINB l 00001111 nhS phn)
B<?c 2: ko chn 2 xuRng 0, ki1m tra l:i A, B, C, D, k>t qu2 thu .<Xc D=1, C=0, B=1, A=1 (gi trS .-c
v/ câ PINB l 0b00001011 nhS phn). Chn C=0 tGc c 1 nt W hng thG 3 .<Xc nh5n, chng ta l:i .ang W B9-c
thO 2 tGc nt nh5n thu*c c*t thG 2. Chng ta c th1 d;ng qu trnh qut t:i .y v k>t qu2 thu v/ nt W hng 3,
c*t 2 (tGc nut '2' .<Xc) .<Xc nh5n.
Qu trnh qut cho cc nt khc c7ng x2y ra t<@ng t`. Ch , n>u c 1 nt no . .<Xc nh5n th c 4 kh2 nKng
c th1 .-c v/ t; 4 A,B,C,D . l:
D=1, C=1, B=1, A=0: nt W hng A .<Xc nh5n, gi trS .-c v/ l 0x0E (cc .<Qng A,B,C,D .<Xc nRi
v?i 4 bit th5p câ PORT trn AVR).
D=1, C=1, B=0, A=1: nt W hng B .<Xc nh5n, gi trS .-c v/ l 0x0D .
D=1, C=0, B=1, A=1: nt W hng C .<Xc nh5n, gi trS .-c v/ l 0x0B .
D=0, C=1, B=1, A=1: nt W hng D .<Xc nh5n, gi trS .-c v/ l 0x07 .
b1 tiBn lXi khi so snh k>t qu2 .-c v/, khi lAp trnh .-c keypad chng ta nn lAp 1 m2ng 4 phLn tC chGa 4 sR
c th1 .-c v/ t; keypad. V dH uint8_t scan_code[4]={0x0E,0x0D,0x0B,0x07};
Trong phLn ti>p theo chng ta sc kh2o st cch .-c keypad 4x4 bZng 1 chip AVR Atmega32.
II. (Rc Keypad 4x4 bMng AVR.
Chng ta sc m ph_ng cch .-c v hi1n thS gi trS t; keypad 4x4 bZng
phLn mm Proteus. Cc m .-c .<Xc t; keypad sc hiIn thS ln 1 Text LCD
16x2. Th< viBn myLCD.h .<Xc dng .1 hi1n thS ln LCD (xem l:i bi Text
LCD). M:ch .iBn m ph_ng th1 hiBn trong hnh 2.
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Hnh 2. b-c v hi1n thS t; Keypad 4x4.
Hy t:o 1 Project bZng WinAVR v?i tn g-i KEYPAD, t:o file main.c
v add vo Project, t:o Makefile, .Png thQi copy file myLCD.h t; bi h-c
Text LCD vo th< mHc chGa Project KEYPAD. MW file myLCD.h v sCa
phLn khai bo PORT nh< List0.
List 0. Khai bo PORT trong file myLCD.h
01
02
03
04
05
....
#define CTRL PORTC
#define DDR_CTRL DDRC
#define DATA_O PORTC
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06
07
08
#define DATA_I PINC
#define DDR_DATA DDRC
....
Vi>t .o:n code trong List1 vo file main.c
List 1. N*i dung file main.c
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% dng 3 chng ta include file myLCD.h .1 sC dHng cc hm thao tc Text LCD. Trong cc dng 5, 6 v 7
chng ta .Snh ngh\a PORT giao ti>p v?i Keypad, theo . PORTB .<Xc dng cho Keypad. Dng 9 khai bo m*t
m2ng 4 phLn tC chGa m .-c v/ t; Keypad nh< . th2o luAn trong phLn trn. Cc dng code t; 10 .>n 13 khai
bo m*t m2ng 2 chi/u c 16 phLn tC chGa m ASCII câ cc k t` .:i diBn cho cc Button, ti sMp x>p cc k t`
d:ng ma trAn .1 dI dng t<@ng Gng v?i cc nt trn keypad. Dng 14 khai bo bi>n key lo:i 8 bit khng d5u, .y
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l bi>n chGa m ascii khi .-c keypad. Dng 15 khai bo hm qut Keypad c tn checkpad(). T5t c2 gi2i thuAt
qut v .-c keypad ./u nKm trong hm ny, gi trS tr2 v/ câ hm l m ascii câ nt .<Xc nh5n.
Tr<?c khi kh2o st .o:n code trong ch<@ng trnh main, chng ta sc tm hi1u ch<@ng trnh con checkpad(). %
dng 31 trong ch<@ng trnh con checkpad, chng ta khai bo 3 bi>n phH 8 bit khng d5u, i l bi>n .:i diBn cho
c*t câ keypad v j l hng, keyin l gi trS .-c v/ t; cc chn A, B, C, D. Vng lDp for 4 lLn trong dng 32 câ
bi>n i chnh l 4 b<?c qut m ti . trnh by trong v dH trn. % b<?c 1, bi>n i=0, n>u chng ta dSch tri sR 1
nh< (1<<(4+i)) th gi trS thu .<Xc l (1<<(4+i))=0b00010000, k>t hXp v?i dng code
33: KEYPAD_PORT=0xFF-(1<<(4+i)); chng ta thu .<Xc KEYPAD_PORT=0xEF. SR 4 trong php dSch xu5t
hiBn v cc c*t câ Keypad .<Xc nRi v?i 4 bit cao câ PORT trn AVR. Tm l:i, sau b<?c .Lu tin c*t thG nh5t
câ Keypad .<Xc ko xuRng mGc 0, sdn sng cho qu trnh ki1m tra cc hng A,B,C,D trong cc dng ti>p theo.
Dng 35 .-c gi trS t; Keypad v/ bi>n keyin, v chng ta k>t nRi cc chn A,B,C,D câ Keypad v?i 4 bit th5p
câ PORT nn chng ta chU quan tm .>n gi trS câ 4 bit th5p ny, viBc AND (&) gi trS .-c v/ v?i 0x0F cho
php chng ta b_ qua 4 bit cao. Trong dng 36, chng ta ki1m tra xem n>u gi trS .-c v/ khc 0x0F th th`c hiBn
cc dng ti>p theo. N>u keyin =0x0F ngh\a l khng c b5t kN nt no trn c*t 1 .<Xc nh5n, cc dng ti>p theo
khng th`c hiBn, vng lDp for cho bi>n i .<Xc ti>p tHc gi trS ti>p theo. N>u bi>n keyin khc 0x0F th chng ta
bi>t rZng c 1 nt no . trn c*t i .<Xc nh5n, cc dng ti>p theo sc xc .Snh chnh xc nt no .<Xc nh5n. Dng
37 cho bi>n hng j ch:y t; 0 .>n 4, dng 38 ki1m tra gi trS keyin, n>u keyin bZng phLn tC thG j trong m2ng
scan_code m chng ta . .Snh ngh\a tr<?c . th nt trn hng j . .<Xc nh5n, tm l:i nt .<Xc nh5n l nt
hng j v c*t i, chng ta tr2 v/ gi trS m ascii câ nt ny bZng cch l5y gi trS t<@ng Gng câ m2ng ascii_code
.<Xc .Snh ngh\a tr<?c .: return ascii_code[j][i]. N>u qu trnh qut th5t b:i chng ta tr2 v/ gi trS 0.
N*i dung câ ch<@ng trnh chnh l khWi .*ng chip v th`c hiBn demo qu trnh .-c Keypad, Dng 19 chng
ta khai bo sC dHng 4 bit th5p câ KEYPAD_PORT lm input (cc chn A,B,C,D l input) v 4 bit cao lm
output. Dng 18 khWi .*ng cc .iBn trW ko ln cho 4 bit th5p. Hai dng 21 v 22 khWi .*ng v xa Text LCD.
Trong vng lDp v tAn while(1), chng ta qut keypad W dng 24 v hi1n thS ln LCD W dng 25 (chU hi1n thS n>u
qu trnh qut thnh cng).
Trong v dH ny ti chU trnh by gi2i thuAt qut Keypad c@ b2n, van cn m*t sR v5n ./ khc nh< ki1m tra s`
kiBn nh5n (key down), th2 (key up)...b:n .-c hy t` gi2i tuy>t theo cch câ ring mnh.

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Text LCD

Bi ny nZm trong phLn Gng dHng AVR thu*c lo:t bi cng h-c AVR.
Trong bi Gng dHng ny chng ta khng kh2o st nhi/u c5u trc AVR m
ch^ y>u l tm hi1u Text LCD cch .i/u khi1n bZng AVR. Cng cH chnh
c7ng l 2 b* phLn m/m quen thu*c WinAVR v Proteus.
- C5u trc Text LCD.
- Nguyn l ho:t .*ng Text LCD
- Pht tri1n 1 th< viBn .i/u khi1n Text LCD bZng AVR c2 2 ch> .* 8 bit
v 4 bit.
- V dH .i/u khi1n Text LCD bZng AVR.
II. Text LCD.
Text LCD l cc lo:i mn hnh tinh th1 l_ng nh_ dng .1 hi1n thS cc
dng ch[ hoDc sR trong b2ng m ASCII. Khng giRng cc lo:i LCD l?n,
Text LCD .<Xc chia sdn thnh t;ng v Gng v?i mYi chU c th1 hi1n thS
m*t k t` ASCII. C7ng v l do chU hiBn thS .<Xc k t` ASCII nn lo:i LCD
ny .<Xc g-i l Text LCD (.1 phn biBt v?i Graphic LCD c th1 hi1n thS
hnh 2nh). MYi câ Text LCD bao gPm cc ch5m tinh th1 l_ng, viBc k>t
hXp ]n v hiBn cc ch5m ny sc t:o thnh m*t k t` cLn hi1n thS. Trong
cc Text LCD, cc mau k t` .<Xc .Snh ngh\a sdn v th> viBc .i/u khi1n
Text LCD sc t<@ng .Ri dI dng h@n cc graphic LCD. Kch th<?c câ Text
LCD .<Xc .Snh ngh\a bZng sR k t` c th1 hi1n thS trn 1 dng v teng sR
dng m LCD c. V dH LCD 16x2 l lo:i c 2 dng v mYi dng c th1
hi1n thS tRi .a 16 k t`. M*t sR kch th<?c Text LCD thng th<Qng gPm
16x1, 16x2, 16x4, 20x2, 20x4Hnh 1 l m*t v dH Text LCD 16x2.
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Hnh 1. Text LCD 16x2.
Text LCD c 2 cch giao ti>p c@ b2n l nRi ti>p (nh< I2C) v song song.
Trong ph:m vi bi h-c ny ti chU gi?i thiBu lo:i giao ti>p song song, cH th1
l LCD 16x2 .i/u khi1n bWi chip HD44780U câ hng Hitachi. bRi v?i cc
LCD khc b:n cLn tham kh2o datasheet ring câ t;ng lo:i. Tuy nhin,
HD44780U c7ng .<Xc coi l chu]n chung cho cc lo:i Text LCD, v th> b:n
c th1 dng ch<@ng trnh v dH trong bi ny .1 test trn cc LCD khc v?i
r5t t hoDc khng cLn chUnh sCa.
HD44780U l b* .i/u khi1n cho cc Text LCD d:ng ma trAn .i1m (dot-
matrix), chip ny c th1 .<Xc dng cho cc LCD c 1 hoDc 2 dng hi1n thS.
HD44780U c 2 mode giao ti>p l 4 bit v 8 bit. N chGa sdn 208 k t` mau
kch th<?c font 5x8 v 32 k t` mau font 5x10 (teng c*ng l 240 k t` mau
khc nhau).
1. S. =V chn.

Cc Text LCD theo chu]n HD44780U th<Qng c 16 chn trong . 14
chn k>t nRi v?i b* .i/u khi1n v 2 chn nguPn cho .n LED n/n. ThG t`
cc chn th<Qng .<Xc sMp x>p nh< sau:
B2ng 1. S@ .P chn.
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Trong m*t sR LCD 2 chn LED n/n .<Xc .nh sR 15 v 16 nh<ng trong
m*t sR tr<Qng hXp 2 chn ny .<Xc ghi l A (Anode) v K (Cathode). Hnh
2 m t2 cch k>t nRi LCD v?i nguPn v m:ch .i/u khi1n.
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Hnh 2. K>t nRi Text LCD.
Chn 1 v chn 2 l cc chn nguPn, .<Xc nRi v?i GND v nguPn 5V.
Chn 3 l chn chUnh .* t<@ng ph2n (contrast), chn ny cLn .<Xc nRi v?i 1
bi>n trW chia p nh< trong hnh 2.Trong khi ho:t .*ng, chUnh .1 thay .ei gi
trS bi>n trW .1 .:t .<Xc .* t<@ng ph2n cLn thi>t, sau . gi[ mGc bi>n trW
ny. Cc chn .i/u khi1n RS, R/W, EN v cc .<Qng d[ liBu .<Xc nRi tr`c
ti>p v?i vi .i/u khi1n. Ty theo ch> .* ho:t .*ng 4 bit hay 8 bit m cc chn
t; D0 .>n D3 c th1 b_ qua hoDc nRi v?i vi .i/u khi1n, chng ta sc kh2o st
kg cng h@n trong cc phLn sau.
2. Thanh ghi v tK chOc bD nh-.
HD44780U c 2 thanh ghi 8 bits l INSTRUCTION REGISTER (IR) v
DATA REGISTER (DR). Thanh ghi IR chGa m lBnh .i/u khi1n LCD v l
thanh ghi chU ghi (chU c th1 ghi vo thanh ghi ny m khng .-c .<Xc
n). Thanh ghi DR chGa cc cc lo:i d[ liBu nh< k t` cLn hi1n thS hoDc d[
liBu .-c ra t; b* nh? LCDC2 2 thanh ghi ./u .<Xc nRi v?i cc .<Qng d[
liBu D0:7 câ Text LCD v .<Xc là ch-n ty theo cc chn .i/u khi1n RS,
RW. Th`c t> .1 .i/u khi1n Text LCD chng ta khng cLn quan tm .>n
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cch thGc ho:t .*ng câ 2 thanh ghi ny, v th> c7ng khng cLn kh2o st chi
ti>t chng.
HD44780U c 3 lo:i b* nh?, . l b* nh? RAM d[ liBu cLn hi1n thS
DDRAM (Didplay Data RAM), b* nh? chGa ROM chGa b* font t:o ra k t`
CGROM (Character Generator ROM) v b* nh? RAM chGa b* font t:o ra
cc symbol ty ch-n CGRAM (Character Generator RAM). b1 .i/u khi1n
hi1n thS Text LCD chng ta cLn hi1u te chGc v cch thGc ho:t .*ng câ cc
b* nh? ny:
2.1 DDRAM.
DDRAM l b* nh? t:m chGa cc k t` cLn hi1n thS ln LCD, b* nh?
ny gPm c 80 .<Xc chia thnh 2 hng, mYi c .* r*ng 8 bit v .<Xc
.nh sR t; 0 .>n 39 cho dng 1; t; 64 .>n 103 cho dng 2. MYi nh? t<@ng
Gng v?i 1 trn mn hnh LCD. Nh< chng ta bi>t LCD lo:i 16x2 c th1
hi1n thS tRi .a 32 k t` (c 32 hi1n thS), v th> c m*t sR nh? câ
DDRAM khng .<Xc sC dHng lm cc hi1n thS. b1 hi1u r h@n chng ta
tham kh2o hnh 3 bn d<?i
Hnh 3. Te chGc câ DDRAM.
ChU c 16 nh? c .Sa chU t; 0 .>n 15 v 16 .Sa chU t; 64 .>n 79 l
.<Xc hi1n thS trn LCD. V th> muRn hi1n thS m*t k t` no . trn LCD
chng ta cLn vi>t k t` . vo DDRAM W 1 trong 32 .Sa chU trn. Cc k t`
nZm ngoi 32 nh? trn sc khng .<Xc hi1n thS, tuy nhin van khng bS m5t
.i, chng c th1 .<Xc dng cho cc mHc .ch khc n>u cLn thi>t.
2.2 CGROM.
CGROM l vng nh? cR .Snh chGa .Snh ngh\a font cho cc k t`.
Chng ta khng tr`c ti>p truy xu5t vng nh? ny m chip HD44780U sc t`
th`c hiBn khi c yu cLu .-c font .1 hiBn thS. M*t .i/u .ng l<u l .Sa chU
font câ mYi k t` vng nh? CGROM chnh l m ASCII câ k t` .. V
dH k t` a c m ASCII l 97, tham kh2o te chGc câ vng nh? CGROM
trong hnh 4 b:n sc nhAn th5y .Sa chU font câ a c 4 bit th5p l 0001 v 4
bit cao l 0110, .Sa chU teng hXp l 01100001 = 97.
CGROM v DDRAM .<Xc t` .*ng phRi hXp trong qu trnh hi1n thS
câ LCD. Gi2 sC chng ta muRn hi1n thS k t` a t:i vS tr .Lu tin, dng thG
2 câ LCD th cc b<?c th`c hiBn sc nh< sau: tr<?c h>t chng ta bi>t rZng vS
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tr .Lu tin câ dng 2 c .Sa chU l 64 trong b* nh? DDRAM (xem hnh 3),
v th> chng ta sc ghi vo nh? c .Sa chU 64 m*t gi trS l 97 (m ASCII
câ k t` a). Ti>p theo, chip HD44780U .-c gi trS 97 ny v coi nh< l
.Sa chU câ vng nh? CGROM, n sc tm .>n vng nh? CGROM c .Sa chU
97 v .-c b2ng font . .<Xc .Snh ngh\a sdn W .y, sau . xu5t b2n font ny
ra cc ch5m trn mn hnh LCD t:i vS tr .Lu tin câ dng 2 trn LCD.
by chnh l cch m 2 b* nh? DDRAM v CGROM phRi hXp v?i nhau .1
hi1n thS cc k t`. Nh< m t2, cng viBc câ ng<Qi lAp trnh .i/u khi1n LCD
t<@ng .Ri .@n gi2n, . l vi>t m ASCII vo b* nh? DDRAM t:i .ng vS tr
.<Xc yu cLu, b<?c ti>p theo sc do HD44780U .2m nhiBm.
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Hnh 4. Vng nh? CGROM.
2.3 CGRAM.
CGRAM l vng nh? chGa cc symbol do ng<Qi dng t` .Snh ngh\a,
mYi symbol .<Xc c kch th<?c 5x8 v .<Xc dnh cho 8 nh? 8 bit. Cc
symbol th<Qng .<Xc .Snh ngh\a tr<?c v .<Xc g-i hi1n thS khi cLn thi>t.
Vng ny c t5t c2 64 nh? nn c tRi .a 8 symbol c th1 .<Xc .Snh ngh\a.
Ti liBu ny khng ./ cAp .>n sC dHng b* nh? CGRAM nn ti sc khng .i
chi ti>t phLn ny, b:n c th1 tham kh2o datasheet câ HD44780U .1 bi>t
thm.
3. (iTu khiGn hiGn th7 Text LCD.
3.1 Cc chn $i7u khi;n LCD.
Cc chn .i/u khi1n viBc .-c v ghi LCD bao gPm RS, R/W v EN.
RS (chn sR 3): Chn là ch-n thanh ghi (Select Register), chn ny cho
php là ch-n 1 trong 2 thanh ghi IR hoDc DR .1 lm viBc. V c2 2 thanh ghi
ny ./u .<Xc k>t nRi v?i cc chn Data câ LCD nn cLn 1 bit .1 là ch-n
gi[a chng. N>u RS=0, thanh ghi IR .<Xc ch-n v n>u RS=1 thanh ghi DR
.<Xc ch-n. Chng ta ./u bi>t thanh ghi IR l thanh ghi chGa m lBnh cho
LCD, v th> n>u muRn gWi 1 m lBnh .>n LCD th chn RS ph2i .<Xc reset
v/ 0. Ng<Xc l:i, khi muRn ghi m ASCII câ k t` cLn hi1n thS ln LCD th
chng ta sc set RS=1 .1 ch-n thanh ghi DR. Ho:t .*ng câ chn RS .<Xc
m t2 trong hnh 5.

Hnh 5. Ho:t .*ng câ chn RS.
R/W (chn sR 4): Chn là ch-n gi[a viBc .-c v ghi. N>u R/W=0 th
d[ liBu sc .<Xc ghi t; b* .i/u khi1n ngoi (vi .i/u khi1n AVR chFng h:n)
vo LCD. N>u R/W=1 th d[ liBu sc .<Xc .-c t; LCD ra ngoi. Tuy nhin,
chU c duy nh5t 1 tr<Qng hXp m d[ liBu c th1 .-c t; LCD ra, . l .-c
tr:ng thi LCD .1 bi>t LCD c .ang bAn hay khng (cQ Busy Flag - BF). Do
LCD l m*t thi>t bS ho:t .*ng t<@ng .Ri chAm (so v?i vi .i/u khi1n), v th>
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m*t cQ BF .<Xc dng .1 bo LCD .ang bAn, n>u BF=1 th chng ta ph2i
chQ cho LCD xC l xong nhiBm vH hiBn t:i, .>n khi no BF=0 m*t thao tc
m?i sc .<Xc gn cho LCD. V th>, khi lm viBc v?i Text LCD chng ta nh5t
thi>t ph2i c m*t ch<@ng trnh con t:m g-i l wait_LCD .1 chQ cho .>n khi
LCD r2nh. C 2 cch .1 vi>t ch<@ng trnh wait_LCD. Cch 1 l .-c bit BF
v/ ki1m tra v chQ BF=0, cch ny .i h_i lBnh .-c t; LCD v/ b* .i/u
khi1n ngoi, do . chn R/W cLn .<Xc nRi v?i b* .i/u khi1n ngoi. Cch 2
l vi>t m*t hm delay m*t kho2ng thQi gian cR .Snh no . (tRt nh5t l trn
1ms). u .i1m câ cch 2 l s` .@n gi2n v khng cLn .-c LCD, do . chn
R/W khng cLn sC dHng v lun .<Xc nRi v?i GND. Tuy nhin, nh<Xc .i1m
câ cch 2 l kho2ng thQi gian delay cR .Snh n>u qu l?n sc lm chAm qu
trnh thao tc LCD, n>u qu nh_ sc gy ra lYi hi1n thS. Trong bi ny ti
h<?ng dan b:n cch teng qut l cch 1, .1 sC dHng cch 2 b:n chU cLn m*t
thay .ei nh_ trong ch<@ng trnh wait_LCD (sc trnh by chi ti>t sau) v k>t
nRi chn R/W câ LCD xuRng GND.
EN (chn sR 5): Chn cho php LCD ho:t .*ng (Enable), chn ny cLn
.<Xc k>t nRi v?i b* .i/u khi1n .1 cho php thao tc LCD. b1 .-c v ghi
data t; LCD chng ta cLn t:o m*t xung c:nh xuRng trn chn EN, ni
theo cch khc, muRn ghi d[ liBu vo LCD tr<?c h>t cLn .2m b2o rZng chn
EN=0, ti>p .>n xu5t d[ liBu .>n cc chn D0:7, sau . set chn EN ln 1 v
cuRi cng l xa EN v/ 0 .1 t:o 1 xung c:nh xuRng.
3.2 T:p l/nh c=a LCD.
B2ng 2 tm tMt cc lBnh c th1 ghi vo LCD
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Danh sch lBnh trn .<Xc ti t 2 mu khc nhau, cc lBnh mu ._ sc
.<Xc dng th<Qng xuyn trong lc hi1n thS LCD v cc lBnh mu xanh
th<Qng chU .<Xc dng 1 lLn trong lc khWi .*ng LCD, ring lBnh Read BF
c th1 .<Xc dng hoDc khng ty theo cch vi>t ch<@ng trnh wait_LCD.
PhLn ti>p theo ti gi2i thch ngh\ câ cc lBnh v tham sR km theo chng.
Tr<?c h>t l nhm lBnh ._:
- Clear display xa LCD: lBnh ny xa ton b* n*i dung DDRAM v
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v th> xa ton b* hi1n thS trn LCD. V .y l 1 lBnh ghi Instruction nn
chn RS ph2i .<Xc reset v/ 0 tr<?c khi ghi lBnh ny ln LCD. M lBnh xa
LCD l 0x01(ghi vo D0:D7).
- Cursor home .<a con tr_ v/ vS tr .Lu, dng 1 câ LCD: lBnh ny
th`c hiBn viBc .<a con tr_ v/ vS tr .Lu tin câ b* nh? DDRAM, v th> n>u
sau lBnh ny m*t bi>n .<Xc ghi vo DDRAM th bi>n ny sc nZm W vS tr
.Lu tin (1;1). RS c7ng ph2i bZng 0 tr<?c khi ghi lBnh. M lBnh l 0x02 hoDc
0x03(ch-n 1 trong 2 m lBnh, ty ).
- Set DDRAM address .Snh vS tr con tr_ cho DDRAM: di chuy1n con
tr_ .>n m*t vS tr ty trong DDRAM v v th> c th1 .<Xc dng .1 ch-n vS
tr cLn hi1n thS trn LCD. b1 th`c hiBn lBnh ny cLn reset RS=0. Bit MSB
câ m lBnh (D7) ph2i bZng 1, 7 bit cn l:i câ m lBnh chnh l .Sa chU
DDRAM muRn di chuy1n .>n. V dH chng ta muRn di chuy1n con tr_ .>n
vS tr thG 3 trn dng 2 câ LCD (.Sa chU 42) chng ta cLn ghi m lBnh 0xAA
v 0xAA=10101010 (binary) trong . bit MSB bZng 1, b2y bit cn l:i l
0101010=42, .Sa chU câ nh? muRn .>n.
- Write to CGRAM or DDRAM ghi d[ liBu vo CGRAM hoDc
DDRAM: v .y khng ph2i l lBnh ghi instruction m l 1 lBnh ghi d[ liBu
nn chn RS cLn .<Xc set ln 1 tr<?c khi ghi lBnh vo LCD. LBnh ny cho
php ghi m ASCII câ m*t k t` cLn hi1n thS vo thanh ghi DDRAM.
Tr<Qng hXp ghi vo CGRAM khng .<Xc kh2o st.
K> .>n l nhm lBnh mu xanh: nhm lBnh ny th<Qng chU th`c hiBn 1
lLn (t nh5t l trong bi h-c ny) v th<Qng .<Xc vi>t chung trong 1 ch<@ng
trnh con khWi .*ng LCD ( chng ta g-i l init_LCD trong bi h-c ny).
- Entry mode set xc lAp cc hiBn thS lin ti>p cho LCD: ni m*t cch
dI hi1u, lBnh ny chU ra cch m b:n muRn hi1n thS m*t k t` ti>p theo 1 k
t` tr<?c .. V dH n>u b:n muRn hiBn thS 2 k t` lin ti>p AB, tr<?c h>t b:n
vi>t A t:i vS tr 5, dng 1. Sau . b:n ghi B vo LCD, lc ny c 4 cch m
LCD c th1 hi1n thS B nh< sau: hi1n thS B bn ph2i A t:i vS tr sR 6 (cch 1);
B c7ng c th1 .<Xc hi1n thS bn tri A, t:i vS tr sR 4(cch 2); hoDc LCD c
th1 t` dSch chuy1n A v/ bn tri .>n vS tr 4 sau . hi1n thS B bn ph2i A, t:i
vS tr 5(cch 3); v kh2 nKng cuRi cng l LCD dSch chuy1n A v/ bn ph2i
.>n vS tr 6 sau . hi1n thS B bn tri A, t:i vS tr 5(cch 4). Chng ta c th1
ch-n 1 trong 4 cch hi1n thS trn thng qua lBnh Entry mode set. by l lBnh
ghi Instruction nn RS=0, 5 bit cao D7:3=00000, bit D2=1, hai bit cn l:i
D1:0 chGa m lBnh .1 là ch-n 1 trong 4 cch hi1n thS. Xem l:i b2ng 2, bit
D1 chGa gi trS I/D v D0 chGa S. Trong . I/D ngh\a l tKng hoDc gi2m
(Increment or Decrement). I/D= 1 l hi1n thS tKng tGc k t` sau sc hi1n thS
bn ph2i k t` tr<?c, n>u I/D=0 th hi1n thS gi2m, tGc k t` sau hi1n thS bn
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tri k t` tr<?c. S l gi trS Shift, n>u S=1 th cc k t` tr<?c . sc .<Xc
.]y .i, k t` sau chi>m chY k t` tr<?c, ng<Xc l:i n>u S=0 th vS tr hi1n
thS câ cc k t` tr<?c . khng thay .ei. C th1 tm tMt 4 mode hi1n thS
Gng v?i 4 m lBnh nh< sau:
+ D7:0 = 0x04 (00000100) : hi1n thS gi2m v khng shift (nh< cch
2 trong v dH).
+ D7:0 = 0x05 (00000101) : hi1n thS gi2m v shift (nh< cch 4 trong v
dH).
+ D7:0 = 0x06 (00000110) : hi1n thS tKng v khng shift (nh< cch
1, khuyQn khch).
+ D7:0 = 0x07 (00000111) : hi1n thS tKng v shift (nh< cch 3 trong v
dH).
- Display on/off control xc lAp cch hiBn thS cho LCD: lBnh ny bao
gPm cc thng sR cho php LCD hi1n thS, cho php hi1n thS cursor v mW/tMt
blinking. by c7ng l m*t lBnh ghi Instrcution nn RS ph2i bZng 0. M lBnh
cho lBnh ny c d:ng 00001DCB trong . D (Display) cho php hi1n thS
LCD n>u mang gi trS 1, C (Cursor) bZng 1 th cursor sc .<Xc hi1n thS v B
l blinking cho cursor t:i vS tr hi1n thS (blinking l d:ng 1 .en nh5p nhy
t:i vS tr k t` .ang hi1n thS). M lBnh .<Xc dng phe bi>n cho lBnh ny l
0x0E (00001110 - hi1n thS cursor nh<ng khng hi1n thS blinking).
- Function set xc lAp chGc nKng cho LCD: .y l lBnh thi>t lAp
ph<@ng thGc giao ti>p v?i LCD, kch th<?c font ch[ v sR l<Xng line câ
LCD. RS c7ng ph2i bZng 0 khi sC dHng lBnh ny. M lBnh function set c
d:ng 001DLNFxx. Trong . n>u DL=1 (DL: Data Length) th mode giao
ti>p 8 bit sc .<Xc dng, lc ny t5t c2 cc chn t; D0 .>n D7 ph2i .<Xc k>t
nRi v?i b* .i/u khi1n ngoi. N>u DL=0 th mode 4 bit .<Xc dng, trong
tr<Qng hXp ny chU c 4 chn D4:7 .<Xc dng .1 truy/n nhAn d[ liBu v k>t
nRi v?i b* .i/u khi1n ngoi, cc chn D0:3 .<Xc .1 trRng. N quy .Snh sR
dng câ LCD, v chng ta .ang kh2o st LCD lo:i hi1n thS 2 dng nn N=1
(N=0 cho tr<Qng hXp LCD 1 dng). F l kch th<?c font ch[ hi1n thS, do
LCD c 2 b* font ch[ c sdn trong CGROM nn chng ta cLn là ch-n
thng qua bit F, n>u F=1 b* font 5x10 .<Xc sC dHng v n>u F=0 th font 5x8
.<Xc hi1n thS. 2 bit th5p trong m lBnh ny c th1 .<Xc gn gi trS ty . M
lBnh .<Xc dng phe bi>n cho lBnh function set l 0x38 (00111000 giao ti>p
8 bit, 2 dng v?i font 5x8 ) hoDc 0x28 (00101000 giao ti>p 4 bit, 2 dng
v?i font 5x8 ). V dH trong bi ny sC dHng c2 2 m lBnh trn.
3.3 Giao ti*p 8 bit v 4 bit.
Nh< trnh by trong lBnh function set, c 2 mode .1 ghi v .-c d[ liBu
vo LCD . l mode 8 bit v mode 4 bit:
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- Mode 8 bit: N>u bit DL trong lBnh function set bZng 1 th mode 8 bit
.<Xc dng. b1 sC dHng mode 8 bit, t5t c2 cc lines d[ liBu câ LCD t; D0
.>n D7 (t; chn 7 .>n chn 14) ph2i .<Xc nRi v?i 1 PORT câ chip .i/u
khi1n bn ngoi (v dH PORTC câ ATmega32 trong v dH câ bi ny) nh<
trong hnh 3. u .i1m câ ph<@ng php giao ti>p ny l d[ liBu .<Xc ghi v
.-c r5t nhanh v .@n gi2n v chip .i/u khi1n chU cLn xu5t hoDc nhAn d[ liBu
trn 1 PORT. Tuy nhin, ph<@ng php ny c nh<Xc .i1m l teng sR chn
dnh cho giao ti>p LCD qu nhi/u, n>u tnh lun c2 3 chn .i/u khi1n th
cLn .>n 11 .<Qng cho giao ti>p LCD.
- Mode 4 bit: LCD cho php giao ti>p v?i b* .i/u khi1n ngoi theo ch>
.* 4 bit. Trong ch> .* ny, cc chn D0, D1, D2 v D3 câ LCD khng
.<Xc sC dHng (.1 trRng), chU c 4 chn t; D4 .>n D7 .<Xc k>t nRi v?i chip
b* .i/u khi1n ngoi. Cc instruction v data 8 bit sc .<Xc ghi v .-c bZng
cch chia thnh 2 phLn, g-i l cc Nibbles, mYi nibble gPm 4 bit v .<Xc
giao ti>p thng qua 4 chn D7:4, nibble cao .<Xc xC l tr<?c v nibble th5p
sau. u .i1m l?n nh5t câ ph<@ng php ny tRi thi1u sR lines dng cho giao
ti>p LCD. Tuy nhin, viBc .-c v ghi t;ng nibble t<@ng .Ri kh khKn h@n
.-c v ghi d[ liBu 8 bit. Trong bi h-c ny, ti sc trnh by 2 ch<@ng trnh
con .<Xc vi>t ring .1 ghi v .-c cc nibbles g-i l Read2Nib v
Write2Nib.
II. AVR v Text LCD.
1. Trnh tX giao tiQp Text LCD.
Trnh t` giao ti>p v?i LCD .<Xc trnh by trong flowchart W hnh 6.
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Hnh 6. Trnh t` giao ti>p v?i Text LCD.
b1 sC dHng LCD chng ta cLn khWi .*ng LCD, sau khi .<Xc khWi .*ng
LCD . sdn sng .1 hi1n thS. Qu trnh khWi .*ng chU cLn th`c hiBn 1 lLn W
.Lu ch<@ng trnh. Trong bi ny, qu trnh khWi .*ng .<Xc vi>t trong 1
ch<@ng trnh con tn int_LCD, khWi .*ng LCD th<Qng bao gPm xc lAp
cch giao ti>p, kch th<?c font, sR dng LCD (funcstion set), cho php hi1n
thS LCD, sursor(Display control), ch> .* hi1n thS tKng/gi2m, shift (Entry
mode set). Cc th^ tHc khc nh< xa LCD, vi>t k t` ln LCD, di chuy1n
con tr_.<Xc sC dHng lin tHc trong qu trnh hi1n thS LCD v sc .<Xc
trnh by trong cc .o:n ch<@ng trnh con ring.
2. AVR giao tiQp v-i Text LCD trong WinAVR.
PhLn ny ti trnh by cch .i/u khi1n hi1n thS Text LCD bZng vi .i/u
khi1n AVR trong mi tr<Qng C câ WinAVR. Hnh thGc l m*t th< viBn
hm giao ti>p Text LCD trong 1 file header c tn l myLCD.h. Cc hm
trong th< viBn bao gPm (ch l phLn code trong List 0 khng nZm trong
file myLCD.h).
List 0. Cc hm c trong th< viBn myLCD.
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char Read2Nib(); //.-c 2 nibbles t; LCD
void Write2Nib(uint8_t chr); //ghi 2 nibbles vo LCD
void Write8Bit(uint8_t chr); //ghi tr` ti>p 8 bit v LCD
void wait_LCD(); //chQ LCD r2nh
void init_LCD(); //khWi .*ng LCD
void clr_LCD(); //xa LCD
void home_LCD(); //.<a cursor v/ home
void move_LCD(uint8_t y, uint8_t x); //di chuy1n cursor .> vS tr mong muRn (dng, c
void putChar_LCD(uint8_t chr); //ghi 1 k t` ln LCD
void print_LCD(char* str, unsigned char len); //hi1n thS chuYi k t`
Tuy nhin, tr<?c khi vi>t cc hm giao ti>p LCD chng ta cLn .Snh
ngh\a m*t sR macro v bi>n. Hy t:o 1 file Header c tn myLCD.h v vi>t
cc .o:n code bn d<?i vo file ny (bMt .Lu t; List 1).
List 1. bSnh ngh\a cc bi>n thay th>.
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#define sbi(sfr,bit) sfr|=_BV(bit)
#define cbi(sfr,bit) sfr&=~(_BV(bit))
#define EN 2
#define RW 1
#define RS 0
#define CTRL PORTB
#define DDR_CTRL DDRB
#define DATA_O PORTB
#define DATA_I PINB
#define DDR_DATA DDRB
/*
#define LCD8BIT
#define DATA_O PORTD
#define DATA_I PIND
#define DDR_DATA DDRD
*/
cbi v sbi l 2 macro .<Xc dHng .1 xa v set 1 bit trong 1 thanh ghi. V
dH cbi(PORTA, 5) l xa bit 5 trong thanh ghi PORT v/ 0. Do WinAVR
khng hY trX tuy xu5t tr`c ti>p cc bit nn cLn .Snh ngh\a 2 macro ny hY
trX.
Ntinside 159
Cc bi>n EN, RW v RS .Snh ngh\a sR thG t` câ chn trn 1 PORT
câ AVR .<Xc dng .1 k>t nRi v?i cc chn EN, R/W v RS câ LCD.
CTRL l bi>n cho bi>t PORT no câ AVR .<Xc dng .1 k>t nRi v?i cc
chn .i/u khi1n câ LCD.DDR_CTRL l thanh ghi .i/u khi1n h<?ng câ
PORT k>t nRi v?i cc chn .i/u khi1n, DDR_CTRL lun phH thu*c vo bi>n
CTRL. Trong tr<Qng hXp câ bi ny, b:n th5y ti .Snh ngh\a CTRL l
PORTB ngh\a l PORTB .<Xc dng .1 k>t nRi v?i cc chn .i/u khi1n
LCD, v CTRL l PORTB nn DDR_CTRL ph2i l DDRB (thanh ghi .i/u
khi1n h<?ng câ PORTB). EN .Snh ngh\a bZng 2 ngh\a l chn EN câ LCD
.<Xc nRi v?i chn 2 câ PORTB (PB2), t<@ng t` chn R/W nRi v?i chn 1
PORTB (PB1) v chn RS nRi v?i chn 0 PORTB (PB0). ViBc ch-n cc
PORT giao ti>p v thG t` chn phH thu*c vo k>t nRi thAt trong m:ch .iBn
giao ti>p, b:n ph2i thay .ei cc .Snh ngh\a ny cho ph hXp v?i thi>t k>
m:ch .iBn câ b:n. L do cho viBc .Snh ngh\a cc bi>n thay th> ki1u ny l
nhZm t:o ra tnh teng qut cho th< viBn hm. V dH, m*t ng<Qi khng muRn
dng PORTB .1 .i/u khi1n LCD m dng PORTA th ng<Qi ny chU cLn
thay .ei .Snh ngh\a W 2 dng 7 v 8, khng cLn thay .ei n*i dung cc hm v
trong cc hm ny chng ta chU dng tn thay th> l CTRL v DDR_CTRL.
T<@ng t`, ti .Snh ngh\a 3 bi>n thay th> l DATA_O ngh\a l PORT xu5t d[
liBu, DATA_I l PORT nhAp d[ liBu v DDR_DATA l thanh ghi .i/u
khi1n h<?ng. DATA_O v DATA_I l PORT nRi v?i cc chn D0:7 (mode
8 bit) hoDc D4:7 (mode 4 bit) câ LCD, .y l cc .<Qng truy/n v nhAn d[
liBu. Trong v dH trn, ti dng chnh PORTB lm .<Qng data v .y l
tr<Qng hXp giao ti>p 4 bit, do 3 chn .Lu câ PORTB k>t nRi v?i cc chn
.i/u khi1n nn PORTB chU cn th;a l:i 5 chn, chng ta sc nRi 4 chn PB4,
PB5, PB6 v PB7 t<@ng Gng v?i D4, D5, D6 v D7 câ LCD. Hnh 7 m t2
cch k>t nRi AVR v LCD theo v dH ny. T5t nhin b:n c th1 sC dHng
PORT khc lm .<Qng data nh5t l khi b:n muRn sC dHng mode 8 bit, v
trong mode ny cLn t?i 11 .<Qng giao ti>p (3 .i/u khi1n + 8 data). PhLn
.<Xc che trong 2 d5u comment /* */ l tr<Qng hXp b:n muRn d^ng mode 8
bit. b1 sC dHng mode 8 bit, b:n cLn .Snh ngh\a 1 bi>n c tn LCD8BIT, bit
ny sc bo cho cc .o:n ch<@ng trnh con th`c hiBn ghi v .-c d[ liBu theo
cch 8 bit. bPng thQi, b:n ph2i .Snh ngh\a l:i .<Qng giao ti>p data
(DATA_O, DATA_I, DDR_DATA).
Ntinside 160

Hnh 7. V dH K>t nRi LCD v?i AVR trong mode 4 bit (chip mega8).
PhLn bn d<?i l phLn .Snh ngh\a cc hm trong th< viBn myLCD. BRn
hm .Lu tin (xem l:i List 0) l cc hm hY trX, chng chU .<Xc dng bWi cc
hm khc trong th< viBn v khng .<Xc g-i trong cc ch<@ng trnh Gng
dHng bn ngoi.
List 2. b-c 2 nibbles t; LCD.
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char Read2Nib(){
char HNib, LNib;
DATA_O |=0xF0;
sbi(CTRL,EN); //enable
DDR_DATA &=0x0F; //set 4 bits cao cua PORT DATA lam input
HNib=DATA_I & 0xF0;
cbi(CTRL,EN); //disable

LNib = DATA_I & 0xF0;
LNib>>=4;
return (HNib|LNib);
Ntinside 161
15 }
Hm ny th`c hiBn viBc .-c d[ liBu t; LCD ra ngoi, .-c theo t;ng
nibble 4 bit, k>t qu2 tr2 v/ l 1 sR 8 bit. Hm ny chU .<Xc dng duy nh5t khi
.-c cQ Busy (BF) trong ch<@ng trnh chQ LCD r2nh (wait_LCD) W mode 4
bit. Tr<?c h>t cLn .Snh ngh\a 1 bi>n t:m HNib (high nibble) v LNib (Low
nibble) .1 chGa 2 nibbles .-c v/ (dng 2, List 2). Dng 5 set chn EN ln
mGc 1 .1 chu]n bS cho LCD lm viBc. Chng ta cLn .ei h<?ng câ PORT d[
liBu trn AVR .1 sdn sng nhAn d[ liBu v/, do chU c 4 bit cao câ PORT
data k>t nRi v?i cc .<Qng data câ LCD (v .y l mode 4 bit) nn chU cLn
set h<?ng cho 4 bit ny trn AVR, dng 6 th`c hiBn viBc set h<?ng. Trong
ch> .* 4 bit, LCD sc truy/n v nhAn nibble cao tr<?c v th> dng 7 .-c d[
liBu t; LCD thng qua cc chn DATA_I vo bi>n HNib, ch l chng ta
chU cLn l5y 4 bit cao câ DATA_I nn cLn ph2i dng gi2i thuAt mDt n:
(mask) che cc bit th5p l:i (and v?i 0xF0). Dng 8 xa chn EN .1 chu]n bS
cho b<?c ti>p theo. T<@ng t`, cc dng 10, 11 v 12 .-c nibble th5p vo
bi>n LNib. Hai dng 13 v 14 k>t hXp 2 nibbles .1 t:o thnh sR 8 bit v tr2
k>t qu2 v/ cho .o:n ch<@ng trnh.
List 3. Ghi 2 nibbles vo LCD.
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void Write2Nib(uint8_t chr){
uint8_t HNib, LNib, temp_data;
temp_data=DATA_O & 0x0F; //doc 4 bit thap cua DATA_O de mask,
HNib=chr & 0xF0;
LNib=(chr<<4) & 0xF0;

DATA_O =(HNib |temp_data);

DATA_O =(LNib|temp_data);
}
Hm Write2Nib th`c hiBn ghi m*t bi>n 8 bit c tn chr vo LCD theo
t;ng nibble, hm ny .<Xc sC dHng r5t nhi/u lLn trong mode 4 bit. Dng 2
.Snh ngh\a 3 bi>n t:m l HNib, LNib v temp_data, khng giRng nh< khi
.-c t; LCD, viBc ghi vo LCD c th1 lm 2nh h<Wng .>n cc chn câ
Ntinside 162
PORT dng lm .<Qng d[ liBu nh5t l khi cc .<Qng .i/u khi1n v d[ liBu
dng chung 1 PORT (PORTB). Bi>n temp_data dng trong gi2i thuAt mDt n:
.1 khng lm 2nh h<Wng .>n cc bit khc khi ghi LCD. Dng 3 .-c d[ liBu
t; PORT DATA_O v che .i cc bit cao, chU ln
temp_data v cc bit th5p ny khng .<Xc dng xu5t nhAp d[ liBu (xem hnh
7, cc chn th5p câ PORTB dng lm cc chn .i/u khi1n). b1 ghi 1 gi trS
8 bit c tn l chr theo cch ghi t;ng nibbles chng ta cLn tch bi>n chr
thnh 2 nibbles. Dng 5 tch 4 bit cao câ chr v chGa vo bi>n HNib. Dng
6 th`c hiBn thm viBc di chuy1n 4 bit th5p câ chr qua tri rPi gn cho bi>n
LNib. Nh< vAy sau 2 dng ny cc bi>n HNib v LNib .<Xc m t2 nh< sau:

Do d[ liu . .<Xc sMp x>p sdn sng W cc vS tr cao (Gng v?i cc chn
D4:7) nn cng vic ti>p theo chU .@n gi2n l xu5t 2 bi>n HNib v LNib ra
.<Qng DATA_O, cLn ph2i t:o 1 xung c:nh xuRng W chn EN mYi lLn xu5t
d[ liBu (dng 9, 10). Ch l ph2i xu5t nibble cao tr<?c v nibble th5p theo
sau.
List 4. Ghi 8 bit tr`c ti>p vo LCD.
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void Write8Bit(uint8_t chr){
DATA_O=chr; //out 8 bits to DATA Line
}
bo:n ny r5t .@n gi2n l xu5t d[ liBu 8 bit ra DATA_O, dng trong
mode 8 bit. Trong mode ny, 8 chn data câ LCD .<Xc nRi v?i 8 .<Qng
DATA_O câ AVR.

List 5. ChQ LCD r2nh.
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void wait_LCD(){
#ifdef LCD8BIT
while(1){
cbi(CTRL,EN); //xa EN
cbi(CTRL,RS); //.y l Instruction
Ntinside 163
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sbi(CTRL,RW); //chi/u t; LCD ra ngoi

DDR_DATA=0xFF; //h<?ng data out
DATA_O=0xFF; // gWi lBnh .-c BF

DDR_DATA=0x00; // bei h<?ng data in
if(bit_is_clear(DATA_I,7)) break;
}
cbi(CTRL,EN); //disable for next step
cbi(CTRL,RW); //ready for next step
DDR_DATA=0xFF; //Ready to Out
#else
char temp_val;
while(1){
cbi(CTRL,RS); //RS=0, the following data is COMMAND
sbi(CTRL,RW); //LCD -> AVR
temp_val=Read2Nib();
if (bit_is_clear(temp_val,7)) break;
}
cbi(CTRL, RW); //ready for next step
DDR_DATA=0xFF;//Ready to Out
#endif
//_delay_ms(1);
}

Hm wait_LCD chU lm m*t viBc .@n gi2n l chQ cho .>n khi LCD r2nh
.1 gn cc cng viBc khc. bo:n code trong list 5 trnh by cch 1: .-c cQ
Busy Flag v chQ .>n khi n bZng 0 (LCD r2nh). ViBc .-c cQ BF phH thu*c
v mode .ang sC dHng l 8 bit hay 4 bit, v th> lBnh #ifdef trong dng sR 2
ki1m tra mode ph hXp tr<?c khi ti>n hnh .-c. #ifdef LCD8BIT ngh\a l
n>u bi>n LCD8BIT . .<Xc .Snh ngh\a W pha trn (mode 8 bit .<Xc dng)
th sc ti>n hnh .-c BF theo mode ny. BZng cch ki1m tra s` c mDt câ
bi>n LCD8BIT ch<@ng trnh sc bi>t cch ghi v .-c LCD ph hXp, ph<@ng
php dng #ifdef LCD8BIT .<Xc p dHng cho t5t c2 cc hm sau ny. Cc
.o:n code t; dng 4 .>n 17 th`c hiBn trong mode 8 bit. Tr<?c khi .-c BF,
chng ta cLn gWi 1 lBnh .-c BF W dng 9, sau . W dng 12 th`c hiBn .ei
h<?ng cc chn data .1 nhAn gi trS v/. Trong dng 10, ki1m tra bit thG 7
câ DATA_I, DATA_I chnh l gi trS .-c v/ v bit thG 7 trong gi trS nhAn
Ntinside 164
v/ chnh l cQ Busy Flag. N>u BF=0 (bit_is_clear(DATA_I,7)) th k>t thc
qu trnh lDp chQ v?i lBnh break;. Trong tr<Qng hXp mode 4 bit .<Xc sC
dHng (#else), qu trnh ki1m tra cQ BF c7ng t<@ng t`, .i1m khc nhau duy
nh5t l cch .-c d[ liBu v/ c khc, chng ta dng hm Read2Nib . .<Xc
vi>t tr<?c . .1 nhAn gi trS v/ (xem dng 23). Nh< . trnh by, chng ta c
th1 vi>t hm wait_LCD bZng cch dng hm delay m*t kho2ng thQi gian cR
.Snh, trong dng 29 b:n th5y m*t hm _delay_ms(1) khng .<Xc sC dHng,
n>u muRn b:n c th1 xa h>t cc dng lBnh tr<?c . trong hm wait_LCD
v dng hm delay ny .1 thay th>, LCD van sc ho:t .*ng tRt.
List 6. KhWi .*ng LCD.
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void init_LCD(){
DDR_CTRL=0xFF;
DDR_DATA=0xFF;
//Function set------------------------------------------------------------------------------
cbi(CTRL,RS); // the following data is COMMAND
cbi(CTRL, RW); // AVR->LCD
cbi(CTRL, EN);
#ifdef LCD8BIT
Write8Bit(0x38);
wait_LCD();
#else
sbi(DATA_O, 5);
wait_LCD();
Write2Nib(0x28);//4 bit mode, 2 line, 5x8 font
wait_LCD();
#endif
//Display control-------------------------------------------------------------------------
#ifdef LCD8BIT
Write8Bit(0x0E);
wait_LCD();
#else
Write2Nib(0x0E);
wait_LCD();
#endif
//Entry mode set------------------------------------------------------------------------
Ntinside 165
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#ifdef LCD8BIT
Write8Bit(0x06);
wait_LCD();
#else
Write2Nib(0x06);
wait_LCD();
#endif
}

Qu trnh khWi .*ng gPm 3 b<?c: function set, display control v entry
mode set.
V?i function set, ba dng 5,6 v 7 xc lAp cc chn .i/u khi1n .1 chu]n
bS gWi cc lBnh. Hai dng 9 v 10 vi>t lBnh function set vo LCD theo mode
8 bit. Gi trS 0x38, tGc 00111000 l m*t lBnh xc lAp mode 8 bit, LCD 2
dng v font 5x8. N>u mode 4 bit .<Xc dng, chng ta cLn vi>t hm
function set khc .i m*t cht. Theo mDc .Snh, khi v;a khWi .*ng LCD th
mode 8 bit sc .<Xc ch-n, v th> n>u m*t hm no . .<@c ghi vo LCD .Lu
tin, LCD sc cR gMng .-c h>t cc chn D0:7 .1 l5y d[ liBu, do trong mode 4
bit cc chn D0:3 khng .<Xc k>t nRi v?i AVR nn viBc .-c lLn .Lu c th1
dan .>n sai sR. V vAy, viBc .Lu tin cLn lm n>u muRn sC dHng mode 4 bit
l gWi m*t lBnh function set v?i tham sR DL=0 (0010xxxx) .>n LCD .1 bo
mode chng ta muRn dng. Dng 13 lm viBc ny, dng lBnh chU .@n gi2n
set bit D5 nh<ng . chnh l gWi lBnh d:ng0010xxxx .>n LCD, v th> LCD
sc vo mode 4 bit sau lBnh ny. Ti>p theo qu trnh thao tc v?i LCD diIn ra
bnh th<Qng, dng 16 ghi vo LCD m câ function set, trong tr<Qng hXp
ny l m 0x28, tGc 00101000: mode 4 bit, LCD 2 dng v font 5x8.
V?i Display control, m lBnh .<Xc dng l 0x0E, tGc 00001110 trong
. 00001 l m câ lBnh display control, 3 bit theo sau xc lAp hi1n thS LCD,
hi1n thS cursor v khng blinking.
V?i Entry mode set, m lBnh .<Xc dng l 0x06 tGc hi1n thS tKng v
khng shift. Xem l:i phLn gi2i thch tAp lBnh LCD .1 hi1u thm ngh\a câ
m lBnh 0x06.
List 7. Di chuy1n cursor.
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void home_LCD(){
#ifdef LCD8BIT
Write8Bit(0x02);
wait_LCD();
Ntinside 166
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#else
Write2Nib(0x02);
wait_LCD();
#endif
}
void move_LCD(uint8_t y,uint8_t x){
uint8_t Ad;
Ad=64*(y-1)+(x-1)+0x80; // tnh m lBnh
#ifdef LCD8BIT
Write8Bit(Ad);
wait_LCD();
#else
Write2Nib(Ad);
wait_LCD();
#endif
}

List 7 trnh by 2 hm di chuy1n cursor v/ home (home_LCD) v di
chuy1n .>n 1 vS tr do ng<Qi dng .Dt. Hmhome_LCD t<@ng .Ri .@n gi2n
v chU cLn ghi m lBnh 0x02 vo LCD th cursor sc t` .*ng di chuy1n v/
home (vS tr .Lu tin trn LCD).
Hm move_LCD(uint8_t y,uint8_t x) cho php di chuy1n cursor .>n
vS tr dng y, c*t x. bi1m cLn ch trong hm ny l cch tnh m lBnh cLn
ghi vo LCD. Th`c ch5t .y l lBnh set DDRAM address. Xem l:i b2ng 2 ta
th5y m lBnh cho lBnh ny c d:ng 1xxxxxxx trong . xxxxxxx l m*t sR 7
bit chGa .Sa chU câ DDRAM chng ta cLn di chuy1n .>n. V th> tr<?c khi
th`c hiBn ghi m lBnh ny, chng ta cLn tnh tham sR xxxxxxx theo dng y,
c*t x. Xem l:i te chGc câ DDRAM trong hnh 3, gi2 sC m*t nh? W dng y
v c*t x trn, do dng 2 bMt .Lu v?i .Sa chU 64, 2 nh? W cng 1 c*t trn 2
dng sc cch nhau 64 vS tr (64*(y-1)). MDt khc do vS tr nh? .<Xc tnh t;
0 trong khi chng ta muRn gn t-a .* x bMt .Lu t; 1, v th> chng ta cLn
thm (x-1) vo cng thGc tnh. CuRi cng chng ta cLn ph2i thm m lBnh
set .Sa chU DDRAM, m 0x80. Gi trS cuRi cng câ m lBnh l : Ad=64*(y-
1)+(x-1)+0x80 (dng 13). Cc dng lBnh ti>p theo trong hm move_LCD
th`c hiBn ghi gi trS m lBnh vo LCD.
CuRi cng l phLn code hi1n thS LCD .<Xc trnh by trong list 8. PhLn
hi1n thS bao gPm 1 ch<@ng trnh con: xa LCd, hi1n thS 1 k t` v hi1n thS 1
chuYi cc k t`.
Ntinside 167
List 8. Hi1n thS trn LCD.
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void clr_LCD(){ //xa ton b* LCD
cbi(CTRL,RS); //RS=0 mean the following data is COMMAND (not normal DATA)
#ifdef LCD8BIT
Write8Bit(0x01);
wait_LCD();
#else
Write2Nib(0x01);
wait_LCD();
#endif
}
void putChar_LCD(uint8_t chr){ //hi1n thS 1 k t` chr ln LCD
sbi(CTRL,RS); //this is a normal DATA
#ifdef LCD8BIT
Write8Bit(chr);
wait_LCD();
#else
Write2Nib(chr);
wait_LCD();
#endif
}
void print_LCD(char* str, unsigned char len){ //Hi1n thS 1 chuYi k t`
unsigned char i;
for (i=0; i<len; i++)
if(str[i] > 0) putChar_LCD(str[i]);
else putChar_LCD(' ');
}
}

b1 xa ton b* LCD chng ta cLn gWi 1 instruction c m 0x01 .>n
LCD, hm clr_LCD() th`c hiBn viBc ny. L cLn xa chn RS xuRng 0 tr<?c khi gWi m ny xuRng
LCD (dng 2 xa chn RS). Hm putChar_LCD(uint8_t chr) hi1n thS 1
k t` ln LCD, gi trS tham sR câ hm ny l m ASCII câ k t` cLn hi1n
thS,chr. N*i dung câ hm hon ton giRng hm xa LCD, chU khc .y
khng ph2i l 1 instruction nn cLn set chn RS ln 1 tr<?c khi gWi m lBnh
.>n LCD (dng 12). M lBnh cho hm ny chnh l m ASCII cLn hi1n thS.
CuRi cng hmprint_LCD(char* str, unsigned char len) cho php hi1n thS
Ntinside 168
1 chuYi k t` lin ti>p ln LCD, th`c ch5t .y l qu trnh lDp câ hm hi1n
thS 1 k t`. Ch tham sR len l chi/u di cLn hi1n thS câ chuYi.
I. V d5 =iTu khiGn Text LCD bMng th9 vi0n myLCD.
PhLn ny ti sc minh h-a cch sC dHng th< viBn myLCD.h .1 hi1n thS
cc k t` ln 1 Text LCD. SC dHng phLn m/m Proteus vc m*t m:ch .iBn
gPm 1 LCD 2x16 (keyword: LM016L), 1 chip Atmega32 v 1 bi>n trW
(POT-LIN) nh< trong hnh 8. T:o 1 Project bZng WinAVR c tn l
TextLCD_Demo v t:o file source l main.c, t:o makefile v?i khai bo s[
dHng chip ATmega32 v clock 8MHz. Copy file myLCD.h vo th< mHc câ
Project m?i t:o. Vi>t code cho file main.c nh< trong list 9. Ch cc .Snh
ngh\a chn k>t nRi v?i LCD trong phLn .Lu file myLCD.h ph2i giRng v?i k>t
nRi thAt trong hnh 8.
Ntinside 169

Hnh 8. M:ch .iBn m ph_ng LCD v?i AVR.
List 8. Ch<@ng trnh demo .i/u khi1n TextLCD, main.c.

#include <avr/io.h>
#include "myLCD.h" //include th< viBn myLCD
int main(){
init_LCD(); //khWi .* LCD
clr_LCD(); // xa to b* LCD
Ntinside 170
putChar_LCD(' '); //ghi 1 kho2ng trMng
putChar_LCD(' '); //ghi 1 kho2ng trMng
putChar_LCD('D'); //Hi1n thS kt` 'D'
print_LCD("emo of the",10); //hi1n thS 1 chuYi k t`
move_LCD(2,1); //di chuy1n cursor .>n dng 2, c*t .Lu tin
print_LCD("2x16 LCD Display",16); //hi1n thS chuYi thG 2
while(1){

};
}

b1 sC dHng th< viBn myLCD, chng ta cLn include file myLCD.h vo
Project nh< trong dng 3, #include "myLCD.h". Hai dng 6 v 7 th`c hiBn
khWi .*ng v xa LCD. Sau ., cc dng 9, 10 v 11 .Dt 3 k t` l cc
kho2ng trMng v ch[ ci D bZng hm putChat_LCD. Dng 12 in chuYi emo
of the ngay ti>p theo ch[ ci D tr<?c . bZng hm print_LCD. Dng 13
th`c hiBn di chuy1n cursor .>n vS tr dng thG 2, c*t .Lu tin câ LCD tr<?c
khi ti>n hnh in chuYi thG 2 2x16 LCD Display W dng code 14. N>u b:n
th`c hiBn .ng trnh t` nh< trn, k>t qu2 thu .<Xc sc nh< trong hnh 8.

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Graphic LCD

Trong bi Gng dHng ny ti trnh by v/ c5u trc v cch .i/u khi1n
Graphic LCD lo:i dot khng mu. Cng cH chnh c7ng l 2 b* phLn m/m
quen thu*c WinAVR, Proteus v phLn m/m bin tAp Graphic LCD, G.Edit.
- C5u trc Graphic LCD 128x64 v chip .i/u khi1n KS0108.
- Nguyn l ho:t .*ng Graphic LCD.
- Pht tri1n 1 th< viBn .i/u khi1n Graphic LCD 128x64 cho AVR.
- V dH .i/u khi1n Graphic LCD 128x64 bZng AVR.
II. Graphic LCD.
Graphic LCD (g-i tMt l GLCD) lo:i ch5m khng mu l cc lo:i mn
hnh tinh th1 l_ng nh_ dng .1 hi1n thS ch[, sR hoDc hnh 2nh. Khc v?i Text
LCD, GLCD khng .<Xc chia thnh cc .1 hi1n thS cc m ASCII v
GLCD khng c b* nh? CGRAM (Character Generation RAM). GLCD
128x64 c 128 c*t v 64 hng t<@ng Gng c 128x64=8192 ch5m (dot). MYi
ch5m t<@ng Gng v?i 1 bit d[ liBu, v nh< th> cLn 8192 bits hay 1024 bytes
RAM .1 chGa d[ liBu hi1n thS .Ly mYi 128x64 GLCD. Ty theo lo:i chip
.i/u khi1n, nguyn l ho:t .*ng câ GLCD c th1 khc nhau, trong bi ny
ti gi?i thiBu lo:i GLCD .<Xc .i/u khi1n bWi chip KS0108 câ Samsung, c
th1 ni GLCD v?i KS0108 l phe bi>n nh5t trong cc lo:i GLCD lo:i ny
(ch5m, khng mu). Hnh 1 l hnh 2nh thAt câ 1 GLCD 128x64 .i/u khi1n
bWi KS0108.
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Hnh 1. Graphic LCD 128x64.
Chip KS0108 chU c 512 bytes RAM (4096 bits = 64x64) v v th> chU
.i/u khi1n hi1n thS .<Xc 64 dng x 64 c*t. b1 .i/u khi1n GLCD 168x64 cLn
2 chip KS0108, v th`c th> trong cc lo:i GLCD c 2 chip KS0108, GLCD
128x64 do . t<@ng t` 2 GLCD 64x64 ghp l:i. Chng ta sc lLn l<Xt kh2o
st s@ .P chn, c5u trc b* nh? v nguyn l ho:t .*ng câ GLCD, chip
KS0108 trong phLn ti>p theo.
1. S. =V chn GLCD 128x64.
Cc GLCD 128x64 dng KS0108 th<Qng c 20 chn trong . chU c 18
chn l th`c s` .i/u khi1n tr`c ti>p GLCD, 2 chn (th<Qng l 2 chn cuRi 19
v 20) l 2 chn Anode v Cathode câ LED n/n. Trong 18 chn cn l:i, c
4 chn cung c5p nguPn v 14 chn .i/u khi1n+d[ liBu. Khc v?i cc Text
LCD HD44780U, GLCD KS0108 khng hY trX ch> .* giao ti>p 4 bit, do .
b:n cLn dnh ra 14 chn .1 .i/u khi1n 1 GLCD 128x64. S@ .P chn phe
bi>n câ GLCD 128x64 .<Xc m t2 trong b2ng 1.
B2ng 1. S@ .P chn GLCD GDM-12864-04.
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Ch l trn m*t sR GLCD, thG t` cc chn c th1 khc (nh< GLCD
WG12864A2) nh<ng sR l<Xng v chGc nKng chn th khng .ei. Hnh 2
m t2 cch k>t nRi GLCD v?i nguPn v m:ch .i/u khi1n.
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Hnh 2. K>t nRi GLCD.
Chn VSS .<Xc nRi tr`c ti>p v?i GND, chn VDD nRi v?i nguPn +5V,
m*t bi>n trW kho2ng 20K .<Xc dng .1 chia .iBn p giCa Vdd v Vee cho
chn Vo, bZng cch thay .ei gi trS bi>n trW chng ta c th1 .i/u chUnh .*
t<@ng ph2n câ GLCD. Cc chn .i/u khi1n RS, R/W, EN v cc .<Qng d[
liBu .<Xc nRi tr`c ti>p v?i vi .i/u khi1n. Ring chn Reset (RST) c th1 nRi
tr`c ti>p v?i nguPn 5V.
EN (Enable): cho php m*t qu trnh bMt .Lu, bnh th<Qng chn EN
.<Xc gi[ W mGc th5p, khi m*t th`c hiBn m*t qu trnh no . (.-c hoDc ghi
GLCD), cc chn .i/u khi1n khc sc .<Xc ci .Dt sdn sng, sau . kch chn
EN ln mGc cao. Khi EN .<Xc ko ln cao, GLCD bMt .Lu lm th`c hiBn
qu trnh .<Xc yu cLu, chng ta cLn chQ m*t kho2ng thQi gian ngMn cho
GLCD .-c hoDc gWi d[ liBu. CuRi cng l ko EN xuRng mGc th5p .1 k>t
thc qu trnh v c7ng .1 chu]n bS chn EN cho qu trnh sau ny.
RS (Register Select): l chn là ch-n gi[a d[ liBu (Data) v lBnh
(Instruction), v th> m trong m*t sR ti liBu b:n c th1 th5y chn RS .<Xc
g-i l chn DI (Data/Instruction Select). Chn RS=1 bo rZng tn hiBu trn
cc .<Qng DATA (D0:7) l d[ liBu ghi hoDc .-c t; RAM câ GLCD. Khi
RS=0, tn hiBu trn .<@ng DATA l m*t m lBnh (Instruction).
RW (Read/Write Select): ch-n là gi[a viBc .-c v ghi. Khi RW=1,
chi/u truy cAp t; GLCD ra ngoi (GLCD->AVR). RW=0 cho php ghi vo
GLCD. Giao ti>p v?i GLCD ch^ y>u l qu trnh ghi (AVR ->GLCD), chU
duy nh5t tr<Qng hXp .-c d[ liBu t; GLCD l .-c bit BUSY v .-c d[ liBu t;
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RAM. b-c bit BUSY th chng ta . kh2o st cho Text LCD, bit ny bo
GLCD c .ang bAn hay khng, viBc .-c ny sc .<Xc dng .1 vi>t hm
wait_GLCD. b-c d[ liBu t; RAM câ GLCD l m*t kh2 nKng m?i m Text
LCD khng c, bZng viBc .-c ng<Xc t; GLCD vo AVR, chng ta c th1
th`c hiBn nhi/u php logic hnh (hay mDt n:, mask) lm cho viBc hi1n thS
GLCD thm th vS.
CS2 v CS1 (Chip Select): nh< ti . trnh by trong phLn trn, mYi
chip KS0108 chU c kh2 nKng .i/u khi1n m*t GLCD c kch th<?c 64x64,
trn cc GLCD 128x64 c 2 chip KS0108 lm viBc cng nhau, mYi chip .2m
nhiBm m*t n[a LCD, 2 chn CS2 v CS1 cho php ch-n m*t chip KS0108
.1 lm viBc. Thng th<Qng n>u CS2=0, CS1=1 th nCa tri .<Xc kch ho:t,
ng<Xc l:i khi CS2=1, CS1=0 th nCa ph2i .<Xc ch-n. Chng ta sc hi1u r
h@n cch phRi hXp lm viBc câ 2 nCa GLCD trong phLn kh2o st b* nh?
câ LCD.
2. TK chOc bD nh-.
Chip KS0108 c m*t lo:i b* nh? duy nh5t . l RAM, khng c b* nh?
chGa b* font hay chGa m font t` t:o nh< chip HD44780U câ Text LCD.
V vAy, d[ liBu ghi vo RAM sc .<Xc hi1n thS tr`c ti>p trn GLCD. MYi
chip KS0108 c 512 bytes RAM t<@ng Gng v?i 4096 ch5m trn m*t nCa
(64x64) LCD. RAM câ KS0108 khng cho php truy cAp t;ng bit m theo
t;ng byte, .i/u ny c ngh\a l mYi lLn chng ta vi>t m*t gi trS vo m*t
byte no . trn RAM câ GLCD, sc c 8 ch5m bS tc .*ng, 8 ch5m ny
nZm trn cng 1 c*t. V l do ny, 64 dng GLCD th<Qng .<Xc chia thnh 8
pages, mYi page c .* cao 8 bit v r*ng 128 c*t (c2 2 chip g*p l:i). Hnh 3
m t2 b/ mDt m*t GLCD v c7ng l cch sMp x>p RAM câ cc chip
KS0108.
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Hnh 3. Te chGc câ RAM.
Te chGc RAM câ 2 chip KS0108 tri v ph2i hon ton t<@ng t`, viBc
.-c hay ghi vo RAM câ 2 chip c7ng .<Xc th`c hiBn nh< nhau. Chng ta
sc ch-n nCa tri GLCD .1 kh2o st. Nh< b:n th5y trn hnh 3, 64 dng t;
trn xuRng d<?i .<Xc chia thnh 8 dy m ta g-i l 8 pages. Page trn
cng l page 0 v page d<?i cng la page 7. Trong cc GLCD, page cn
.<Xc g-i l .Sa chU X (X address), hay ni cch khc X=0 l .Sa chU câ page
trn cng, t<@ng t` nh< th>, X=7 l .Sa chU câ page d<?i cng. MYi page
chGa 64 c*t (chU xt 1 chip KS0108), mYi c*t l m*t byte RAM 8 bit, mYi bit
t<@ng Gng v?i 1 ch5m trn LCD, bit c tr-ng sR th5p (LBS - tGc bit D0 nh<
trong hnh 3) t<@ng Gng v?i ch5m trn cao nh5t. Bit c tr-ng sR cao nh5t
(MBS - tGc bit D7 nh< trong hnh 3) t<@ng Gng v?i ch5m th5p nh5t trong 1
page. ThG t` cc c*t trong 1 page g-i l .Sa chU Y (Y address), nh< th> c*t
.Lu tin c .Sa chU Y = 0 trong khi c*t cuRi cng c .Sa chU Y l 63. BZng
cch phRi hXp .Sa chU X v .Sa chU Y chng ta xc .Snh .<Xc vS tr câ byte
cLn .-c hoDc ghi. Chip KS0108, t5t nhin, sc hY trX cc lBnh di chuy1n .>n
.Sa chU X v Y .1 ghi hay .-c RAM. Hy quan st hnh 4 .1 xem cch m
m*t ch[ ci a .<Xc hi1n thS trn GLCD.
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Hnh 4. Hi1n thS ch[ ci a trn GLCD.
Trong cch hi1n thS W hnh 4, ch[ a chU nZm trong page 0, tGc X=0.
MuRn hi1n thS ch[ ci a chng ta cLn ghi vo cc c*t (.Sa chU Y) câ page
0 lLn l<Xt cc gi trS nh< sau: 0, 228, 146, 74, 252 v 128., xem b2ng bn
d<?i.

3. T]p l0nh cho chip KS0108.
B2ng 2 tm tMt cc lBnh câ chip KS0108.
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So v?i HD44780U câ Text LCD, lBnh cho KS0108 câ GLCD .@n gi2n
v t h@n v v th> vi>t ch<@ng trnh .i/u khi1n GLCD c7ng t<@ng .Ri dI
h@n Text LCD. C t5t c2 7 lBnh (Instruction) c th1 giao ti>p v?i KS0108.
Ti sc lLn l<Xt gi2i thch ngh\a v cch sC dHng câ t;ng lBnh.
- Display ON/OFF Hi1n thS GLCD: lBnh ny cho php GLCD hi1n thS
n*i dung trn RAM ra b/ mDt GLCD. b1 vi>t lBnh ny cho GLCD, 2 chn
RS v RW cLn .<Xc ko xuRng mGc th5p (RS=0: .y l Instrucion, RW=0:
AVR->GLCD). M lBnh (code) .<Xc chGa trong 7 bit cao (D7:1) v bit D0
chGa thng sR. Quan st b2ng 2, dI th5y m lBnh nhS phn cho Display
ON/OFF l 0011111x (0x3E+x) trong . x=1: cho php GLCD hi1n thS,
x=0: tMt hi1n thS.
- Set Address ch-n .Sa chU: .ng h@n .y l lBnh ch-n c*t hay ch-n
.Sa chU Y. Hai bit D7 v D6 chGa m lBnh (01000000=0x40=64) v 6 bit cn
l:i chGa chU sR câ c*t muRn di chuy1n .>n. Ch l mYi nCa GLCD c 64
c*t nn cLn 6 bit .1 chGa chU sR ny (26=64). VAy lBnh ny c d:ng 0x40+Y.
V dH n>u chng ta muRn di chuy1n .>n c*t 36 chng ta ghi vo GLCD m
lBnh: 0x40+36. Hai chn RS v RW .<Xc gi[ W mGc th5p khi th`c hiBn lBnh
ny.
- Set Page ch-n trang: lBnh cho php ch-n page (hay .Sa chU X) cLn di
chuy1n .>n, do GLCD chU c 8 pages nn chU cLn 3 bit .1 chGa .Sa chU page.
M lBnh cho lBnh ny c d:ng 0xB8+X. Trong . bi>n X l chU sR page cLn
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di chuy1n .>n. Hai chn RS v RW .<Xc gi[ W mGc th5p khi th`c hiBn lBnh
ny.
- Display Start Line ch-n line .Lu tin: hay cn g-i l lBnh cu*n,
lBnh ny cho php di chuy1n ton b* hnh 2nh trn GLCD (hay RAM) ln
pha trn m*t sR dng no ., chng ta g-i l LOffset. SR l<Xng LOffset c
th1 t; 0 .>n 63 nn cLn 6 bit chGa gi trS ny. M lBnh Display Start Line c
d:ng 0xC0+LOffset. Hai chn RS v RW .<Xc gi[ W mGc th5p khi th`c hiBn
lBnh ny. Khi di chuy1n GLCD ln pha trn, phLn d[ liBu pha trn bS che
khu5t sc cu*n xuRng pha d<?i. Hnh 5 l m*t v dH cu*n GLCD ln 20
dng.

- Status Read .-c tr:ng thi GLCD: .y l m*t trong 2 lBnh .-c t;
GLCD. C7ng giRng nh< v?i Text LCD, lBnh .-c tr:ng thi GLCD ch^ y>u
.1 xt bit BUSY (bit thG 7) xem GLCD c .ang bAn hay khng, lBnh ny sc
.<Xc dng .1 vi>t m*t hm wait_GLCD chQ cho .>n khi GLCD r2nh. V
.y l lBnh .-c t; GLCD nn chn RW ph2i .<Xc set ln mGc 1 tr<?c khi
th`c hiBn, chn RS van W mGc th5p (.-c Instruction).
- Write Display Data ghi d[ liBu cLn hi1n thS vo GLCD hay RAM: v
.y l 1 lBnh ghi d[ liBu hi1n thS nn chn RS cLn .<Xc set ln 1 tr<?c khi
th`c hiBn, chn RW gi[ W mGc 0. LBnh ny cho php ghi m*t byte d[ liBu
vo RAM câ KS0108 v c7ng l d[ liBu sc hi1n thS ln GLCD t:i vS tr hiBn
hnh câ 2 con tr_ .Sa chU X v Y. 8 bit d[ liBu ny sc t<@ng Gng v?i 8 ch5m
trn c*t Y W page X. Ch l sau lBnh Write Display Data, .Sa chU c*t Y t`
.*ng .<Xc tKng ln 1 v v th> n>u c m*t d[ liBu m?i .<Xc ghi, d[ liBu m?i
sc khng . ln d[ liBu c7. ViBc tKng t` .*ng .Sa chU Y r5t c lXi cho viBc
ghi d[ liBu lin ti>p, n gip gi2m thQi gian set l:i .Sa chU c*t Y. Sau khi
th`c hiBn ghi W c*t Y=63 (c*t cuRi cng trong 1 page, .Ri v?i 1 chip
KS0108), Ysc v/ 0.
- Read Display Data .-c d[ liBu hi1n thS t; GLCD (c7ng l d[ liBu t;
RAM câ KS0108): lBnh .-c ny m?i so v?i Text LCD, n cho php chng
ta .-c ng<Xc 1 byte d[ liBu t; RAM câ KS0108 t:i vS tr hiBn hnh v/
Ntinside 180
AVR. Sau khi . .-c .<Xc gi trS t:i vS tr hiBn hnh, chng ta c th1 th`c
hiBn cc php Logic nh< .2o bit, or hay andlm tKng kh2 nKng thao tc
hnh 2nh. Tr<?c khi th`c hiBn .-c chng ta cLn di chuy1n .>n vS tr muRn
.-c bZng 2 lBnh set .Sa chU X v Y, sau khi .-c gi trS .Sa chU page X v c*t
Y khng thay .ei, do . n>u .-c ti>p m khng di chuy1n .Sa chU th van thu
.<Xc gi trS c7.
III. AVR v Graphic LCD.
1. Trnh tX giao tiQp GLCD.
So v?i Text LCD th viBc giao ti>p v?i GLCD dI h@n nhi/u v GLCD
c t Instruction h@n, GLCD chU c m*t lo:i b* nh? l RAM t<@ng Gng tr`c
ti>p v?i mn hnh hi1n thS, GLCD khng c cursor nn khng cLn set cursor,
GLCD chU hY trX giao ti>p 8 bit nn khng cLn bAn tm ch-n mode, qu
trnh khWi .*ng cho GLCD v th1 r5t .@n gi2n bZng cch g-i lnh DISPLAY
ON/OFF. Trong hnh 5 ti trnh by qu trnh khWi .*ng v sC dHng GLCD.

Hnh 5. Trnh t` giao ti>p v?i GLCD.
Sau khi khWi .*ng GLCD bZng hm DISPLAY ON chng ta c th1 set
.Sa chU X v Y .1 ghi d[ liBu, thAm ch c th1 ghi d[ liBu m khng cLn set
X, Y. Tuy nhin, cLn nhMc l:i l c .>n 2 chip KS0108 trn GLCD 128x64,
v vAy t5t c2 cc qu trnh ./u ph2i th`c hiBn cho 2 chip.
2. AVR giao tiQp v-i GLCD trong WinAVR.
PhLn ny ti trnh by cch .i/u khi1n hi1n thS GLCD 128x64 bZng vi
.i/u khi1n AVR trong mi tr<Qng C câ WinAVR. Hnh thGc l m*t th<
viBn hm giao ti>p GLCD trong 1 file header c tn l myGLCD.h. Cc hm
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trong th< viBn bao gPm (ch l phLn code trong List 0 khng nZm trong
file myGLCD.h):
List 0. Cc hm c trong th< viBn myGLCD.
Tr<?c khi vi>t cc hm giao ti>p LCD chng ta cLn .Snh ngh\a m*t sR
macro v bi>n. Hy t:o 1 file Header c tn myGLCD.h v vi>t cc .o:n
code bn d<?i vo file ny (bMt .Lu t; List 1).
List 1. bSnh ngh\a cc bi>n thay th>
Ntinside 182
Do GLCD khng hY trX b* font, n>u muRn hi1n thS cc k t` chng ta
cLn .Snh ngh\a chng trong m*t b2ng font (t<@ng t` tr<Qng hXp ma trAn
LED), file font.h . .<Xc t:o tr<?c v include vo th< viBn myGLCD (dng
2). bPng thQi, b* font sc .<Xc chGa trong b* nh? ch<@ng trnh (FLASH) nn
cLn cc hm hY trX .-c FLASH, chng ta include file pgmspace.h phHc vH
cho viBc ny (dng 3).
Ntinside 183
cbi v sbi l 2 macro .<Xc dHng .1 xa v set 1 bit trong 1 thanh ghi. V
dH cbi(PORTA, 5) l xa bit 5 trong thanh ghi PORTA v/ 0. Do WinAVR
khng hY trX tuy xu5t tr`c ti>p cc bit nn cLn .Snh ngh\a 2 macro ny hY trX
(dng 5, 6).
Tm .<Qng DATA sc .<Xc dnh cho 1 PORT, cc dng 8, 9 v 10 .Snh
ngh\a PORT trn AVR dnh cho DATA, trong v dH ny l PORTB. T<@ng
t` cc .<Qng .i/u khi1n c7ng nZm trn cng 1 PORT, cc dng 14, 15, 16
.Snh ngh\a PORT dnh cho cc .<Qng .i/u khi1n (PORTD chFng h:n), sau
. chng ta .Snh ngh\a thG t` chn trn PORT .i/u khi1n k>t nRi v?i cc
chn EN, RW, RS, CS1 v CS2 câ GLCD (xem cc dng t; 18 .>n 22).
Chng ta .Snh ngh\a ti>p 2 macro .1 kch ho:t v stop GLCD W cc dng 25
v 26 v cc ho:t .*ng ny .<Xc dng r5t nhi/u khi giao ti>p v?i GLCD.
Ti>p theo chng ta .Snh ngh\a 4 m lBnh (Instruction code) câ 4 hm
Display on/off, Set Address, Set page v Display Start Line m ti . trnh
by W trn (cc dng t; 29 .>n 32). CuRi cng l .Snh ngh\a vS tr bit BUSY
khi .-c tr:ng thi GLCD.
Sau phLn .Snh ngh\a chng ta sc bMt .Lu vi>t code truy cAp GLCD, .o:n
code trnh by trong List 2 chGa cc hm hY trX.
List 2. Cc hm hY trX.
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Hm GLCD_Delay() th`c hiBn delay kho2ng 16 chu kN my, hm ny
.<Xc dng .1 chQ LGCD .-c hay ghi d[ liBu sau khi chn EN .<Xc kch.
M*t nt m?i W .y l ti sC dHng ngn ng[ ASM chn vo C, d chU l chn
hm nop nh<ng n ni cho b:n bi>t rZng avr-gcc cho php chng ta chn
ASM, ti sc trnh by chi ti>t cc v dH chn ASM phGc t:p h@n trong m*t
bi khc.
Hm GLCD_OUT_Set() W dng 5 set cc PORT giao ti>p trn AVR
(DATA v Control) c h<?ng Ouput. Hm GLCD_IN_Set() W dng 12 set
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cc PORT giao ti>p c h<?ng Input (dng khi .-c t; GLCD -> AVR). Hm
GLCD_SetSide(char Side) W dng 19 ch-n chip KS0108 tri hoDc ph2i .1
thao tc, trong . Side=1 th m*t nCa GLCD bn ph2i .<Xc ch-n bZng cch
reset bit CS1=0 v CS2=1 (cc dng 22, 23), ng<Xc l:i nCa bn tri .<Xc
kch ho:t, CS1=1, CS2=0 (dng 26 v 27).
List 3 trnh by phLn code cho 4 hm truy cAp Instruction GLCD c@ b2n
vi>t l:i cho cc hm Status Read, Display On/Off, Set Address, Set page v
Display Start Line trch t; b2ng 2.
List 3. Cc hm truy cAp Instruction.
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Ntinside 187
T5t c2 cc hm trong List 3 ./u truy cAp Instruction nn chn RS lun
.<Xc ko xuRng mGc th5p, trong 5 hm trn, hm wait_GLCD sC dHng
Instruction .-c tr:ng thi t; GLCD nn chn RW sc .<Xc ko ln cao, trong
4 hm cn l:i chn RW W mGc th5p.
Hm wait_GLCD(void), c7ng t<@ng t` nh< hm wait_LCD() trong
tr<Qng hXp Text LCD, hm ny chQ GLCD r2nh bZng cch .-c tr:ng thi
GLCD v ki1m tra bit BUSY, n>u BUSY bZng 1 th GLCD .ang bAn,
BUSY=0 tGc GLCD r2nh. Cc dng 4, 5, 6 chu]n bS cc .<Qng DATA, RS,
RW cho qu trnh .-c Instruction t; GLCD (RS=0, RW=0), W dng 8 chn
EN .<Xc ko ln cao bZng macro GLCD_ENABLE (.Snh ngh\a trong list
1). NhMc l:i chGc nKng câ chn EN, khi EN=1 GLCD bMt .Lu qu trnh giao
ti>p do cc chn RS, RW xc lAp (trong tr<Qng hXp ny l .-c Instruction t;
GLCD), chng ta cLn chQ m*t kho2ng thQi gian ngMn cho GLCD .]y thanh
ghi tr:ng thi ra cc .<Qng DATA bZng hm GLCD_Delay() trong dng 9.
Ti>p theo g-i GLCD_DISABLE .1 ko chn EN xuRng mGc 0 .1 k>t thc
qu trnh .-c (m*t xung . .<Xc t:o trn chn EN), v bMt .Lu ki1m tra bit
BUSY. Dng 12 l m*t vng lDp while ki1m tra xem n>u bit BUSY trong
gi trS .-c v/ (gi trS .-c v/ chGa trong thanh ghi PIN câ PORT DATA trn
AVR), n>u BUSY=1 (bit_is_set) vng lDp ti>p tHc v?i viBc t:o m*t xung
khc trn chn EN (cc dng ) rPi quay l:i ki1m tra bit BUSY. N>u BUSY
bZng 0, GLCD . r2nh, vng lDp while .<Xc gi2i thot, qu trnh chQ k>t
thc.
Hm GLCD_SetDISPLAY(uint8_t ON) cho php GLCD hi1n thS khi
tham sR ON=1, hoDc tMt khi tham sR ON=0. Tr<?c khi set GLCD chng ta
cLn chQ cho GLCD r2nh bZng cch g-i hm wait_GLCD() W dng 20, sau .
xc lAp cc chn RS, RW sdn sng cho qu trnh gWi m lBnh vo GLCD
(dng 21, 22 v 23). Tr<?c khi kch ho:t qu trnh, cLn chu]n bS m lBnh sdn
sng trn .<Qng d[ liBu, dng
25: GLCD_DATA_O=GLCD_DISPLAY+ON, trong .
GLCD_DISPLAY l m lBnh câ hm Display On/Off .<Xc .Snh ngh\a
trong List 1, bi>n ON bo GLCD tMt hay mW. Sau khi m-i thG . sdn sng,
m*t xung .<Xc t:o ra trn chn EN (cc dng t; 26 .>n 28). Qu trnh set
Display th`c hiBn v k>t thc.
Hm void GLCD_SetYADDRESS(uint8_t Col) l hm vi>t l:i cho
Insrtuction ch-n .Sa chU Y (c*t) cLn thao tc, tham sR Col trong hm ny
chnh l chU sR c*t, Col c gi trS t; 0 .>n 63. N*i dung hm ny hon ton
giRng hmGLCD_SetDISPLAY, chU c m*t .i1m khc duy nh5t l m hm
khc, m GLCD_YADDRESS .<Xc dng (xem dng 36:GLCD_DATA_O
= GLCD_YADDRESS+Col).
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Hm void GLCD_SetXADDRESS(uint8_t Line) l hm vi>t l:i cho
Insrtuction ch-n .Sa chU X (page) cLn thao tc, tham sR Line trong hm ny
chnh l chU sR page, Line c gi trS t; 0 .>n 8. N*i dung hm ny hon ton
giRng hmGLCD_SetXADDRESS, nh<ng m GLCD_XADDRESS .<Xc
dng thay cho GLCD_YADDRESS,(xem dng 36:GLCD_DATA_O =
GLCD_XADDRESS+Line).
Hm void GLCD_StartLine(uint8_t Offset) l hm vi>t l:i cho
Insrtuction cu*n GLCD, chU sR Offset l gi trS cu*n ln. Xem l:i v dH
hnh cu*n GLCD trong phLn gi2i thch câ lBnh Display Start Line, v?i
tr<Qng hXp ny hm GLCD_StartLine(20) . .<Xc g-i.
List 4 trnh by 2 hm vi>t v .-c d[ liBu hi1n thS ln GLCD.
List 4. Cc hm thao tc d[ liBu.
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Hai hm trong list 4 thao tc d[ liBu hi1n thS trn GLCD nn chn RS
ph2i .<Xc set bZng 1.
Hm GLCD_WriteDATA(uint8_t DATA) ghi m*t byte vo RAM câ
KS0108, byte ny c7ng sc .<Xc hi1n thS ln GLCD, vS tr ghi vo l vS tr
hiBn hnh câ con tr_ X v Y (2nh h<Wng bWi cc qu trnh ghi tr<?c . hoDc
do cc hm set .Sa chU), tham sR DATA l byte cLn ghi. N*i dung bn trong
hm ny c7ng giRng nhG cc hm trong list 3. bi1m khc l chn RS .<Xc
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ko ln .1 bo .y l qu trnh thao tc d[ liBu (dng
6: sbi(GLCD_CTRL_O, GLCD_RS)). Gi trS gWi .>n GLCD chnh l
tham sR DATA nh< trong dng 8: GLCD_DATA_O=DATA.
Hm uint8_t GLCD_ReadDATA(void) .-c gi trS hi1n thS trn t;
GLCD vo AVR, chn RW cLn .<Xc set ln 1 .1 bo qu trnh ny l .-c
(dng 22: sbi(GLCD_CTRL_O, GLCD_RW)). Chn EN .<Xc kch ln 1
tr<?c (dng 24:GLCD_ENABLE;) v chQ m*t kho2ng thQi gian ngMn tr<?c
khi .-c gi trS t; cc .<Qng DATA vo m*t bi>n t:m DATA nh< trong dng
26: DATA=GLCD_DATA_I;. Sau khi tr2 gi trS v/ bZng dng lBnh 30:
return DATA, th qu trSnh .-c k>t thc.
V?i cc hm . t:o chng ta . c th1 .i/u khi1n .1 hi1n thS GLCD, cc
ch<@ng trnh con trong List 5 v List 6 sC dHng cc hm trn .1 th`c hiBn
m*t sR nhiBm vH hi1n thS c@ b2n. Chng ta g-i l cc ch<@ng trnh con mW
r*ng.
List 5. Cc ch<@ng trnh con mW r*ng.
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Hm void GLCD_Init(void) khWi .*ng GLCD. Tr<?c h>t, chng ta ph2i
ch-n chip KS0108 .1 khWi .*ng, dng 4: GLCD_SetSide(0) ngh\a l ch-n
chip KS0108 bn tri tGc nCa tri GLCD. Chng ta khWi .*ng nCa tri
GLCD bZng viBc cho php hi1n thS (dng 5: GLCD_SetDISPLAY(1)), di
chuy1n con tr_ v/ vS tr .Lu tin trn GLCD v?i 2 hm ch-n .Sa chU W cc
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dng 6 v 7, ch-n gi trS cu*n l 0 W dng 8: GLCD_StartLine(0). Sau .
lDp l:i qu trnh khWi .*ng cho nCa ph2i câ GLCD (xem cc dng t; 10 .>n
14).
Hm void GLCD_GotoXY(uint8_t Line, uint8_t Col) di chuy1n con
tr_ hi1n thS .>n .Sa chU X v Y. Tham sR Line l .Sa chU X (tGc l page, gi
trS t; 0 .>n 7), tham sR Col l .Sa chU Y hay chnh l c*t. Hm ny cho php
di chuy1n trn ton b* GLCD, ngh\a l bi>n Col c kho2ng gi trS t; 0 .>n
127, v th> tr<?c h>t chng ta ph2i xc .Snh vS tr cLn duy chuy1n .>n thu*c
nCa no câ GLCD, n>u Col<64 th vS tr . thu*c nCa tri, ng<Xc l:i n
thu*c v/ nCa ph2i. Dng 19 chng ta chia Col cho 64 v gn phLn nguyn
k>t qu2 cho 1 bi>n t:m tn l Side (Side=Col/64 ), r rng n>u Col<64 th
Side=0, ng<Xc l:i Side=1. Bi>n Side .<Xc dng lm tham sR cho hm
GLCD_SetSide(Side) W dng 20, v?i cch th`c hiBn ny chng ta . t` .*ng
ch-n nCa GLCD m .i1m cLn di chuy1n .>n thu*c vo. Do hm ch-n .Sa
chU Y (hm GLCD_SetYADDRESS xt W trn) chU ch-n .Sa chU trong ph:m
vi 1 nCa LCD, nn chng ta cLn cAp nhAt l:i gi trS câ c*t Col, dng 21 th`c
hiBn viBc ny: Col -= 64*Side. Sau dng 21, gi trS Col .<Xc cAp nhAt l:i t;
0 .>n 63 v .<Xc ch-n lm c*t khi hmGLCD_SetYADDRESS(Col) W
dng 22 .<Xc g-i. CuRi cng l ch-n .Sa chU X W dng
23:GLCD_SetXADDRESS(Line).
Hm void GLCD_Clr(void) xa ton b* mn hnh GLCD (c2 2 nCa
GLCD). M5u chRt câ viBc xa GLCD l vi>t gi trS 0 vo t5t c2 cc vS tr
trong RAM, cu lBnh: GLCD_WriteDATA(0) W 2 dng 29 v 33 th`c hiBn
.i/u ny. Qu trnh xa .<Xc th`c hiBn trn t;ng chip KS0108, c 2 vng
vDp for .<Xc dng l v th>, ch dng lBnh
28: GLCD_GotoXY(Line,0) .<a con tr_ v/ c*t .Lu câ page thG Line,
nCa tri GLCD. Trong khi ., dng lBnh 32: GLCD_GotoXY(Line,64) .<a
con tr_ v/ c*t .Lu câ page thG Line, nCa ph2i GLCD (c*t 64 câ GLCD
l c*t .Lu tin câ nCa bn ph2i).
List 6. Cc ch<@ng trnh con mW r*ng (tt)..
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by l 3 ch<@ng trnh con cuRi cng trong th< viBn myGLCD. Trong .
c 2 hm in cc k c kch th<?c 7x8 (7 c*t, 8 dng) .<Xc .Snh ngh\a trong
b2ng font v 1 hm in ton b* mn hnh GLCD v?i m*t hnh kch th<?c
128x64.
Hm void GLCD_PutChar78(uint8_t Line, uint8_t Col, uint8_t
chr) cho php in k t` c m ascii l bi>n chr, bi>n Line l .Sa chU X (0
.>n 7) v bi>n Col l .Sa chU c*t Y (0 .>n 127). PhLn phGc t:p nh5t trong
ch<@ng trnh con ny l viBc xt tr<Qng hXp c s` chuy1n bn (tri qua ph2i)
khi in. V mYi k t` .<Xc .Snh ngh\a bZng 7 bytes trong b2ng font, t<@ng
Gng v?i 7 c*t trn GLCD, n>u chng ta muRn in k t` t:i vS tr 60 trn
GLCD, cc byte thG 0 1, 2, 3 nZm W vS tr c*t 60, 61, 62 v 63 câ nCa tri
trong khi cc byte thG 4, 5 v 6 l:i nZm W cc c*t 0, 1 v 2 câ nCa bn ph2i.
Chng ta ph2i nhAn ra s` chuy1n bn ny .1 chuy1n chip KS0108 cLn thao
tc. Chng ta chia qu trnh in ra 2 tr<Qng hXp, tr<Qng hXp c s` chuy1n bn
v tr<Qng hXp cn l:i khng chuy1n bn (k t` nZm tr-n bn tri hoDc ph2i).
C5u trc If dng trong dng 4 ki1m tra xem c s` chuy1n bn x2y ra hay
khng: if ((Col>57) && (Col<64)), n>u c*t Col l?n h@n 57 v nh_ h@n 63
th sc c m*t s` chuy1n bn x2y ra (v 1 k t` chi>m 7 c*t trn GLCD). Chia
qu trnh in thnh 2 vng lDp for, vng for thG nh5t (dng 6) in t; vS tr Col
.>n vS tr c*t câ nCa tri v vng lDp for thG 2 W dng 9 in t; c*t .Lu tin
câ nCa GLCD bn ph2i .>n byte cuRi cng câ k t` cLn in. Tr<Qng hXp
ng<Xc l:i, khng c s` chuy1n bn x2y ra, chng ta in bnh th<Qng (xem cc
dng t; 12 .>n 15). Ch l d[ liBu ghi vo GLCD l5y t; b2ng font7x8
.<Xc .Snh ngh\a trong file font.h, b2ng font .<Xc vi>t sdn trong b* nh?
FLASH câ AVR, viBc .-c n*i dung FLASH th`c hiBn bZng hm
pgm_read_byte, b:n xem l:i bi .i/u khi1n ma trAn LED .1 hi1u thm.
Hm void GLCD_Print78(uint8_t Line, uint8_t Col, char* str) cho
php in m*t chuYi k t` hay 1 cu ln GLCD, hm ny c7ng giRng hm in
chuYi m chng ta . th`c hiBn trong tr<Qng hXp câ Text LCD (modified
code), m*t .i1m khc ti thm vo l cho phep xuRng dng n>u cu cLn in
v<Xt qu 1 dng. Cc cu lBnh bn trong .i/u kiBn if (dng 23 .>n 27) th`c
hiBn xuRng dng n>u cLn thi>t. Qu trnh in sau . diIn ra bnh th<Qng bZng
cch g-i hm GLCD_PutChar78.
CuRi cng l hm void GLCD_PutBMP(char *bmp) th`c hiBn in m*t
hnh c kch th<?c 128x64 .<Xc .Snh ngh\a tr<?c ln ton b* mn hnh
GLCD (in .). Qu trnh in c7ng kh .@n gi2n v?i viBc .-c n*i dung hnh
trong FLASH v gWi .>n GLCD. CLn chia thnh 2 qu trnh in cho 2 nCa tri
v ph2i (2 vng lDp for trong 2 dng 38 v 43). D[ liBu hnh .<Xc ghi trong
FLASH c .Snh kch th<?c 128x8 pages= 1024 bytes, .Snh d:ng l 1 m2ng
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c 1024 phLn tC, mYi phLn tC l 1 con sR d:ng byte, mYi sR t<@ng Gng 8
ch5m câ 1 c*t trong 1 page. Cc con sR .<Xc sMp x>p thnh 8 dng t<@ng
Gng 8 pages, mYi dng c 128 phLn tC t<@ng Gng 128 c*t GLCD.
GLCD c kh2 nKng ty bi>n hi1n thS cao, . l c@ h*i cho b:n th1 hiBn
s` sng t:o ~, trong th< viBn myGLCD ti chU trnh by m*t sR ch<@ng trnh
con c@ b2n, phLn cn l:i thu*c v/ b:n. Hy sC dHng cc hm truy xu5t trong
myGLCD .1 vi>t cc ch<@ng trnh con hi1n thS khc nh< vc .<Qng thFng,
.<Qng trn, hm sine, cosine hay b5t kN hm sR noHope to hear from
you soon.
IV. V d5 =iTu khiGn Graphic LCD bMng th9 vi0n myGLCD.
PhLn ny ti sc minh h-a cch sC dHng th< viBn myGLCD.h .1 in tr`c
ti>p d[ liBu ln GLCD, hi1n thS cc k t` trong b2ng font7x8 v hnh 2nh ln
GLCD. SC dHng phLn m/m Proteus vc m*t m:ch .iBn gPm 1 GLCD 128x64
(keyword: LGM12641BS1R), 1 chip Atmega32 v 1 bi>n trW (keyword:
POT-LIN) nh< trong hnh 6. T:o 1 Project bZng WinAVR c tn l
myGLCD v t:o file source l main.c, t:o Makefile v?i khai bo s[ dHng
chip ATmega32 v clock 8MHz. Copy file myGLCD.h v font.h vo th<
mHc câ Project m?i t:o. Vi>t code cho file main.c nh< trong list 7. Ch
cc .Snh ngh\a chn k>t nRi v?i LCD trong phLn .Lu file myGLCD.h ph2i
giRng v?i k>t nRi thAt trong hnh 6.
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Hnh 6. M:ch .iBn m ph_ng Graphic LCD v?i AVR.
List 7. Ch<@ng trnh demo giao ti>p GLCD.
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b1 sC dHng th< viBn myGLCD, chng ta cLn include file myGLCD.h
vo Project nh< trong dng 4, #include "myGLCD.h". Hai dng 9 v 10 th`c
hiBn khWi .*ng v xa LCD. Ti th`c hiBn 4 demo in ln GLCD. Trong cc
dng t; 12 .>n 17 th`c hiBn ghi tr`c ti>p gi trS ln GLCD bZng
hm GLCD_WriteDATA, k>t qu2 l 1 dy cc ch5m c .* r*ng 8 bit nZm W
page 4 câ GLCD (xem hnh bn d<?i). Ch l .1 in h>t c2 chi/u ngang
câ GLCD cLn th`c hiBn 2 lLn in trn 2 nCa GLCD.

Cc dng lBnh t; 21 .>n 27 th`c hiBn in 97 k t` trong b2ng font7x8 bMt
.Lu bZng m ascii 33 (k t` !), bi>n Line l .Sa chU page .<Xc khWi t:o
bZng 0 khi khai bo trong dng 7. Bi>n Col l .Sa chU c*t, Col c7ng .<Xc
khWi t:o bZng 0. Dng 32 in k t` c m i ln GLCD t:i vS tr page=Line,
c*t=Col. Sau khi m*t k t` .<Xc in, Col sc .<Xc tKng ln 8 vS tr (dng
24), chng ta dnh 8 c*t trn GLCD cho m*t k t` 7x8 .1 trnh cc k t`
dnh v?i nhau. N>u Col l?n h@n 127 th m*t qu trnh xuRng dng cLn
th`c hiBn, khi . reset Col v/ 0 v tKng bi>n Line thm 1 (dng 25). Cc k
t` sc .<Xc in lLn l<Xt trn GLCD v?i 1 kho2ng delay.
Cc dng t; 31 .>n 35 m t2 cch dng hm GLCD_Print78 .1 in cc
chuYi k t` hay cc cu. Dng 23 in t; code ln GLCD t:i vS tr page=4,
c*t=20. Ch hm sprintf trong dng 33, .y l m*t hm câ ngn ng[ C,
hm ny cho php chuy1n m*t sR thnh m*t chuYi cc k t`, trong v dH ny
ti th`c hiBn chuy1n sR 8205 thnh chuYi 8205, k>t qu2 chGa trong bi>n
dis, bi>n ny l 1 m2ng cc k t` hay con tr_ .>n m2ng cc k t`. Sau .,
dng 34 in chuYi dis ln GLCD.
Demo cuRi cng l in 1 hnh 128x64 ln GLCD bZng
hm GLCD_PutBMP(hiGLCD) v sau . th`c hiBn animation (m*t ki1u
ho:t hnh) bZng hm GLCD_StartLine. Dng 38 in m*t hnh c tn hiGLCD
.<Xc .Snh ngh\a tr<?c trong file font.h ra GLCD. Cc dng 40 .>n 44 cu*n
mn hnh GLCD ln trn .1 th`c hiBn animation. Bi>n i l bi>n offset .<Xc
cho ch:y t; 1 .>n 63, sau mYi lLn cu*n chng ta delay m*t kho2ng thQi gian
ngMn .1 th5y GLCD cu*n.
Hy tham kh2o thm bi gi?i thiBu phLn m/m G.Edit .1 bi>t cch t:o code hnh
2nh cho Graphic LCD
Ntinside 199
C cho AVR

Nh< ti . trnh by W cc bi h-c tr<?c, khi b:n . hi1u AVR, .1 th`c hiBn cc Gng dHng, b:n c th1 khng nh5t
thi>t ph2i lun lAp trnh bZng Assembly(ASM). Ngn ng[ c5p cao nh< C sc gip cho b:n xy d`ng cc Gng dHng
nhanh chng v dI dng h@n, tuy nhin khng v th> m b:n qun ASM, lAp trnh bZng C k>t hXp ASM l gi2i
php hay nh5t. M*t ch l chng ta chU sC dHng C .1 .@n gi2n ha lAp trnh tnh ton, c5u trc .i/u khi1nlAp
trnh C cho AVR khng c ngh\a l b:n khng cLn bi>t c5u trc v cch thGc ho:t .*ng câ chip. Ti khng c
.Snh ni v/ ngn ng[ C W .y nh<ng chU gi?i thiBu m*t cch c@ b2n nh5t v/ cch vi>t ch<@ng trnh cho AVR
bZng C, cH th1 l C trong avr-gcc. b1 c th1 hi1u v vi>t nh[ng ch<@ng trnh phGc t:p h@n, b:n cLn t` trang bS
ki>n thGc v/ C, ti liBu ny sc khng gip b:n phLn .. Tuy nhin, n>u b:n ch<a t;ng lAp trnh bZng C th b:n
c7ng yn tm .-c ti liBu ny, v t ra ti sc gi2i thch nh[ng g ti vi>t.
I. MDt sI khi ni0m C cho AVR.
M*t ch<@ng trnh C cho AVR th<Qng bao gPm cc thnh phLn nh<: ch thch (comments), bi1u thGc
(expressions), cu lBnh (statements), khRi (blocks), ton tC, c5u trc .i/u khi1n (Flow controls), hm
(functions)
Ch thch (comments): c 2 cch .1 t:o phLn ch thch trong C l ch
thch t;ng dng bZng 2 d5u // nh< trong dng .Lu câ .o:n v dH //day la
chu thich, khong duoc bien dich hoDc ch thch block bZng cch kip block
cLn ch thch vo gi[a /* .*/ v dH:
/*
Ban co the type bat ky chu thich nao trong block nay
Ngay ca khi ban xuong dong
Phan chu thich thuong co mau chu la green
*/
TiTn xU l (preprocessor): l m*t tiBn ch câ ngn ng[ C, cc
preprocessor .<Xc trnh bin dSch xC l tr<?c t5t c2 cc phLn khc, cc
preprocessor c chGc nKng t<@ng t` cc Directive trong ASM cho AVR.Cc
preprocessor .<Xc bMt .Lu bZng d5u #, trong sR cc preprocessors trong
ngn ng[ C c hai preprocessors .<Xc sC dHng phe bi>n nh5t
l #include v#define. Preprocessor #include chU .Snh 1 file .<Xc .nh km
trong qu trnh bin dSch (t<@ng .<@ng .INCLUDE trong ASM)
v #define .1 .Snh ngh\a 1 chuei thay th> hoDc 1 macro. Xem cc v dH sau:
#include /*.nh km n*i dung file io.h trong lc bin dSch (file io.h nZm
trong th< mHc con avr câ th< mHc include trong th< mHc ci .Dt câ
WinAVR).*/
#define max (a,b) ((a)>(b)? (a): (b)) /*.Snh ngh\a m*t macro tm sR l?n
nh5t trong 2 sR a v b, trong ch<@ng trnh n>u b:n g-i x=max(2,3) th
k>t qu2 thu .<Xc x=3.*/
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BiGu thOc (Expressions): l 1 phLn câ cc cu lBnh, bi1u thGc c th1
bao gPm bi>n, ton tC, g-i hm, bi1u thGc tr2 v/ 1 gi trS .@n. Bi1u thGc
khng ph2i l 1 cu lBnh hon chUnh. V dH: PORTB=val.
Cu l0nh (Statement): th<Qng l 1 dng lBnh hon chUnh, c th1 bao gPm
cc keywords, bi1u thGc v cc cu lBnh khc v .<Xc k>t thc bZng d5u ;.
V dH: unsigned char val=1; val*=2; l cc cu lBnh.
KhIi (Blocks): l s` k>t hXp câ nhi/u cu lBnh .1 th`c hiBn chung 1
nhiBm vH no ., khRi .<Xc bao bWi 2 d5u mW khRi { v .ng khRi }: v
dH 1 khRi:
while(1){
PORTB=val;
val*=2;
if (!val) val=1;
}
Ton tU (Operators): l nh[ng k hiBu bo cho trnh bin dSch cc
nhiBm vH cLn th`c hiBn, cc b2ng bn d<?i tm tMt cc ton tC C dng cho
lAp trnh AVR:
B@ng 1 cc ton tU =3i sI: dng th`c hiBn cc php ton .:i sR quen
thu*c, trong . .ng ch l cc ton tC ++ (tKng thm 1) v -- (b?t .i
1), ch phn biBt y=x++ v y=++x, v dH ta c x=3 trong khi y=x++
ngh\a l gn x cho y rPi sau . tKng x thm 1, .i/u ny khng 2nh h<Wng
.>n y (cuRi cng y=3, x=4) trong khi y=++x ngh\a l tKng x tr<?c rPi m?i
gn cho y (cuRi cng y=x=4), t<@ng t` cho cc tr<Qng hXp câ ton tC -- .

Ntinside 201
B@ng 2 Ton tU truy c]p v kch thOc: ton tC [] th<Qng .<Xc sC
dHng khi b:n dng m2ng trong lc lAp trnh, phLn tC thG câ m2ng sc .<Xc
truy xu5t thng qua [i], ch m2ng trong C bMt .Lu t; 0.

B@ng 3 Ton tU Logic v quan h0: th`c hiBn cc php so snh v
logic, th<Qng .<Xc dng lm .i/u kiBn trong cc c5u trc .i/u khi1n, ch
ton tC so snh bZng ==, ton tC ny khc v?i ton tC gn =, trong khi y
= x ngh\a l l5y gi trS câ x gn cho y th (y== x) ngh\a l n>u y bZng x.

B@ng 4 Ton tU thao tc Bit (Bitwise operator): l cc ton tC th`c
hiBn trn t;ng bit nhS phn câ cc con sR, cc ton tC dSch tri r5t th<Qng
.<Xc sC dHng khi sC l sR.
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B@ng 5 cc ton tU khc: l 1 sR ton tC .Dc biBt r5t hay sC dHng
nh<ng chng ta th<Qng khng .1 v vai tr câ chng r5t dI nhAn th5y.
bDc biBt ch ton tC ?: l 1 ton tC r5t .Dc biBt câ C so v?i cc ngn
ng[ lAp trnh khc, ?: l ton tC 3 ngi duy nh5t c th1 dng thay th> cho
c5u trc if .@n gi2n.

II. CLu trc =iTu khiGn v hm.
2.1 C?u trc $i7u khi;n (Flow Controls).
Cc c5u trc .i/u khi1n bi>n t<Wng câ b:n thnh hiBn th`c. M*t sR c5u
trc .i/u khi1n c@ b2n trong C nh< sau:
If (=iTu ki0n) statement;: n>u .i/u kiBn l .ng th th`c hiBn
statement theo sau, statement c th1 .<Xc trnh by cng dng hoDc dng
sau .i/u khi1n If. bi/u kiBn c th1 l m*t bi1u thGc b5t kN, c th1 l s` k>t
hXp câ nhi/u .i/u kiBn bZng cc ton tC quan hB AND (&&), OR (||)bi/u
kiBn .<Xc cho l .ng khi n khc 0, v dH if (1) th .i/u kiBn hi1n nhin l
.ng. Xt m*t vi v dH dng c5u trc if nh< sau:
If (!val) val=1; ngh\a l n>u val bZng 0 th ch<@ng trnh sc gn cho val
gi trS l 1, ! l ton tC NOT, NOT câ m*t sR khc 0 th bZng 0, ng<Xc
l:i, NOT câ 0 th thu .<Xc k>t qu2 l 1. Trong v dH ny, n>u val bZng 0 th
!val sc bZng 1, nh< th> .i/u kiBn sc trW thnh .ng v cu lBnh val=1 .<Xc
th`c thi.
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If (x==1 && y==2) result=A; ngh\a l n>u x bZng 1 v y bZng 2 th gn
k t` A cho bi>n result. Trong v dH ny, ton tC logic && .<Xc sC dHng
.1 nRi 2 .i/u kiBn l:i, b:n hon ton c th1 sC dHng nhi/u ton tC logic
khc n>u cLn thi>t.
Trong tr<Qng hXp b:n muRn th`c thi nhi/u cu lBnh cng lc n>u m*t
.i/u kiBn no . th_a th b:n cLn .Dt t5t c2 cc cu lBnh . trong 1 khRi nh<
bn d<?i:
If (.i/u kiBn) {
Statement1;
Statement2;

}
If (=iTu ki0n ) statement1; else statement2; : n>u .i/u kiBn .ng th
th`c hiBn statement1, ng<Xc l:i th`c thi statement2. ViBc .Dt cc statement
v else..trn cng 1 dng hay trn nh[ng dng khc nhau ./u khng 2nh
h<Wng .>n k>t qu2. T<@ng t` tr<Qng hXp trn, n>u c nhi/u statements th
cLn .Dt chng trong 1 khRi.
If (.i/u kiBn) {
Statement1;
Statement2;

}else {
Statement1;
Statement2;

}
Ngoi ra, b:n c7ng c th1 .Dt nhi/u c5u trc ifelse lPng vo nhau.
CLu trc switch: trong tr<Qng hXp c nhi/u kh2 nKng c th1 x2y ra cho 1
bi1u thGc (hay 1 bi>n), Gng v?i mYi kh2 nKng b:n cLn ch<@ng trnh th`c hiBn
m*t viBc no ., khi ny b:n nn sC dHng c5u trc switch. C5u trc ny
.<Xc trnh by nh< bn d<?i.
switch (bi1u thGc) {
case hZng_sR_1:
cc statement1;
break;
case hZng_sR_2:
cc statement2;
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break;

default:
cc statement khc;
}
Hy xt 1 v dH b:n k>t nRi 2 chip AVR v?i nhau, 1 chip lm Master sc ra
cc lBnh .i/u khi1n chip Slaver, chip Slaver nhAn m lBnh t; Master v th`c
hiBn cc cng viBc .<Xc tho2 hiBp tr<?c. Gi2 sC m lBnh .<Xc ln
Command, d<?i .y l ch<@ng trnh v dH cch xC l câ chip Slaver Gng v?i
t;ng m lBnh.
switch (Command) {
case 1:
PWM=255;
ON_Motor();
break;
case 2:
PWM=0;
OFF_Motor();;
break;

default:
Get_Cmd();
break;
}Ngoi ra, b:n c7ng c th1 .Dt nhi/u c5u trc ifelse lPng vo nhau.
N>u Command=1, gn gi trS 255 cho bi>n PWM v g-i ch<@ng trnh con
ON_Motor(). Trong tr<Qng hXp ny, break .<Xc sC dHng, break ngh\a l
thot kh_i c5u trc .i/u khi1n hiBn t:i ngay lAp tGc, nh< vAy sau khi th`c
hiBn 2 lBnh, switch k>t thc m khng cLn xt .>n cc tr<Qng hXp khc. By
giQ, n>u Command=2, gn gi trS 0 cho bi>n PWM v g-i ch<@ng trnh con
OFF_Motor(), trong t5t c2 cc tr<Qng hXp cn l:i (default), th`c hiBn
ch<@ng trnh con Get_Cmd().
while (=iTu ki0n ) statement1;: l m*t c5u trc lDp (Loop), ngh\a câ
c5u trc while l khi .i/u kiBn cn .ng th sc th`c hiBn statement1 (hoDc
cc statements n>u chng .<Xc .Dt trong 1 khRi {} nh< trong tr<Qng hXp câ
if .<Xc gi?i thiBu W trn). C]n thAn, b:n r5t dI r@i vo m*t vng lDp khng
lRi thot v?i while n>u .i/u kiBn lun lun .ng.
for (biGu_thOc_1; biGu_thOc_2; biGu_thOc_3) statement;: l m*t c5u
trc lDp khc, trong c5u trc for, bi1u_thGc_1 th<Qng .<Xc hi1u l khWi t:o,
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bi1u_thGc_2 l .i/u kiBn v bi1u_thGc_3 l bi1u thGc .<Xc th`c hiBn sau.
C5u trc for ny t<@ng .<@ng v?i c5u trc while sau:
bi1u_thGc_1;
while (bi1u_thGc_2){
statement;
bi1u_thGc_3;
}
Cc bi1u thGc trong c5u trc for c th1 vMng mDt trong c5u trc nhung
cc d5u ; th khng .<Xc b_. N>u b:n vi>t for( ; ; ) t<@ng .<@ng v?i vng
lDp v tAn while (1).
C5u trc for th<Qng .<Xc dng .1 th`c hiBn 1 hay nh[ng cng viBc no
. trong sR lLn no ., v dH bn d<?i th`c hiBn xu5t cc gi trS t; 0 .>n 200
ra PORTB, sau mYi lLn xu5t sc g-i lBnh delay trong 65000 chu kN my.
for (uint8_t i=0; i<=200; i++){
PORTB=i;
}
Ch , b:n c th1 th`c hiBn viBc khai bo 1 bi>n (xem phLn khai bo bi>n
bn d<?i) ngay trong c5u trc for n>u bi>n lLn .Lu .<Xc sC dHng. V dH trn
.<Xc hi1u nh< sau: khai bo 1 bi>n i ki1u byte khng m, gn gi trS khWi
.Lu cho i=0 (chU th`c hiBn 1 lLn duy nh5t), ki1m tra .i/u kiBn i<=200 (nh_
h@n hoDc bZng 200), n>u .i/u kiBn cn .ng, th`c hiBn 2 statements trong
block {}, sau . quay v/ .1 th`c hiBn i++ (tKng i thm 1) rPi l:i ki1m tra
.i/u kiBn i<=200 v qu trnh lDp l:i. Nh< th> .o:n code trong {} .<Xc th`c
thi kho2ng 201 lLn tr<?c khi bi>n i bZng 201 v .i/u kiBn i<=200 sai.
2.2 Hm (Functions).
Ngn ng[ C bao gPm tAp hXp câ r5t nhi/u hm, mYi hm th`c hiBn m*t
chGc nKng cH th1, cc hm trong C th<Qng .<Xc thi>t k>t r5t nh_ g-n, .1 c
cc hm phGc t:p ng<Qi dng cLn t` t:o ra. Hm C cho AVR .<Xc .Snh
ngh\a trong th< viBn avr-libc, ngoi cc hm C thng th<Qng, avr-libc cn
chGa r5t nhi/u cc hm ring dng ring cho chip AVR, cc hm ny .<Xc
khai bo trong cc file header ring, .1 sC dHng hm no, b:n cLn #include
file header t<@ng Gng (tham kh2o ti liBu avr-libc user manual .1 bi>t
thm chi ti>t, trong ti liBu ny, khi cLn sC dHng m*t hm no ti sc ni r
file header cLn thi>t).
V dH: _delay_loop_2(65000) l m*t hm .<Xc .Snh ngh\a trong file
delay.h (trong th< mHc C:\WinAVR\avr\include\util), hm ny th`c hiBn
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viBc delay kho2ng 65000 chu kN my. C 4 hm delay b:n c th1 sC dHng
sau khi include file . l:
_delay_loop_1(uint8_t __count) : delay theo m*t sR lLn chu kN my
nh5t .Snh (bi>n __count), sR l<Xng chu kN delay l sR 8 bit (t; 0 .>n 255).
_delay_loop_2(uint16_t __count) : delay theo m*t sR lLn chu kN my
nh5t .Snh (bi>n __count), sR l<Xng chu kN delay l sR 16 bit (t; 0 .>n
65535).
(Ch : th`c ch5t 2 hm delay trn .<Xc .Snh ngh\a trong file header
delay_basic.h).
_delay_us(double __us): delay 1 microsecond.
_delay_ms(double __ms): delay 1 milisecond.
Ch : .1 dng 2 hm _delay_us v _delay_ms cLn .Snh ngh\a tLn sR
xung clock trong Makefile (bi>n F_CPU), sC dHng 2 hm ny tr`c ti>p
th<Qng cho k>t qu2 khng nh< mong muRn, ti sc trnh by cch sC dHng 2
hm ny trong v dH bn d<?i.
Main: m*t ch<@ng trnh C cho AVR ph2i bao gPm 1 ch<@ng trnh chnh
main, t5t c2 cc n*i dung chnh sc .<Xc .Dt bn trong ch<@ng trnh chnh.
C5u trc ch<@ng trnh chnh c th1 nh< sau:
int main(void){
//noi dung chinh
return 0; //gia tri tra ve cho chuong trinh chinh
}
Trong ., int l ki1u gi trS tr2 v/ câ main, t; kha void ni rZng ch<@ng
trnh chnh câ chng ta khng cLn b5t kN tham sR no km theo.
Cn r5t nhi/u cc v5n ./ lin quan .>n C cho AVR, chng ta sc tm hi1u
trong lc vi>t cc v dH cH th1.
III. V d5 minh hRa.
b1 minh h-a cc khi niBm v ph<@ng php lAp trnh C cho AVR, ti sc
gi2i thch v dH qut LED vi>t bZng C m chng ta th`c hiBn trong bi h<?ng
dan WinAVR. bo:n code .<Xc trnh by trong List 1.
List 1. v dH qut LED bZng C.

//file: main.c
//Description: AVR1 by GCC, "Cung hoc AVR" Series
#include <avr/io.h>
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10
11
12
13
14
15
unsigned char val=1;
int main(void){
DDRB=0xFF; //set PORTB as output lines
while(1){
PORTB=val;
val*=2;
if (!val) val=1;
}
return 0;
}
Tr<?c h>t l preprocessor .nh km cc file khi bin dSch, #include l
.nh km file header io.h, file ny th`c ra khng ph2i l file chGa cc thng
tin v/ chip nh<ng n sc lm m*t nhiBm vH trung gian l .nh km 1 file khc
t<@ng Gng v?i bi>n MCU trong Makefile, v dH trong
Makefile, MCU=atmega8 th dng #include .<Xc th`c thi,
file iom8.h .<Xc t` .*ng .nh km km vo v file iom8.h m?i th`c ch5t
chGa cc .Snh ngh\a cho chip ATmega8 (cc .Snh ngh\a v/ .Sa chU thanh ghi,
kch th<?c b* nh?,). bi/u ny gip b:n khng cLn nh? h>t t5t c2 cc file
header câ t;ng chip AVR. N>u khng an tm, b:n c th1 thm
dng #include iom8.h sau khi include io.h (=iTu ny khng th]t sX c>n
thiQt). Ngoi ra, mî l>n include file io.h sE c 4 file header khc =9Wc tX
=Dng =nh km l avr/sfr_defs.h, avr/portpins.h, avr/common.h,
v avr/version.h. Tm l3i b3n c>n (hoZc ph@i) include file io.h v khai
bo lo3i chip AVR trong file Makefile (dng MFile, nh9 h9-ng d`n C
trn) l c thG an tm viQt ch9.ng trnh C cho AVR.
- Dng thG 4 include file header delay.h .1 sC dHng lBnh delay nh< . ./
cAp W trn.
- Dng 5 : khai bo 1 bi>n tn val trong b* nh? SRAM, ki1u câ val l
unsigned char l ki1u d[ liBu 8 bit khng d5u c kho2ng gi trS t; 0 .>n 255.
Bi>n val .<Xc dng lm bi>n t:m .1 chGa gi tr<?c khi xu5t ra PORTB.
Bi>n trong C .<Xc khai bo bZng cch .Dt ki1u bi>n tr<?c sau . tn bi>n.
M*t sR kiu d[ liBu c@ b2n trong C .<Xc tm tMt trong b2ng 6.
B2ng 6 cc ki1u d[ liBu trong C.
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Tn kiGu dP li0u
(Data type)
SI byte Kho@ng dP li0u (Range)
char 1 127 to 127 or 0 to 255
unsigned char 1 0 to 255
signed char 1 127 to 127
int 2 32,767 to 32,767
unsigned int 2 0 to 65,535
signed int 2 Nh< ki1u int
short int 2 Nh< ki1u int
unsigned short int 2 0 to 65,535
signed short int 2 Nh< ki1u short int
long int 4 2,147,483,647 to
2,147,483,647
signed long int 4 Nh< ki1u long int
unsigned long int 4 0 to 4,294,967,295
long long int 8 (2
63
1) to 2
63
1 (C99 only)
signed long long int 8 same as long long int (C99
only)
unsigned long long
int
8 0 to 2
64
1 (C99 only)
float 4 6 digits of precision
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Tn kiGu dP li0u
(Data type)
SI byte Kho@ng dP li0u (Range)
double 8 10 digits of precision
long double 12 10 digits of precision
M*t sR ki1u d[ liBu thng dHng nh5t l char (1 byte), int (2 byte) v float.
T; kha unsigned .<Xc thm tr<?c 1 ki1u d[ liBu nguyn .1 chU .Snh cc sR
nguyn d<@ng, khi . kho2ng gi trS nguyn sc .<Xc tKng ln gLn 2 lLn. V
dH char chU cc sR nguyn t; -127 .>n 127 th<Qng .<Xc dng .1 chU m
ASCII câ cc k t` trong b2ng m ASCII, nh<ng unsigned char sc bao gPm
cc sR nguyn d<@ng t; 0 .>n 255 v th<Qng .<Xc dng khi lm viBc v?i
cc thanh ghi 8 bit.
Ngoi ra, avr-libc cn .Snh ngh\a m*t sR ki1u d[ liBu thay th>, chng ta c
th1 dng cc ki1u d[ liBu ny thay cho cc ki1u thng th<Qng, xem tm tMt
nh< bn d<?i.

M*t khai bo uint8_t val t<@ng .<@ng usigned char val, sC dHng ki1u
khai bo no l do thi quen câ ng<Qi sC dHng. Ch l theo mDc .Snh,
m*t bi>n m?i .<Xc khai bo theo cch thng th<Qng nh< trn sc .<Xc .Dt
trong SRAM, nh< cc b:n . bi>t SRAM trong AVR t<@ng .Ri nh_ v th>
nn khai bo v sC dHng hXp l bi>n, .;ng khai bo qu nhi/u bi>n n>u b:n
khng sC dHng h>t, .;ng khai bo ki1u bi>n qu l?n so v?i gi trS thAt sC
dHng, tuy nhin c7ng khng .<Xc khai bo ki1u d[ liBu c kch th<?c qu
nh_ so v?i gi trS m bi>n . c th1 v<@n t?i. SC dHng b* nh? ch<@ng trnh
(flash program memory) .1 lt kiBm b* SRAM, ti sc ./ cAp v5n ./ ny trong 1 bi khc.
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CuRi cng v/ viBc khai bo bi>n, m*t bi>n c th1 .<Xc gn gi trS khWi t:o
ngay lc khai bo nh< trong tr<Qng hXp câ chng ta, bi>n val=1 lc .<Xc
khai bo.
- Dng 6 int main(void){ bMt .Lu ch<@ng trnh chnh.
- Dng 7: DDRB=0xFF gn gi trS hexadecimal 0xFF (11111111) cho
thanh thi .i/u khi1n câ Port B, DDRB, Port B khi . sc trW thnh Port xu5t
- Dng 8 while (1){: bMt .Lu 1 vng lDp v tAn.
- Dng 9 v dng 10: xu5t val ra PORTB v g-i lBnh delay.
- B:n cLn ch 11 v 12, 2 dng ny c chGc nKng xoay gi trS câ bi>n
val .1 xu5t ra PORTB t:o hiBu Gng xoay vng.val*=2 .<Xc hi1u
l val=val*2, .y l 1 ki1u vi>t thu g-n câ C, n>u ton h:ng thG nh5t v k>t
qu2 tr2 v/ l cng 1 bi>n, chng ta c th1 b_ b?t 1 tn bi>n v di chuy1n ton
tC v/ bn ph2i ton tC gn =. V dH: i = i + 6 .<Xc rt g-n thnh i + = 6.

Nh< th> sau cu lBnh val*=2 gi trS câ val .<Xc tKng ln 2 lLn. ngh\a
thAt s` câ viBc g5p .i bi>n val l g? Hy nhn vo gi trS nhS phn câ val,
lc khai bo val, chng ta gn cho val = 1 hay val = 00000001 (nhS phn),
sau khi g5p .i lLn thG nh5t, val = 2=00000010, ti>p tHc g5p .i lLn thG hai,
val = 4=00000100c th1 b:n . th5y chuyBn g x2y ra? by l cu tr2 lQi:
trong thao tc v?i sR nhS phn, g5p .i m*t sR ngh\a l di chuy1n sR . sang
tri 1 vS trQu trnh g5p .i sc ti>p diIn .>n lc val = 128=10000000,
n>u ti>p tHc g5p .i, b:n ngh\ val = 256 ? Tuy nhin b:n nh? rZng chng ta
. khai bo bi>n val c ki1u unsigned char (8 bits), trong khi .
256=100000000 (9 bits), n>u gn val = 256, chU c 8 bits th5p (00000000)
câ 256 sc .<Xc gn cho val, k>t qu2 l val = 0. Ni m*t cch khc, sau khi
val=128, val = 0, cu lBnh: if (!val) val=1; sc gip cho qu trnh qut lDp
quay l:i t; .Lu n>u val = 0. M-i thG . r.
CuRi cng v ch<@ng trnh chnh câ chng ta c ki1u int (int main)
chng ta cLn tr2 v/ m*t gi trS no ., return 0; th`c hiBn tr2 v/ 0 (b:n
c th1 tr2 v/ gi trS no ty ).

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Thi#t l)p Fuse Bits

AVR c m*t sR m:ch .iBn hay cc thi>t bS hY trX bn trong, viBc .i/u
khi1n cc m:ch .iBn ny .<Xc th`c hiBn thng qua cc Fuse bits. V dH bn
trong cc chip AVR c b* t:o dao .*ng cho chip, muRn hay khng muRn sC
dHng b* t:o dao .*ng ny chng ta sc set cc Fuse bits t<@ng Gng. Nh< th>,
Fuse bits c7ng giRng nh< cc cLu ch hay cc cng tMc cGng nRi AVR
v?i cc m:ch .iBn hY trX. V l cc cng tMc cGng nn chng ph2i .<Xc set
ring biBt, khng set .<Xc bZng lBnh "m/m".
MYi lo:i AVR c sR l<Xng m:ch .iBn hY trX khc nhau v v th> sR
l<Xng Fuse bits sc khc nhau. VS tr cc Fuse bits c7ng khc nhau trn mYi
lo:i AVR tuy nhin tn g-i th nh< nhau. Ti sc dng chip ATmega32 lm
minh h-a. Chip ATmega32 c 16 Fuse bits .<Xc bR tr trong 2 byte g-i l
Fuse High Byte v Fuse Low Byte. VS tr cc Fuse bits khng quan
tr-ng nh<ng tn g-i v chGc nKng th cLn kh2o st. B2ng 1 tm tMt cc bits
trong Fuse High Byte v b2ng 2 tm tMt cc bits trong Fuse Low Byte.
B2ng 1. Fuse High Byte

B2ng 2. Fuse Low Byte
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ba sR cc ch<@ng trnh n:p chip ./u hY trX n:p Fuse bits. Cc Fuse .<Xc n:p .*c lAp .Ri v?i file ch<@ng
trnh. Cc phLn m/m n:p nh< PonyProg, phLn m/m n:p trong CodevisionAVR, Bascom, ICCAVRhY trX set
t;ng Fuse bit m*t trong khi m*t sR ch<@ng trnh nh< avrdude chU hY trX n:p cc byte Fuse, n>u muRn sC dHng
cc ch<@ng trnh n:p ny .1 n:p Fuse b:n cLn tnh ton gi trS 2 byte Fuse tr<?c. M*t ch r5t quan tr-ng l .Ri
v?i cc Fuse bits, gn gi tr7 0 cho 1 Fuse bit .Png ngh\a v?i Fuse bit . .<Xc lAp trnh (programmed), trong
khi 1 ngh\a l khng .<Xc lAp trnh (unprogrammed).
Ti sc sC dHng phLn m/m PonyProg .1 lm minh h-a n:p Fuse bits cho
chip ATmega32. Tr<?c khi n:p Fuse bits b:n cLn ch-n device v lo:i m:ch
n:p trong PonyProg (xem l:i bi M:ch n:p). b1 n:p Fuse bits b:n hy ch-n
menu Command/Security and Configuration Bits hoDc nh5n Ctrl+S
(m:ch n:p ph2i .<Xc nRi sdn v?i my tnh v m:ch AVR). Nh5n nt Read
.1 .-c cc c5u hnh Fuse bits trn chip câ b:n, n>u .y l lLn .Lu tin chip
ATmega32 câ b:n .<Xc n:p Fuse bits th b:n sc thu .<Xc k>t qu2 c5u hnh
cc Fuse bits nh< trong hnh 1.

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Hnh 1. C5u hnh Fuse bits mDc .Snh trn chip ATmega32.
Chng ta sc lLn l<Xt kh2o st cc Fuse bit theo nhm chGc nKng câ chng.
1. JTAGEN (JTAG Enable): trn AVR c tch hXp sdn b* JTAG, . l m*t module giao ti>p v?i phLn cGng
câ chip. Nhn chung, JTAG th<Qng .<Xc dng .1 ki1m tra ho:t .*ng câ chip, trn AVR JTAG th<Qng .<Xc
dng .1 n:p ch<@ng trnh v phe bi>n h@n l Debug lYi ch<@ng trnh (gl rRi ch<@ng trnh). Module JTAG lm
viBc thng qua 4 chn TCK, TMS, TDO v TDI, trn chip ATmega32 4 chn lLn lLn l<Xt l PC2, PC3, PC4 v
PC5. Theo mDc .Snh JTAG .<Xc kch ho:t, bit JTAGEN=0 (programmed) nh< trong hnh 1, v th> v?i cc chip
ATmega32 m?i mua v/, cc chn PC2:5 trn PORTC c th1 khng sC dHng .1 xu5t nhAp thng th<Qng .<Xc.
N>u b:n khng muRn sC dHng chGc nKng Debug tr`c ti>p trn chip th hy uncheck bit JTAGEN(uncheck t<@ng
.<@ng unprogrammed, t<@ng .<@ng JTAGEN=1) .1 dng cc chn JTAG nh< cc chn xu5t nhAp thng
th<Qng.
2. OCDEN (On Chip Debug Enable): AVR cho php chng ta gl rRi
ch<@ng trnh tr`c ti>p trn chip thng qua module JTAG. Bit OCDEN cho
php th`c hiBn Debug trn chip, n>u b:n c m*t m:ch Debug cho AVR nh<
m:ch JTAG ICE câ Atmel (xem bi Debug v?i JTAG ICE) v b:n muRn
debug ch<@ng trnh th hy set bit OCDEN bZng 0 (check vo OCDEN).
B:n cLn nh? rZng, khi lAp trnh cho bit OCDEN th AVR sc ho:t .*ng trong
mode Debug, trong mode ny chip sc W trong tr:ng thi ng^ (Sleep
mode), b:n chU c th1 th`c hiBn Debug m khng th1 ch:y ch<@ng trnh thAt.
Theo mDc .Snh, OCDEN khng .<Xc lAp trnh v ch> .* Debug .<Xc v
hiBu ha. LQi khuyn l b:n nn .1 bit ny unprogrammed tr<?c khi .<a
chip vo sC dHng. (.;ng .Hng vo bit ny n>u b:n khng c .Snh Debug
trn chip).
3. BODEN (Brown-Out Detection Enable) v BODLEVEL(BOD Level): AVR c sdn m*t m:ch .iBn Brown-
Out Detection, hi1u nm na l m:ch pht hiBn sHt .iBn p nguPn, n>u fuse BODEN .<Xc lAp trnh th m:ch
BOD .<Xc kch ho:t, khi . fuse bit BODLEVEL ch-n mGc .iBn p câ BOD, n>u BODLEVEL=1
(unprogrammed) th mGc .iBn p BOD mDc .Snh l 2.7V, ng<Xc l:i n>u BODLEVEL .<Xc lAp trnh th mGc .iBn
p BOD l 4.0V. Khi m:ch BOD .<Xc sC dHng, n>u .iBn p VCC gi2m xuRng th5p h@n mGc .iBn p BOD th 1
Reset BOD x2y ra. N>u khng thAt s` cLn thi>t hy .1 cc bit ny khng .<Xc lAp trnh nh< mDc .Snh. Hnh 2 m
t2 m*t s` kiBn BOD trn AVR.

Hnh 2. S` kiBn BOD trn AVR.
Ntinside 214
4. EESAVE (EEPROM Erase SAVE): n>u bit EESAVE .<Xc lAp trnh (bZng 0), th b* nh? EEPROM sc
khng bS xa khi xa chip, ng<Xc l:i EESAVE =1 (unprogrammed) th EEPROM sc bS xa theo chip.
5. BOOT LOADER: .y l m*t tnh nKng r5t hay trn cc chip AVR m?i (ch khng ph2i dng AVR no
c7ng c Boot Loader), Boot Loader l phLn b* nh? ch<@ng trnh .<Xc kch ho:t .Lu tin khi khWi .*ng chip.
Boot Loader trn cc chip AVR .<Xc bR tr pha d<?i câ b* nh? ch<@ng trnh (xem l:i bi 2, c5u trc AVR).
Boot Loader th<Qng .<Xc sC dHng .1 ghi hoDc .-c n*i dung b* nh? ch<@ng trnh, v th> Gng dHng phe bi>n nh5t
câ n l update ch<@ng trnh cho chip m*t m*t cch nhanh chng m khng cLn m:ch n:p. C@ ch> nh< sau:
-Tr<?c h>t chng ta cLn c 1 ch<@ng trnh Boot Loader .<Xc n:p sdn trong phLn b* nh? Boot Loader (pha
d<?i b* nh? ch<@ng trnh). Ch<@ng trnh ny c kh2 nKng giao ti>p v?i my tnh (thng qua UART chFng
h:n) v .-c, ghi b* nh? ch<@ng trnh câ chip.
-Khi cLn update ch<@ng trnh m?i cho AVR, trn my tnh c 1 ch<@ng
trnh giao ti>p v?i Boot Loader, k>t nRi AVR v?i my tnh, ch<@ng trnh
trn my tnh sc gWi n*i dung cLn update cho AVR, ch<@ng trnh Boot
Loader sc .-c n*i dung ny v ghi vo b* nh? ch<@ng trnh câ AVR.
BZng cch ny chng ta . n:p ch<@ng trnh cho AVR m khng cLn
dng m:ch n:p.
N:p ch<@ng trnh bZng Boot Loader cho php khch hng câ b:n t` cAp nhAt cc chGc nKng m?i m khng
cLn trao chip cho b:n. SC dHng hay khng sC dHng Boot Loader sc .<Xc xc lAp thng qua cc Fuse
bits BOOTRST, BOOTSZ1 vBOOTSZ0.
-BOOTRST (Select Reset Vector) : N>u Fuse bit BOOTRST khng
.<Xc lAp trnh (bZng 1) th khi v;a khWi .*ng chip, con tr_ ch<@ng trnh
sc nh2y .>n vS tr .Lu tin trong ch<@ng trnh (0x0000) .1 lLn l<Xt th`c
thi phLn ch<@ng trnh nh< thng th<Qng. N>u BOOTRST .<Xc lAp trnh
(bZng 0) th vS tr Reset l .Sa chU .Lu câ phLn Boot Loader, khng ph2i
.Sa chU 0x0000 nh< th<Qng lB. Khi . phLn ch<@ng trnh trong Boot
Loader sc .<Xc th`c thi thay cho ch<@ng trnh chnh pha trn (xem hnh
3).

Hnh 3. hnh h<Wng câ Fuse bit BOOTRST.
Ntinside 215
-BOOTSZ1 v BOOTSZ0 (Select Boot Size): kch th<?c phLn b* nh?
dnh cho Boot Loader khng .<Xc .Snh tr<?c, n>u Boot Loader khng
.<Xc kch ho:t (fuse BOOTRST=1) th ton b* b* nh? ch<@ng trnh
dnh cho ch<@ng trnh chnh. Khi Boot Loader .<Xc kch ho:t, 2 Fuse
bits BOOTSZ1 v BOOTSZ0 sc quy>t .Snh kch th<?c Boot Loader.
B2ng 3 tm tMt cc kch th<?c câ phLn Boot Loader phH thu*c vo 2 bit
BOOTSZ1:0. Ch l kch th<?c tnh theo INSTRUCTION WORD, v?i
AVR 1 INSTRUCTION WORD = 2 bytes. Ph2i nhMc l:i .Ri v?i Fuse
bits, gi trS 1 ngh\a l khng .<Xc lAp trnh (khng check trong
PonyProg). N>u bit BOOTRST khng .<Xc lAp trnh th 2 bit BOOTSZ
khng c tc dHng.
B2ng 3. Kch th<?c Boot Loader.

Trong cc Gng dHng lAp trnh thng th<Qng, Boot Loader khng .<Xc quan tm, v th> tRi khuyn b:n nn .1
cc Fuse bit BOOTRST, BOOTSZ1:0 nh< mDc .Snh, khi no cLn sC dHng ti sc ni r (xem bi Debug v?i m:ch
JTAG ICE).
6. ChRn NguVn Xung giP nh7p v thAi gian khCi =Dng (start-up times): by l phLn r5t .<Xc quan tm
khi set Fuse bits. C .>n 7 Fuse bits tham gia vo viBc ny . l 4 bits CKSEL3:0, 2 bis SUT1:0 v bit CKOPT.
Trong . 2 bit SUT1:0 ch^ y>u dng .1 ch-n thQi gian khWi .*ng, phLn ny khng 2nh h<Wng nhi/u trong hLu
h>t cc tr<Qng hXp (t nh5t l cc v dH trong Cng h-c AVR) v th> ti sc b_ qua, chng ta .1 2 fuse bits nh<
mDc .Snh, n>u start-up time thAt s` 2nh h<Wng .>n ch<@ng trnh câ b:n, b:n hy tham kh2o thm phLn System
Clock and Clock Option trong datasheet câ chip. PhLn ny ti ch^ y>u trnh by cch ch-n nguPn xung gi[
nhSp cho chip.
C t5t c2 5 lo:i nguPn xung gi[ nhSp chnh cho chip nh<ng .1 .@n gi2n chng ta chU xt 2 tr<Qng hXp l dng
nguPn th:ch anh ngoi v dng xung gi[ nhSp .<Xc t:o bWi m:ch RC trong chip.
Xung gi[ nhSp trong chip (xung n*i): HLu h>t cc chip AVR .<Xc trang bS 1 m:ch t:o xung gi[ nhSp RC bn
trong, n>u sC dHng nguPn xung gi` nhSp ny chng ta c th1 b_ qua m:ch t:o xung bn ngoi. NguPn xung gi[
nhSp .<Xc t:o ra bn trong chip .<Xc cR .Snh W 1 trong 4 mGc : 1MHz, 2 MHz, 4 Mhz v 8 MHz. Cc Fuse bits
CKSEL3:0 quy>t .Snh viBc ch-n nguPn xung ny. B2ng 4 tm tMt cch phRi hXp cc Fuse bits CKSEL .1 ch-n
nguPn xung n*i.
B2ng 4. Ch-n xung gi[ nhSp n*i bZng cc Fuse bits CKSEL.
Ntinside 216

(Nomial frequency: tLn sR danh ngh\a, gi trS th`c c th1 khc do sai sR)
bRi v?i chip ATmega32, nguPn xung n*i 1MHz .<Xc set mDc .Snh trn cc chip m?i. Xem l:i hnh 1 b:n
th5y CKSEL3=0 (.<Xc checked), CKSEL2=0 (.<Xc checked), CKSEL1=0 (.<Xc checked), CKSEL0=1 (khng
check). Cc hnh 4, 5, 6 v 7 bn d<?i gXi b:n cch ch-n nguPn xung n*i bZng phLn m/m n:p PonyProg, ch
sau khi ch-n cc bits b:n ph2i nh5n bt Write .1 ghi vo chip.

Hnh 4. Ch-n nguPn xung n*i 1MHz (.Png thQi tMt JTAG, Boot Loader,
BOD).

Ntinside 217
BOD).

BOD).

BOD).
Xung gi[ nhSp t; m:ch th:ch anh bn ngoi (Crystal): dng xung n*i c nh<Xc .i1m l t5n sR xung . .<Xc
gi[ cR .Snh trong 4 mGc v t5n sR cao nh5t c th1 .:t l 8MHz trong khi AVR cho php lm viBc W 16Mhz, mDc
khc sai sR c7ng t<@ng .Ri l?n khi xng xung n*i. Dng th:ch anh .1 t:o xung gi[ nhSp l m*t gi2i php tRt, c
th1 t:o m*t m:ch th:ch anh .@n gi2n v nRi v?i 2 chn XTAL1 v XTAL2 câ AVR nh< trong hnh 8.
Ntinside 218

Hnh 8. M:ch t:o xung ngoi bZng th:ch anh.
b1 bo cho AVR bi>t l chng ta muRn sC dHng th:ch anh ngoi lm m:ch t:o xung, hy set cc Fuse bits
CKSEL3:0 thnh 1 trong 2 gi trS: 1111 hoDc 1010 (nhS phn). Trong tr<Qng hXp ny, Fuse bit CKOPT c tc
dHng ch-n gi[a 2 ch> .* khuy>ch .:i, ch> .* CKOPT = 0 (programmed) thch hXp v?i th:ch anh c tLn sR l?n
nh5t l 16MHz v CKOPT=1 (unprorgammed) khi tLn sR th:ch anh nh_ h@n hoDc bZng 8MHz. Cc hnh 9 v 10
gXi cch set Fuse bits .1 ch-n nguPn xung nhSp l m:ch th:ch anh ngoi v?i cc tLn sR l?n nh5t 8MHz v l?n
nh5t 16MHz.

Hnh 9. Ch-n xung gi[ nhSp t; th:ch anh ngoi v?i tLn sR l?n nh5t l
8MHz.
Ntinside 219

Hnh 10. Ch-n xung gi[ nhSp t; th:ch anh ngoi v?i tLn sR l?n nh5t l
16MHz.
Sau khi . ch-n cc Fuse bits, viBc cuRi cng v r5t quan tr-ng l ghi cc Fuse bits ny vo chuip bZng cch
nh5n nt Write (PonyProg).
bRi v?i cc ch<@ng trnh n:p chip khc, Fuse bits c7ng .<Xc set t<@ng t`.

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