EE108a: Verilog Examples

Version 1.0 David Black-Schaffer

Building Counters Veriog Example
here are man! differen" #a!s "o #ri"e code in Verilog "o implemen" "he same fea"$re. %n ee108a !o$ sho$ld
s"rive "o make !o$r code as eas! "o read and de&$g as possi&le.
he co$n"er example in "he &ook ins"an"ia"es a flip flop for s"oring "he co$n"' and "hen $ses a case s"a"emen" "o
&$ild a m$x "o choose "he nex" inp$" "o "he flip flop &ased on "he con"rol signals. (e")s "ake a look a" "#o #a!s
"o #ri"e "his in Verilog.
Example 1:
his is "he $p*do#n co$n"er code from "he co$rse reader:
module UDL_Count1(clk, rst, up, down, load, in, out) ;
parameter n = 4 ;
input clk, rst, up, down, load ;
input [n-1:0] in ;
output [n-1:0] out ;
wire [n-1:0] out ;
reg [n-1:0] next ;
DFF #(n) count(clk, next, out) ;
always@(rst, up, down, load, in, out) begin
casex({rst, up, down, load})
4b1xxx: next = {n{1b0}} ;
4b01xx: next = out + 1b1 ;
4b001x: next = out - 1b1 ;
4b0001: next = in ;
default: next = out ;
endcase
end
endmodule
his code is fairl! eas! "o read excep" "ha" i" conca"ena"es all of "he &i"s of "he con"rol +rs"' $p' do#n' load, in"o
one signal and "hen does a case on "hem. -nders"anding #ha" "he .)&001x: case is re/$ires "he reader "o look a"
#ha" "he case s"a"emen" is doing. 0ommen"s #o$ld help here' &$" #e)d like "o make i" simpler.
EE108a: Verilog Examples
Example 2:
his is "he same
1
$p*do#n co$n"er as "he code from "he co$rse reader' &$" i" is a lo" easier "o $nders"and:
module UDL_Count2(clk, rst, up, down, load, in, out) ;
parameter n = 4 ;
input clk, rst, up, down, load ;
input [n-1:0] in ;
output [n-1:0] out ;
wire [n-1:0] out ;
reg [n-1:0] next ;
DFF #(n) count(clk, next, out) ;
always@* begin
if (rst)
next = {n{1b0}};
else if (load)
next = in;
else if (up)
next = out + 1b1;
else if (down)
next = out 1b1;
else
next = out;
end
endmodule
%" is immedia"el! apparen" "ha" "he else if +do#n, case is #ha" happens #hen co$n"ing do#n' $nlike "he .)&001x
case in Example 1.
So #ha" is "he "radeoff here1 2ell' Example 3 is clearl! easier "o read and $nders"and' &$" Example 1 is more
explici" a&o$" #ha" logic sho$ld &e &$il". %n general !o$ sho$ld #ri"e "he mos" clear and eas! "o de&$g code !o$
can. 4o$ sho$ld onl! rever" "o explici"l! "elling "he "ools #ha" "o do +as in Example 1, #hen !o$ see "ha" 1, "he
"ools are doing a &ad 5o& #i"h !o$r code and 3, !o$)ve de"ermined "ha" i" is "ha" ch$nk of code "ha" reall!
ma""ers. 4o$ ma! #ell r$n in"o "his iss$e in la& . and "he final pro5ec"6
1
echnicall! "his version chooses "he res$l"s #i"h priori"!. +%.e.' if "he firs" if s"a"emen" is "r$e "hen i" #on)"
eval$a"e an! of "he follo#ing s"a"emen"s., 7o#ever' "ha" "his is exac"l! #ha" "he casex s"a"emen" in Example 1
is doing &! having "he leas" specific "o mos" specific cases lis"ed.
EE108a: Verilog Examples
Inferred state
2e)ve #arned !o$ several "imes a&o$" no" inferring la"ches in ee108a. Whenever you need state storage
(counters, FSMs, etc.) you must explicitly instantiate a flip flop from the provided ff_lib.v file. his file
explici"l! infers s"a"e "o genera"e a flip flop. o $nders"and #ha" !o$ need "o do "o avoid doing "his !o$rself'
le")s "ake a look inside "he flip flop li&rar!:
The EE108a Flip Flop Module:
module dff (d, clk, q);
parameter WIDTH = 1;
input clk;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @ (posedge clk)
q <= d;
endmodule
4o$ sho$ld no"e "#o "hings here "ha" !o$ haven)" seen &efore in Verilog. he firs" is "he 8 +posedge clk, and "he
second is "he 9: opera"or. +4o$ are no" allo#ed "o $se ei"her of "hese in ee108a so "ha")s #h! !o$ haven)" seen
"hem !e".,
So #ha" is "ha" al#a!s &lock doing1 2ell' &eca$se i" is no" $sing al#a!s 8; i" #ill onl! eval$a"e #hen 8
+posedge clk, is "r$e. his means "ha" on ever! rising edge of "he clock +and onl! on "he rising edges of "he
clock, "his &lock #ill &e eval$a"ed. he / 9: d s"a"emen" sa!s "ha" / #ill ge" "he las" val$e of d' and #ill onl!
change "o "ha" val$e #hen ever!"hing else is done &eing eval$a"ed. +ha" #a! "he o$"p$" of "he flip flop #ill
onl! change once even if "he inp$" changes m$l"iple "imes d$ring sim$la"ion.,
<o# "he real /$es"ion is #ha" is "he val$e of / #hen #e)re no" on "he rising edge of "he clock1 2ha" happens is
"ha" Verilog infers a la"ch for /' and remem&ers i"s val$e #henever "he clock is no" a rising edge. his is exac"l!
"he &ehavior #e #an" for a flip flop' &$" #e don)" #an" "his &ehavior an!#here else in o$r designs.
Mistakes that infer state
<o# "ha" #e)ve seen ho# "o &$ild a flip flop on p$rpose' le")s see ho# #e can &$ild "hem &! acciden".
Verilog #ill onl! infer s"a"e in !o$r design if !o$ don)" &$ild com&ina"ional logic in al#a!s &locks. ha" is' as
long as every single output is defined for every single combination of inputs you ill never infer state.
his sho$ld make sense: if all "he o$"p$"s are defined for all "he inp$"s "hen "he &lock is p$rel! com&ina"ional
+"he o$"p$"s onl! depend on "he c$rren" inp$"s,. %f an o$"p$" is no" defined for a given se" of inp$"s "hen Verilog
#ill infer a la"ch "o remem&er "he previo$s o$"p$" "o $se in "ha" case. 4o$ are no" allo#ed "o do "his ee108a and
#e #ill "ake off poin"s if !o$ do.
EE108a: Verilog Examples
(e")s look a" an example:
reg result;
reg status;
always @* begin
if (input_button) begin
status = 1b1;
result = 1b0;
end
else if (done_signal) begin
status = 1b0;
end
end
his code does no" define ever! o$"p$" for ever! com&ina"ion of inp$"s. here are "#o differen" pro&lems here.
he firs" is "ha" #e don)" define "he val$e of "he res$l" o$"p$" for "he case #here done=signal is "r$e. he second
is "ha" #e don)" define "he val$e of ei"her s"a"$s or res$l" in "he case #here &o"h done=signal and inp$"=&$""on
are false. >s a res$l" "his #ill infer la"ches.
he correc" code is as follo#s' #i"h changes $nderlined:
reg result;
reg status;
always @* begin
if (input_button) begin
status = 1b1;
result = 1b0;
end
else if (done_signal) begin
status = 1b0;
result = 1b1;
end
else begin
status = 1b0;
result = 1b0;
end
end
his version is p$rel! com&ina"ional &eca$se i" defines all o$"p$"s for all com&ina"ions of inp$"s. he same
"hing can happen #i"h a case s"a"emen" #here !o$ don)" incl$de a defa$l".
he &asic r$les "o avoid "his pro&lem are:
1. >l#a!s have an else for ever! if
3. >l#a!s define "he same se" of signals in all cases or if cla$ses
?. >l#a!s have a defa$l" for ever! case
.. >l#a!s read "he #arnings in @ilinx %SE a&o$" inferred la"ches.
4o$ #ill onl! see #arnings a&o$" "his in @ilinx &eca$se AodelSim ass$mes "ha" !o$ 5$s" #an"ed "o &$ild a la"ch
and so i" 5$s" gives !o$ one. 2hen !o$ r$n @ilinx !o$ need "o look a" "he o$"p$" from "he s!n"hesis s"ep and
make s$re !o$ don)" see an! #arnings excep" #here !o$ have ins"an"ia"ed a flip flop from "he ff=li&.v mod$le.
E.g.' "he follo#ing #arning is no" allo#ed in "his class:
EE108a: Verilog Examples