W

bus
RAM
MDR
16
LP_0
PROGRAM
COUNTER
LP_1
Inv_CLK
Ep
Cp
16
16
MAR
Lm
16
8
INPUT
inv_clK
Clock
mode
RUN
mode
Inv_CLK
Lr
Er
8
Lmd
Lmd1
Emd
Emd1
8 8_U
8
clock_mode
RUN mode
Li
!LT
CLK
Inv_CLK
29
CONTROL "U#
IN#TRUCTION
REGI#TER $
CONTROLLER
A
REGI#TER
ARIT!METIC
$ LOGIC UNIT
8
16
8
8
L%
E%
Inv_CLK
8
O&'_1
O&'_(
Eu!u
8
8
8_U
TEMPORAR)
REGI#TER
L'
E'_
E'_1
Inv_CLK
8
8
"
REGI#TER
L*
E*
Inv_CLK
16
C&
Cd
En
Inv_CLK
#TACK
O&'
Inv_CLK
8
8
DI#PLA)
OUTPUT
REGI#TER
"
E+ E+1
Inv_CLK
,LAG
REGI#TER
-
,LAG DI#PLA)