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SC( switched-capacitor)
circuits
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SCC
1) Building Blocks
Op-amps
Switch
Capacitor
Two Non-overlapping clocks
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scc
Capacitor
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scc
Switch


NMOS sw
TG sw
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scc
Op-amp

>high-freq
>high slew-rate
>low offset voltages
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scc
clocks
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scc
Resistor equivalence of a switched-capacitor


=>
=>
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scc
Advantages of Switched Capacitor Circuits

1.) Compatibility with CMOS technology
2.) Good accuracy of time constants
3.) Good voltage linearity
4.) Good temperature characteristic

Disadvantages of Switched Capacitor Circuits
1.) Experience clock feed-through (use of differential i/p-
o/p ckts overcomes this problem)
2.) Require a non-overlapping clock
3.) Bandwidth of the signal must be less than the clock
frequency
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scc
Integrators (parasitic dependent)
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Scc Integrators (parasitic dependent)
At end of phase 1
At end of phase 2
At end of phase 2=>
At the end of next phase 1
=>
On completion of a full cycle
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Scc Integrators (parasitic dependent)
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Scc Integrators (parasitic dependent)
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Scc Integrators (parasitic independent)

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Scc Integrators (parasitic independent)
<= non-inverting Integrator
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Scc Integrators (parasitic independent)
Prove that
And also parasitic insensitive
Assignment
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Scc (generalized circuit signal-flow-graph)
Applying superposition
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Scc (generalized circuit signal-flow-graph)
Combining them, total output=>

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Scc (1
st
order generalized filter)
C1
R2
R3
CA
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Scc 1
st
order generalized filter
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Scc 1
st
order generalized filter

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SCC (1
st
order generalized filter)
Problem
Design a 1
st
order SC-LPF with cutoff at
10kHz , zero gain at 50kHz and the dc-
gain of unity for switching frequency of 100
kHz.
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SCC (Biquad filter)
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SCC (Biquad filter)
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SCC (Biquad filter)

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SCC (Biquad filter)