1

1
2
2
3
3
4
4
D D
C C
B B
A A
Title
Number Revision Size
A4
Date: 2011-12-30 Sheet of
File: D:\OV7670+FIFO\7670.SchDoc Drawn By:
AVDD
A1
AGND
B3
VREF2
B2
DVDD
C1
VREF1
C2
DOVDD
F1
DOGND
F3
PWDN
B1
VSYNC
D1
STROBE
E2
SIO_D
A2
SIO_C
A3
D0
B4
D1
A4
D2
B5
D3
A5
D4
F5
D5
E5
D6
F4
D7
E4
HREF
D2
PCLK
E1
XCLK
E3
#RESET
F2
U2
OV7670
DI0
1
DI1
2
DI2
3
DI3
4
DI4
11
DI5
12
DI6
13
DI7
14
WE
5
GND
6
TST
7
WRST
8
WCK
9
VDD
10
DO7
15
DO6
16
DO5
17
DO4
18
DEC
19
RCK
20
RRST
21
OE
22
GND
23
RE
24
DO3
25
DO2
26
DO1
27
DO0
28
U3
AL422B
VIN VCC
SDA
SCL
VSYNC
HREF
PCLK
C_D0
C_D1
C_D2
C_D3
C_D4
C_D5
C_D6
C_D7
RRST
RCLK
WEN
XCLK
100nF
C2
100nF
C1
100nF
C3
100nF
C4
100nF
C5
AVDD
VCC
V1
V2
DVDD
100nF
C7
100nF
C8
0R
R3
OE
100nF
C6 10K
R4
1K R2
VIN VCC
100uF
C14
100nF
C13
VIN
1
GND
2
EN
3
BYT
4
OUT
5
U5
PAM3101DAB28
100nF
C12
2.8V
0R
R5
AVDD
100nF
C11
10uF
C10
SCL
SDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
P1
Header 2x10
VSYNC
WEN
HREF
OE
RCLK
D0
D1
D2
D3
D4
D5
D6
D7
VIN
SCCBclock
SCCBdata
Vertical synchronization
Line synchronization
FIFO write enable
FIFOchip enable
FIFOread clock
FIFOoutput data
FIFOoutput data
FIFO01$%2 FIFOoutput data
FIFO
FIFO
FIFO
FIFO
FIFOoutput data
3.3V+/- 0.05V
D0
D1
D2
D3
D4
D5
D6
D7
A
1
B
2
GND
3
VCC
5
Y
4
U1
SN74LVC1G00
VIN
NC
1
GND
2
VOUT
3
VCC
4
U4
X_24MHZ
VCC

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1 REV1.0
OV7670+AL422 Moduleun
uninstall R1 XCLK
VSYNC
RRST FIFO read address reset
XCK
VCC
10UF
C9
1k
R6
1k
R7
20K
R8
VCC